VirtRegMap: Preserve LiveDebugVariables

[arsenm]

Summary

This avoids recomputing it between regalloc runs.

[arsenm]

ping

[qcolombet]

lib/CodeGen/VirtRegMap.cpp

274 ↗

(On Diff #176842)

DebugVars may be nullptr IIRC what getAnalysisIfAvailable API does.

Make sure to test for it.

[arsenm]

Rebase and fix null check

[qcolombet]

llvm/lib/CodeGen/VirtRegMap.cpp

273

I think we should push the test on DebugVars before this block.
Otherwise

1. we won't clear the VRM and MRI when DebugVars are not present.
2. we won't emit the debug values all the time (but maybe that's ok?)

I.e.,

if (DebugVars)
  DebugVars->emitDebugValues(VRM).

if (ClearVirtRegs) {
  VRM->clearAllVirt();
  MRI->clearAllVirt();
}

[qcolombet]

llvm/lib/CodeGen/VirtRegMap.cpp

273

2. we won't emit the debug values all the time (but maybe that's ok?)

Looks like it would be okay, since you had:

if (!ClearVirtRegs)
   AU.addPreserved<LiveDebugVariables>();

Still, it is okay to assume ClearVirtRegs will be set eventually. E.g., what happens for WebAssembly?

[arsenm]

llvm/lib/CodeGen/VirtRegMap.cpp

273

I think this was to avoid double-emitting the debug values, since this will be run twice

[arsenm]

Add comment and test for double emission

[arsenm]

llvm/lib/CodeGen/VirtRegMap.cpp

273

Without this, the debug values end up getting emitted twice. It doesn't matter for webassembly since the allocator passes are never run

[arsenm]

ping

[arsenm]

ping

[arsenm]

808dc6f8663c4c0696fc6eaf998db61a06330266

llvm/lib/CodeGen/VirtRegMap.cpp

 class VirtRegRewriter : public MachineFunctionPass {
   MachineFunction *MF;
   const TargetRegisterInfo *TRI;
   const TargetInstrInfo *TII;
   MachineRegisterInfo *MRI;
   SlotIndexes *Indexes;
   LiveIntervals *LIS;
   VirtRegMap *VRM;
+  LiveDebugVariables *DebugVars;
   DenseSet<Register> RewriteRegs;
   bool ClearVirtRegs;
 
   void rewrite();
   void addMBBLiveIns();
   bool readsUndefSubreg(const MachineOperand &MO) const;
   void addLiveInsForSubRanges(const LiveInterval &LI, MCRegister PhysReg) const;
   void handleIdentityCopy(MachineInstr &MI);
void VirtRegRewriter::getAnalysisUsage(AnalysisUsage &AU) const {
   AU.addRequired<LiveIntervals>();
   AU.addPreserved<LiveIntervals>();
   AU.addRequired<SlotIndexes>();
   AU.addPreserved<SlotIndexes>();
   AU.addRequired<LiveDebugVariables>();
   AU.addRequired<LiveStacks>();
   AU.addPreserved<LiveStacks>();
   AU.addRequired<VirtRegMap>();
+
+  if (!ClearVirtRegs)
+    AU.addPreserved<LiveDebugVariables>();
+
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
 bool VirtRegRewriter::runOnMachineFunction(MachineFunction &fn) {
   MF = &fn;
   TRI = MF->getSubtarget().getRegisterInfo();
   TII = MF->getSubtarget().getInstrInfo();
   MRI = &MF->getRegInfo();
   Indexes = &getAnalysis<SlotIndexes>();
   LIS = &getAnalysis<LiveIntervals>();
   VRM = &getAnalysis<VirtRegMap>();
+  DebugVars = getAnalysisIfAvailable<LiveDebugVariables>();
   LLVM_DEBUG(dbgs() << "********** REWRITE VIRTUAL REGISTERS **********\n"
                     << "********** Function: " << MF->getName() << '\n');
   LLVM_DEBUG(VRM->dump());
 
   // Add kill flags while we still have virtual registers.
   LIS->addKillFlags(VRM);
 
   // Live-in lists on basic blocks are required for physregs.
   addMBBLiveIns();
 
   // Rewrite virtual registers.
   rewrite();
 
+  if (DebugVars && ClearVirtRegs) {
     // Write out new DBG_VALUE instructions.
-  getAnalysis<LiveDebugVariables>().emitDebugValues(VRM);
 
-  if (ClearVirtRegs) {
+    // We only do this if ClearVirtRegs is specified since this should be the
+    // final run of the pass and we don't want to emit them multiple times.
+    DebugVars->emitDebugValues(VRM);
+
     // All machine operands and other references to virtual registers have been
     // replaced. Remove the virtual registers and release all the transient data.
     VRM->clearAllVirt();
     MRI->clearVirtRegs();
   }
 
   return true;
 }

llvm/test/CodeGen/AMDGPU/debug-value.ll

bb28:                                             ; preds = %bb25, %bb21
   %tmp51 = extractelement <4 x float> %tmp42, i32 2
   %tmp52 = fmul float undef, undef
   %tmp53 = fadd float %tmp52, undef
   %tmp54 = fadd float %tmp51, %tmp53
   %tmp55 = extractelement <4 x float> %tmp49, i32 1
   %tmp56 = fmul float %tmp55, %tmp50
   %tmp57 = fmul float %tmp54, %tmp56
   %tmp58 = fdiv float %tmp57, 0.000000e+00
+  ; Make sure this isn't double emitted
+  ; CHECK-NOT: ;DEBUG_VALUE:
   ; CHECK: ;DEBUG_VALUE: foo:var <- [DW_OP_constu 1, DW_OP_swap, DW_OP_xderef]
+  ; CHECK-NOT: ;DEBUG_VALUE:
   call void @llvm.dbg.value(metadata <4 x float> %tmp29, metadata !3, metadata !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)) #2, !dbg !5
   %tmp59 = bitcast i64 %tmp35 to <2 x float>
   %tmp60 = insertelement <2 x float> undef, float %tmp58, i32 0
   %tmp61 = shufflevector <2 x float> %tmp60, <2 x float> undef, <2 x i32> zeroinitializer
   %tmp62 = fmul <2 x float> %tmp61, undef
   %tmp63 = fsub <2 x float> %tmp62, %tmp59
   %tmp64 = extractelement <2 x float> %tmp63, i64 0
   call void @eggs(float %tmp64) #2