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VirtRegMap: Support partially allocated virtual registers
Needs ReviewPublic

Authored by arsenm on Dec 4 2018, 10:10 AM.

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Reviewers
MatzeB
qcolombet
Summary

Don't assert if there are unassigned virtual registers.
Maintain LiveIntervals by removing the RegUnits for allocated
registers, since they should not longer be necessary.

One part I find somewhat questionable is the special
handling necessary for handleIdentityCopy. The LiveIntervals
for the relevant regunits needs to be removed.

Diff Detail

Event Timeline

arsenm created this revision.Dec 4 2018, 10:10 AM

The LiveIntervals for the relevant regunits needs to be removed.

Could you elaborate on why we need to remove these?

lib/CodeGen/VirtRegMap.cpp
624

Although that's unlikely to happen, we could imagine that another physical reg that share regunits with the one we are clearing is still relevant for subsequence allocation.

Put differently, why is this code valid?

In theory we may clear RegA's regunits, while they overlap with RegB's regunits and RegB's live interval needs to be valid.

arsenm marked an inline comment as done.Feb 25 2019, 9:32 AM
arsenm added inline comments.
lib/CodeGen/VirtRegMap.cpp
624

For the real use case I have, that can't happen. If these aren't removed, there will be a huge amount of work to maintain these accurately on the off chance this happens. I think this should just be documented as a restriction for the register class filter functions. If one regunit is disabled, any register class that has a register overlapping that regunit also needs to be disabled.

qcolombet added inline comments.Feb 25 2019, 9:43 AM
lib/CodeGen/VirtRegMap.cpp
624

I was thinking along the same line.
Could you think of some assert that we could use to make sure this doesn't happen?