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Differential D52487

[AArch64][v8.5A] Add MTE system instructions
ClosedPublic

Authored by olista01 on Sep 25 2018, 7:18 AM.

Details

Reviewers
javed.absar
t.p.northover
rengolin
SjoerdMeijer
ab
kcc
pcc
eugenis
vlad.tsyrklevich
Commits
rG4493f421acc5: [AArch64][v8.5A] Add MTE system instructions
rL343570: [AArch64][v8.5A] Add MTE system instructions
Summary

The Memory Tagging Extension adds system instructions for data cache
maintenance, implemented as new operands to the DC instruction.

Patch by Pablo Barrio!

Diff Detail

Repository
rL LLVM

Event Timeline

olista01 created this revision.Sep 25 2018, 7:18 AM
Herald added a reviewer: javed.absar. · View Herald TranscriptSep 25 2018, 7:18 AM
Herald added subscribers: llvm-commits, kristof.beyls. · View Herald Transcript
Harbormaster completed remote builds in B23080: Diff 166904.Sep 25 2018, 7:18 AM
olista01 added reviewers: t.p.northover, rengolin, SjoerdMeijer, ab, kcc, pcc, eugenis, vlad.tsyrklevich.Sep 25 2018, 7:30 AM
t.p.northover accepted this revision.Sep 27 2018, 6:08 AM

This looks fine.

This revision is now accepted and ready to land.Sep 27 2018, 6:08 AM
Closed by commit rL343570: [AArch64][v8.5A] Add MTE system instructions (authored by olista01). · Explain WhyOct 2 2018, 2:50 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
21 lines
AsmParser/
1 line
test/
MC/
AArch64/
60 lines
Disassembler/
AArch64/
60 lines

Diff 167904

llvm/trunk/lib/Target/AArch64/AArch64SystemOperands.td

Show First 20 Lines • Show All 102 Lines • ▼ Show 20 Lines
def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>; def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
let Requires = [{ {AArch64::HasV8_2aOps} }] in let Requires = [{ {AArch64::HasV8_2aOps} }] in
def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>; def : DC<"CVAP", 0b011, 0b0111, 0b1100, 0b001>;
let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in let Requires = [{ {AArch64::FeatureCacheDeepPersist} }] in
def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>; def : DC<"CVADP", 0b011, 0b0111, 0b1101, 0b001>;
let Requires = [{ {AArch64::FeatureMTE} }] in {
def : DC<"IGVAC", 0b000, 0b0111, 0b0110, 0b011>;
def : DC<"IGSW", 0b000, 0b0111, 0b0110, 0b100>;
def : DC<"CGSW", 0b000, 0b0111, 0b1010, 0b100>;
def : DC<"CIGSW", 0b000, 0b0111, 0b1110, 0b100>;
def : DC<"CGVAC", 0b011, 0b0111, 0b1010, 0b011>;
def : DC<"CGVAP", 0b011, 0b0111, 0b1100, 0b011>;
def : DC<"CGVADP", 0b011, 0b0111, 0b1101, 0b011>;
def : DC<"CIGVAC", 0b011, 0b0111, 0b1110, 0b011>;
def : DC<"GVA", 0b011, 0b0111, 0b0100, 0b011>;
def : DC<"IGDVAC", 0b000, 0b0111, 0b0110, 0b101>;
def : DC<"IGDSW", 0b000, 0b0111, 0b0110, 0b110>;
def : DC<"CGDSW", 0b000, 0b0111, 0b1010, 0b110>;
def : DC<"CIGDSW", 0b000, 0b0111, 0b1110, 0b110>;
def : DC<"CGDVAC", 0b011, 0b0111, 0b1010, 0b101>;
def : DC<"CGDVAP", 0b011, 0b0111, 0b1100, 0b101>;
def : DC<"CGDVADP", 0b011, 0b0111, 0b1101, 0b101>;
def : DC<"CIGDVAC", 0b011, 0b0111, 0b1110, 0b101>;
def : DC<"GZVA", 0b011, 0b0111, 0b0100, 0b100>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// IC (instruction cache maintenance) instruction options. // IC (instruction cache maintenance) instruction options.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2, class IC<string name, bits<3> op1, bits<4> crn, bits<4> crm, bits<3> op2,
bit needsreg> : SearchableTable { bit needsreg> : SearchableTable {
let SearchableFields = ["Name", "Encoding"]; let SearchableFields = ["Name", "Encoding"];
let EnumValueField = "Encoding"; let EnumValueField = "Encoding";
▲ Show 20 Lines • Show All 1,278 Lines • Show Last 20 Lines

llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

Show First 20 Lines • Show All 2,819 Lines • ▼ Show 20 Linesstatic const struct Extension {
{ "aes", {AArch64::FeatureAES} }, { "aes", {AArch64::FeatureAES} },
{ "crypto", {AArch64::FeatureCrypto} }, { "crypto", {AArch64::FeatureCrypto} },
{ "fp", {AArch64::FeatureFPARMv8} }, { "fp", {AArch64::FeatureFPARMv8} },
{ "simd", {AArch64::FeatureNEON} }, { "simd", {AArch64::FeatureNEON} },
{ "ras", {AArch64::FeatureRAS} }, { "ras", {AArch64::FeatureRAS} },
{ "lse", {AArch64::FeatureLSE} }, { "lse", {AArch64::FeatureLSE} },
{ "predctrl", {AArch64::FeaturePredCtrl} }, { "predctrl", {AArch64::FeaturePredCtrl} },
{ "ccdp", {AArch64::FeatureCacheDeepPersist} }, { "ccdp", {AArch64::FeatureCacheDeepPersist} },
{ "mte", {AArch64::FeatureMTE} },
// FIXME: Unsupported extensions // FIXME: Unsupported extensions
{ "pan", {} }, { "pan", {} },
{ "lor", {} }, { "lor", {} },
{ "rdma", {} }, { "rdma", {} },
{ "profile", {} }, { "profile", {} },
}; };
▲ Show 20 Lines • Show All 2,833 Lines • Show Last 20 Lines

llvm/trunk/test/MC/AArch64/armv8.5a-mte.s

// RUN: llvm-mc -triple aarch64 -show-encoding -mattr=+mte < %s | FileCheck %s
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=+v8.5a < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
// RUN: not llvm-mc -triple aarch64 -show-encoding -mattr=-mte < %s 2>&1 | FileCheck %s --check-prefix=NOMTE
dc igvac, x0
dc igsw, x1
dc cgsw, x2
dc cigsw, x3
dc cgvac, x4
dc cgvap, x5
dc cgvadp, x6
dc cigvac, x7
dc gva, x8
dc igdvac, x9
dc igdsw, x10
dc cgdsw, x11
dc cigdsw, x12
dc cgdvac, x13
dc cgdvap, x14
dc cgdvadp, x15
dc cigdvac, x16
dc gzva, x17
// CHECK: dc igvac, x0 // encoding: [0x60,0x76,0x08,0xd5]
// CHECK: dc igsw, x1 // encoding: [0x81,0x76,0x08,0xd5]
// CHECK: dc cgsw, x2 // encoding: [0x82,0x7a,0x08,0xd5]
// CHECK: dc cigsw, x3 // encoding: [0x83,0x7e,0x08,0xd5]
// CHECK: dc cgvac, x4 // encoding: [0x64,0x7a,0x0b,0xd5]
// CHECK: dc cgvap, x5 // encoding: [0x65,0x7c,0x0b,0xd5]
// CHECK: dc cgvadp, x6 // encoding: [0x66,0x7d,0x0b,0xd5]
// CHECK: dc cigvac, x7 // encoding: [0x67,0x7e,0x0b,0xd5]
// CHECK: dc gva, x8 // encoding: [0x68,0x74,0x0b,0xd5]
// CHECK: dc igdvac, x9 // encoding: [0xa9,0x76,0x08,0xd5]
// CHECK: dc igdsw, x10 // encoding: [0xca,0x76,0x08,0xd5]
// CHECK: dc cgdsw, x11 // encoding: [0xcb,0x7a,0x08,0xd5]
// CHECK: dc cigdsw, x12 // encoding: [0xcc,0x7e,0x08,0xd5]
// CHECK: dc cgdvac, x13 // encoding: [0xad,0x7a,0x0b,0xd5]
// CHECK: dc cgdvap, x14 // encoding: [0xae,0x7c,0x0b,0xd5]
// CHECK: dc cgdvadp, x15 // encoding: [0xaf,0x7d,0x0b,0xd5]
// CHECK: dc cigdvac, x16 // encoding: [0xb0,0x7e,0x0b,0xd5]
// CHECK: dc gzva, x17 // encoding: [0x91,0x74,0x0b,0xd5]
// NOMTE: DC IGVAC requires mte
// NOMTE: DC IGSW requires mte
// NOMTE: DC CGSW requires mte
// NOMTE: DC CIGSW requires mte
// NOMTE: DC CGVAC requires mte
// NOMTE: DC CGVAP requires mte
// NOMTE: DC CGVADP requires mte
// NOMTE: DC CIGVAC requires mte
// NOMTE: DC GVA requires mte
// NOMTE: DC IGDVAC requires mte
// NOMTE: DC IGDSW requires mte
// NOMTE: DC CGDSW requires mte
// NOMTE: DC CIGDSW requires mte
// NOMTE: DC CGDVAC requires mte
// NOMTE: DC CGDVAP requires mte
// NOMTE: DC CGDVADP requires mte
// NOMTE: DC CIGDVAC requires mte
// NOMTE: DC GZVA requires mte

llvm/trunk/test/MC/Disassembler/AArch64/armv8.5a-mte.txt

# RUN: llvm-mc -triple=aarch64 -mattr=+mte -disassemble < %s | FileCheck %s
# RUN: llvm-mc -triple=aarch64 -mattr=+v8.5a -disassemble < %s | FileCheck %s --check-prefix=NOMTE
# RUN: llvm-mc -triple=aarch64 -mattr=-mte -disassemble < %s | FileCheck %s --check-prefix=NOMTE
[0x60,0x76,0x08,0xd5]
[0x81,0x76,0x08,0xd5]
[0x82,0x7a,0x08,0xd5]
[0x83,0x7e,0x08,0xd5]
[0x64,0x7a,0x0b,0xd5]
[0x65,0x7c,0x0b,0xd5]
[0x66,0x7d,0x0b,0xd5]
[0x67,0x7e,0x0b,0xd5]
[0x68,0x74,0x0b,0xd5]
[0xa9,0x76,0x08,0xd5]
[0xca,0x76,0x08,0xd5]
[0xcb,0x7a,0x08,0xd5]
[0xcc,0x7e,0x08,0xd5]
[0xad,0x7a,0x0b,0xd5]
[0xae,0x7c,0x0b,0xd5]
[0xaf,0x7d,0x0b,0xd5]
[0xb0,0x7e,0x0b,0xd5]
[0x91,0x74,0x0b,0xd5]
# CHECK: dc igvac, x0
# CHECK: dc igsw, x1
# CHECK: dc cgsw, x2
# CHECK: dc cigsw, x3
# CHECK: dc cgvac, x4
# CHECK: dc cgvap, x5
# CHECK: dc cgvadp, x6
# CHECK: dc cigvac, x7
# CHECK: dc gva, x8
# CHECK: dc igdvac, x9
# CHECK: dc igdsw, x10
# CHECK: dc cgdsw, x11
# CHECK: dc cigdsw, x12
# CHECK: dc cgdvac, x13
# CHECK: dc cgdvap, x14
# CHECK: dc cgdvadp, x15
# CHECK: dc cigdvac, x16
# CHECK: dc gzva, x17
# NOMTE: sys #0, c7, c6, #3, x0
# NOMTE: sys #0, c7, c6, #4, x1
# NOMTE: sys #0, c7, c10, #4, x2
# NOMTE: sys #0, c7, c14, #4, x3
# NOMTE: sys #3, c7, c10, #3, x4
# NOMTE: sys #3, c7, c12, #3, x5
# NOMTE: sys #3, c7, c13, #3, x6
# NOMTE: sys #3, c7, c14, #3, x7
# NOMTE: sys #3, c7, c4, #3, x8
# NOMTE: sys #0, c7, c6, #5, x9
# NOMTE: sys #0, c7, c6, #6, x10
# NOMTE: sys #0, c7, c10, #6, x11
# NOMTE: sys #0, c7, c14, #6, x12
# NOMTE: sys #3, c7, c10, #5, x13
# NOMTE: sys #3, c7, c12, #5, x14
# NOMTE: sys #3, c7, c13, #5, x15
# NOMTE: sys #3, c7, c14, #5, x16
# NOMTE: sys #3, c7, c4, #4, x17