[RISCV] Implment pseudo instructions for load/store from a symbol address.

[kito-cheng]

Summary

Those pseudo-instructions are making load/store instructions able to load/store from/to a symbol, and its always using PC-relative addressing to generating a symbol address.

[kito-cheng]

• Add default case in switch.

[rogfer01]

Hi, thanks a lot for the patch. A few comments inline.

Could you add some negative tests so the instructions reject symbols that are not bare?

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

995

You will need to extend this case otherwise symbols named like registers fail to parse. I ran into this same problem! :)

That said, maybe we want to rethink this because your change adds a bunch of pseudos to this case.

t.s:1:8: error: immediate must be an integer in the range [-2048, 2047]
lb a0, zero
       ^
t.s:2:8: error: immediate must be an integer in the range [-2048, 2047]
sb a3, zero, a1
       ^

1252

Suggestion: what about renaming it emitLoadSymbolAddressHi, it might look like the full symbol address will be computed otherwise. Then you can rename the new emitLoadWithSymbol to just emitLoadSymbol.

[kito-cheng]

Changes:

• Rename functions
  • emitLoadSymbolAddress -> emitLoadSymbolAddressHi
  • emitLoadWithSymbol -> emitLoadSymbol
  • emitStoreWithSymbol -> emitStoreSymbol
• Return shouldForceImediateOperand to true for new pseudo instructions.
• Add negative test

[kito-cheng]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

995

Thanks, I was worried it will not work for those pseudo load/store, because the have another non-pseudo version, but it seems work fine :)

1252

Thanks your suggestion, naming is always hard to me :P

[rogfer01]

Thanks for the update @kito-cheng . Some more comments inline as the change is propagating a mistake of mine I introduced in rL339314 (fixed in rL339654).

You may have to rebase the patch. Apologies.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1264

This introduces the same bug I introduced in my earlier patch (fixed in rL339654). The easiest way to avoid it is to use MCInstBuilder as an argument of a function call.

1289

Ditto.

1326

Ditto.

1361

Ditto.

[kito-cheng]

Changes:

• Rebase.

[kito-cheng]

Hi Roger:

Thanks, I don't know can't do that too, it teach me a lesson :)

[asb]

• I'd like to find a solution that doesn't get rid of the helpful error reporting we currently have for load/store. Downgrading all errors to just "invalid operand for instruction" is an unfortunate regression
• The F/D load/store are wrong as this patch has them accepting GPRs rather than FPR32/FPR64. The outs for PseudoSTORE also has a mistake
• We no longer have the shouldForceImmediate logic because associating custom parsers with operands was found to be superior. From some playing with a modified version of this patch it looks like more logic is needed to get these aliases to parse though...

I think defining the load/store classes like this makes sense:

class PseudoLoadSym<RegisterClass rdty, string opcodestr>
    : Pseudo<(outs rdty:$rd), (ins bare_symbol:$addr), [],
              opcodestr, "$rd, $addr"> {
  let hasSideEffects = 0;
  let mayLoad = 1;
  let mayStore = 0;
  let isAsmParserOnly = 1;
}

class PseudoStoreSym<RegisterClass rs1ty, string opcodestr>
    : Pseudo<(outs GPR:$tmp), (ins rs1ty:$rs1, bare_symbol:$addr), [],
              opcodestr, "$rs1, $addr, $tmp"> {
  let hasSideEffects = 0;
  let mayLoad = 0;
  let mayStore = 1;
  let isAsmParserOnly = 1;
}

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1252

It strikes me that, apart from choosing the opcode (add/load/store) and store having a temporary register, emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol all do exactly the same thing. Can we not move all that into emitLoadSymbolAddressHi, rename it appropriately (something like emitAuipcInstPair as an idea) and then remove emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol? Then processInstruction would look something like:

// ...
case RISCV::PseudoLLA:
  emitAuipcInstPair(Inst, RISCV::ADDI, IDLoc, Out);
  return false;
case RISCV::PseudoLB:
  emitAuipcInstPair(Inst, RISCV::LB, IDLoc, Out);
  return false;
// ...
case RISCV::PseudoSB:
  emitAuipcInstPair(Inst, RISCV::SB, IDLoc, Out);
  return false;
// ...

Note that Inst.getNumOperands() tells you whether there is a temporary register to use.

Alternatively, you can make emitAuipcInstPair take unsigned Opcode, MCOperand DestReg, MCOperand TmpReg, MCExpr *Symbol, SMLoc IDLoc, MCStreamer &Out and keep your wrappers, but their only job is to unpack DestReg, Symbol and TmpReg (set to DestReg for add/load). I'd still push the opcode selection out into processInstruction as you already have to enumerate the pseudo opcodes there. Then you'd have something like:

void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
                                          MCStreamer &Out) {
  // The local load address pseudo-instruction "lla" is used in PC-relative
  // addressing of symbols:
  //   lla rdest, symbol
  // expands to
  //   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
  //             ADDI rdest, %pcrel_lo(TmpLabel)
  MCOperand DestReg = Inst.getOperand(0);
  const MCExpr *Symbol = Inst.getOperand(1).getExpr();
  emitAuipcInstPair(RISCV::ADDI, DestReg, DestReg, Symbol, IDLoc, Out);
}

void RISCVAsmParser::emitLoadSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
                                    MCStreamer &Out) {
  // The load pseudo-instruction does a pc-relative load with
  // a symbol.
  //
  // The expansion looks like this
  //
  //   TmpLabel: AUIPC rd, %pcrel_hi(symbol)
  //             LX    rd, %pcrel_lo(TmpLabel)(rd)
  MCOperand DestReg = Inst.getOperand(0);
  const MCExpr *Symbol = Inst.getOperand(1).getExpr();
  emitAuipcInstPair(Opcode, DestReg, DestReg, Symbol, IDLoc, Out);
}

void RISCVAsmParser::emitStoreSymbol(MCInst &Inst, unsigned Opcode, SMLoc IDLoc,
                                    MCStreamer &Out) {
  // The store pseudo-instruction does a pc-relative store with
  // a symbol.
  //
  // The expansion looks like this
  //
  //   TmpLabel: AUIPC tmp, %pcrel_hi(symbol)
  //             SX    rd, %pcrel_lo(TmpLabel)(tmp)
  MCOperand DestReg = Inst.getOperand(0);
  MCOperand TmpReg = Inst.getOperand(1);
  const MCExpr *Symbol = Inst.getOperand(2).getExpr();
  emitAuipcInstPair(Opcode, DestReg, TmpReg, Symbol, IDLoc, Out);
}

Although we can be smart and distinguish between stores and non-stores as described above, I'm actually leaning towards this one as it's a bit more explicit, clearer, and will catch cases where we do something stupid (e.g. stores without a temporary register).

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1343

Further investigation reveals that, for GNU as, the symbol is still Operands[1], and the temporary register is Operands[2], i.e. sw a0, foo, t0.

[kito-cheng]

Changes:

• Merge emitLoadLocalAddress/emitLoadSymbol/emitStoreSymbol
• Fix wrong operand type and syntax for floating point load instruction.

However this item is still a kind of regression:

• Downgrading all errors to just "invalid operand for instruction" is an unfortunate regression

[kito-cheng]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1343

The order of Operands not literally order in the asm syntax, it's ordered by (outs) (ins) in the pattern, it seems a little counter-intuitive here.

[kito-cheng]

Changes:

• Add missing tests

[apazos]

Just noted that this is failing:

"sw zero, (a0)"
<stdin>:1:15: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
sw zero, (a0)

^

We should also accept it as "sw zero, 0(a0)".
I verified GNU accepts it.

[jrtc27]

In D50496#1358355, @apazos wrote:

Just noted that this is failing:

"sw zero, (a0)"   
<stdin>:1:15: error: operand must be a symbol with %lo/%pcrel_lo modifier or an integer in the range [-2048, 2047]
sw      zero, (a0)
              ^

We should also accept it as sw zero, 0(a0).
I verified GNU accepts it.

[To clarify, we only accept 0(a0), whereas GNU as will also accept (a0) as having an implicit zero immediate.]

Yes; I have a local patch to add aliases with a missing immediate offset for all the IFDC loads/stores. I have a bunch of patch tidying, updating and submitting to do but it's on my list. However, such support is unrelated to this revision, which is all about expanding pseudo-instructions that use symbols.

[lewis-revill]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1252

Can this implementation of emitAuipcInstPair be brought in line with the same function as implemented in D55325, or vice-versa? I would prefer @jrtc27's second suggestion here as has been implemented in D55325, simply because emitLoadAddress requires a wrapper anyway, and emitLoadLocalAddress would have to be re-added in that patch if it were to be deleted here.

[lewis-revill]

This patch doesnt interact well with instructions like sw a3, CONST(a4) introduced by D52298. Looks like MatchOperandParserImpl is happy to match the 'CONST' as a bare symbol for the pseudo before parseImmediate can be called. Perhaps one way to fix it is to have parseBareSymbol check for a trailing parenthesis?

[lewis-revill]

test/MC/RISCV/rvi-pseudos-invalid.s

10

Typo 'few'

[kito-cheng]

Changes:

• Fix parseBareSymbol with a constant symbols.
• Rebase to D55325

[apazos]

The patch is not applying cleanly due to the added test/MC/RISCV/rv64i-pseudos.s which was first added in https://reviews.llvm.org/D55325

[kito-cheng]

Changes:

• Update test/MC/RISCV/rvi-pseudos-invalid.s

[asb]

This looks good to me, thanks! Just a few minor comments inline.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

933

Should be Tok and I don't think this is a good case for using auto (see https://llvm.org/docs/CodingStandards.html#use-auto-type-deduction-to-make-code-more-readable). AsmToken Tok = getLexer().getTok(); would IMHO be more readable and in line with the style used elsewhere in LLVM.

934

const MCExpr *V =

lib/Target/RISCV/RISCVInstrFormats.td

111

It would be good to add a comment here to indicate that these are used for load/store to a symbol address.

[asb]

I believe the pre-requisite patches for this are now committed, so please go ahead and commit once you've addressed the minor nits in my previous review. Thanks!

[jrtc27]

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

1296

Extra blank line is not necessary

1308

Typo: should be SymbolOpIdx

1390

The most common convention in the code base by my limited grepping is /*HasTmpReg=*/false; that's certainly most common in the RISC-V backend.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

class RISCVAsmParser : public MCTargetAsmParser {
   // Helper to actually emit an instruction to the MCStreamer. Also, when
   // possible, compression of the instruction is performed.
   void emitToStreamer(MCStreamer &S, const MCInst &Inst);
 
   // Helper to emit a combination of LUI, ADDI(W), and SLLI instructions that
   // synthesize the desired immedate value into the destination register.
   void emitLoadImm(unsigned DestReg, int64_t Value, MCStreamer &Out);
 
+  // Helper to emit load symbol address.
+  const MCExpr *emitLoadSymbolAddressHi(const MCExpr *Symbol,
+                                        const MCOperand &TmpReg,
+                                        MCStreamer &Out);
+
   // Helper to emit pseudo instruction "lla" used in PC-rel addressing.
   void emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
 
+  // Helper to emit pseudo instruction lb/lbu/lh/lhu/lw/lwu/ld
+  // that does a load with symbol.
+  void emitLoadSymbol(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
+
+  // Helper to emit pseudo instruction sb/sh/sw/sd
+  // that does a store with symbol.
+  void emitStoreSymbol(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
+
   /// Helper for processing MC instructions that have been successfully matched
   /// by MatchAndEmitInstruction. Modifications to the emitted instructions,
   /// like the expansion of pseudo instructions (e.g., "li"), can be performed
   /// in this method.
   bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out);
 
 // Auto-generated instruction matching functions
 #define GET_ASSEMBLER_HEADER
if (getParser().parseParenExpression(SubExpr, E)) {
     return MatchOperand_ParseFail;
   }
 
   const MCExpr *ModExpr = RISCVMCExpr::create(SubExpr, VK, getContext());
   Operands.push_back(RISCVOperand::createImm(ModExpr, S, E, isRV64()));
   return MatchOperand_Success;
 }
 
 OperandMatchResultTy
 RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
   if (getLexer().isNot(AsmToken::LParen)) {
     Error(getLoc(), "expected '('");
     return MatchOperand_ParseFail;
   }
 
   getParser().Lex(); // Eat '('
   Operands.push_back(RISCVOperand::createToken("(", getLoc(), isRV64()));
 

 static bool shouldForceImediateOperand(StringRef Name, unsigned OperandIdx) {
   // FIXME: This may not scale so perhaps we want to use a data-driven approach
   // instead.
   switch (OperandIdx) {
   case 0:
     // call imm
     // tail imm
     return Name == "tail" || Name == "call";
   case 1:
-    // lla rdest, imm
-    return Name == "lla";
+    // l[bhw][u] rdest, imm
+    // ld rdest, imm
+    // fl[wd] rdest, imm
+    // s[bhw] rdest, imm, tmp
+    // fs[wd] rdest, imm, tmp
+    // lla imm
+    return StringSwitch<bool>(Name)
+        .Case("lb", true)
+        .Case("lbu", true)
+        .Case("lh", true)
+        .Case("lhu", true)
+        .Case("lw", true)
+        .Case("lwu", true)
+        .Case("ld", true)
+        .Case("flw", true)
+        .Case("fld", true)
+        .Case("sb", true)
+        .Case("sh", true)
+        .Case("sw", true)
+        .Case("sd", true)
+        .Case("fsw", true)
+        .Case("fsd", true)
+        .Case("lla", true)
+        .Default(false);
   default:
     return false;
   }
 }
 
 bool RISCVAsmParser::ParseInstruction(ParseInstructionInfo &Info,
                                       StringRef Name, SMLoc NameLoc,
                                       OperandVector &Operands) {
void RISCVAsmParser::emitLoadImm(unsigned DestReg, int64_t Value,
 
   if (Lo12)
     emitToStreamer(Out, MCInstBuilder(RISCV::ADDI)
                             .addReg(DestReg)
                             .addReg(DestReg)
                             .addImm(Lo12));
 }
 
-void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
+/// Emit top half of the load symbol address code sequence.
+/// and return the reference of TmpLabel to the symbol address.
+///
+/// This function will emit a TmpLabel and an auipc instruction:
+///   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
+const MCExpr *RISCVAsmParser::emitLoadSymbolAddressHi(const MCExpr *Symbol,
+                                                      const MCOperand &TmpReg,
                                                       MCStreamer &Out) {
-  // The local load address pseudo-instruction "lla" is used in PC-relative
-  // addressing of symbols:
-  //   lla rdest, symbol
-  // expands to
-  //   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
-  //             ADDI rdest, %pcrel_lo(TmpLabel)
   MCContext &Ctx = getContext();
 
   MCSymbol *TmpLabel = Ctx.createTempSymbol(
       "pcrel_hi", /* AlwaysAddSuffix */ true, /* CanBeUnnamed */ false);
   Out.EmitLabel(TmpLabel);
 
-  MCOperand DestReg = Inst.getOperand(0);
-  const RISCVMCExpr *Symbol = RISCVMCExpr::create(
-      Inst.getOperand(1).getExpr(), RISCVMCExpr::VK_RISCV_PCREL_HI, Ctx);
+  const RISCVMCExpr *SymbolExpr = RISCVMCExpr::create(
+      Symbol, RISCVMCExpr::VK_RISCV_PCREL_HI, Ctx);
 
   MCInst &AUIPC =
-      MCInstBuilder(RISCV::AUIPC).addOperand(DestReg).addExpr(Symbol);
+      MCInstBuilder(RISCV::AUIPC).addOperand(TmpReg).addExpr(SymbolExpr);
   emitToStreamer(Out, AUIPC);
 
   const MCExpr *RefToLinkTmpLabel =
       RISCVMCExpr::create(MCSymbolRefExpr::create(TmpLabel, Ctx),
                           RISCVMCExpr::VK_RISCV_PCREL_LO, Ctx);
 
+  return RefToLinkTmpLabel;
+}
+
+void RISCVAsmParser::emitLoadLocalAddress(MCInst &Inst, SMLoc IDLoc,
+                                          MCStreamer &Out) {
+  // The local load address pseudo-instruction "lla" is used in PC-relative
+  // addressing of symbols:
+  //   lla rdest, symbol
+  // expands to
+  //   TmpLabel: AUIPC rdest, %pcrel_hi(symbol)
+  //             ADDI rdest, %pcrel_lo(TmpLabel)
+  MCOperand DestReg = Inst.getOperand(0);
+  const MCExpr *Symbol = Inst.getOperand(1).getExpr();
+
+  const MCExpr *RefToLinkTmpLabel =
+      emitLoadSymbolAddressHi(Symbol, DestReg, Out);
+
   MCInst &ADDI = MCInstBuilder(RISCV::ADDI)
                      .addOperand(DestReg)
                      .addOperand(DestReg)
                      .addExpr(RefToLinkTmpLabel);
   emitToStreamer(Out, ADDI);
 }
 
+void RISCVAsmParser::emitLoadSymbol(MCInst &Inst, SMLoc IDLoc,
+                                    MCStreamer &Out) {
+  // The load pseudo-instruction does a pc-relative load with
+  // a symbol.
+  //
+  // The expansion looks like this
+  //
+  //   TmpLabel: AUIPC rd, %pcrel_hi(symbol)
+  //             LX    rd, %pcrel_lo(TmpLabel)(rd)
+  MCOperand DestReg = Inst.getOperand(0);
+  const MCExpr *Symbol = Inst.getOperand(1).getExpr();
+
+  const MCExpr *RefToLinkTmpLabel =
+      emitLoadSymbolAddressHi(Symbol, DestReg, Out);
+
+  unsigned Opcode;
+  switch (Inst.getOpcode()) {
+  default:
+    llvm_unreachable("Unexpected opcode!");
+  case RISCV::PseudoLB:  Opcode = RISCV::LB;  break;
+  case RISCV::PseudoLBU: Opcode = RISCV::LBU; break;
+  case RISCV::PseudoLH:  Opcode = RISCV::LH;  break;
+  case RISCV::PseudoLHU: Opcode = RISCV::LHU; break;
+  case RISCV::PseudoLW:  Opcode = RISCV::LW;  break;
+  case RISCV::PseudoLWU: Opcode = RISCV::LWU; break;
+  case RISCV::PseudoLD:  Opcode = RISCV::LD;  break;
+  case RISCV::PseudoFLW: Opcode = RISCV::FLW; break;
+  case RISCV::PseudoFLD: Opcode = RISCV::FLD; break;
+  }
+
+  MCInst &LOAD = MCInstBuilder(Opcode)
+                    .addOperand(DestReg)
+                    .addOperand(DestReg)
+                    .addExpr(RefToLinkTmpLabel);
+  emitToStreamer(Out, LOAD);
+}
+
+void RISCVAsmParser::emitStoreSymbol(MCInst &Inst, SMLoc IDLoc,
+                                     MCStreamer &Out) {
+  // The store pseudo-instruction does a pc-relative store with
+  // a symbol.
+  //
+  // The expansion looks like this
+  //
+  //   TmpLabel: AUIPC tmp, %pcrel_hi(symbol)
+  //             SX    rd, %pcrel_lo(TmpLabel)(tmp)
+  MCOperand DestReg = Inst.getOperand(0);
+  MCOperand TmpReg = Inst.getOperand(1);
+  const MCExpr *Symbol = Inst.getOperand(2).getExpr();
+
+  const MCExpr *RefToLinkTmpLabel =
+      emitLoadSymbolAddressHi(Symbol, TmpReg, Out);
+
+  unsigned Opcode;
+  switch (Inst.getOpcode()) {
+  default:
+    llvm_unreachable("Unexpected opcode!");
+  case RISCV::PseudoSB:  Opcode = RISCV::SB;  break;
+  case RISCV::PseudoSH:  Opcode = RISCV::SH;  break;
+  case RISCV::PseudoSW:  Opcode = RISCV::SW;  break;
+  case RISCV::PseudoSD:  Opcode = RISCV::SD;  break;
+  case RISCV::PseudoFSW: Opcode = RISCV::FSW; break;
+  case RISCV::PseudoFSD: Opcode = RISCV::FSD; break;
+  }
+
+  MCInst &STORE = MCInstBuilder(Opcode)
+                    .addOperand(DestReg)
+                    .addOperand(TmpReg)
+                    .addExpr(RefToLinkTmpLabel);
+  emitToStreamer(Out, STORE);
+}
+
 bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
                                         MCStreamer &Out) {
   Inst.setLoc(IDLoc);
 
-  if (Inst.getOpcode() == RISCV::PseudoLI) {
+  switch (Inst.getOpcode()) {
+  default:
+    break;
+  case RISCV::PseudoLI: {
     auto Reg = Inst.getOperand(0).getReg();
     int64_t Imm = Inst.getOperand(1).getImm();
     // On RV32 the immediate here can either be a signed or an unsigned
     // 32-bit number. Sign extension has to be performed to ensure that Imm
     // represents the expected signed 64-bit number.
     if (!isRV64())
       Imm = SignExtend64<32>(Imm);
     emitLoadImm(Reg, Imm, Out);
     return false;
-  } else if (Inst.getOpcode() == RISCV::PseudoLLA) {
+  }
+  case RISCV::PseudoLLA:
     emitLoadLocalAddress(Inst, IDLoc, Out);
     return false;
+  case RISCV::PseudoLB:
+  case RISCV::PseudoLBU:
+  case RISCV::PseudoLH:
+  case RISCV::PseudoLHU:
+  case RISCV::PseudoLW:
+  case RISCV::PseudoLWU:
+  case RISCV::PseudoLD:
+  case RISCV::PseudoFLW:
+  case RISCV::PseudoFLD:
+    emitLoadSymbol(Inst, IDLoc, Out);
+    return false;
+  case RISCV::PseudoSB:
+  case RISCV::PseudoSH:
+  case RISCV::PseudoSW:
+  case RISCV::PseudoSD:
+  case RISCV::PseudoFSW:
+  case RISCV::PseudoFSD:
+    emitStoreSymbol(Inst, IDLoc, Out);
+    return false;
   }
 
   emitToStreamer(Out, Inst);
   return false;
 }
 
 extern "C" void LLVMInitializeRISCVAsmParser() {
   RegisterMCAsmParser<RISCVAsmParser> X(getTheRISCV32Target());
   RegisterMCAsmParser<RISCVAsmParser> Y(getTheRISCV64Target());
 }

lib/Target/RISCV/RISCVInstrFormats.td

 
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {
   let isPseudo = 1;
   let isCodeGenOnly = 1;
 }
 
+// Pseudo load instructions.
+class PseudoLOAD<string opcodestr>
+    : Pseudo<(outs GPR:$rd), (ins bare_symbol:$addr), [], opcodestr, "$rd, $addr"> {
+  let hasSideEffects = 0;
+  let mayLoad = 1;
+  let mayStore = 0;
+  let isCodeGenOnly = 0;
+  let isAsmParserOnly = 1;
+}
+
+// Pseudo store instructions.
+class PseudoSTORE<string opcodestr>
+    : Pseudo<(outs GPR:$rs, GPR:$tmp), (ins bare_symbol:$addr), [], opcodestr, "$rs, $addr, $tmp"> {
+  let hasSideEffects = 0;
+  let mayLoad = 0;
+  let mayStore = 1;
+  let isCodeGenOnly = 0;
+  let isAsmParserOnly = 1;
+}
+
 // Instruction formats are listed in the order they appear in the RISC-V
 // instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
 // RVInstRAtomic) sorted alphabetically.
 
 class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
               dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;

lib/Target/RISCV/RISCVInstrInfo.td

 //===-- RISCVInstrInfo.td - Target Description for RISCV ---*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the RISC-V instructions in TableGen format.
 //
 //===----------------------------------------------------------------------===//
 
-include "RISCVInstrFormats.td"
-
 //===----------------------------------------------------------------------===//
 // RISC-V specific DAG Nodes.
 //===----------------------------------------------------------------------===//
 
 def SDT_RISCVCall         : SDTypeProfile<0, -1, [SDTCisVT<0, XLenVT>]>;
 def SDT_RISCVCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>,
                                             SDTCisVT<1, i32>]>;
 def SDT_RISCVCallSeqEnd   : SDCallSeqEnd<[SDTCisVT<0, i32>,

 // 11 is 1, to compensate for the low 12 bits in the matching immediate addi
 // or ld/st being negative.
 def HI20 : SDNodeXForm<imm, [{
   return CurDAG->getTargetConstant(((N->getZExtValue()+0x800) >> 12) & 0xfffff,
                                    SDLoc(N), N->getValueType(0));
 }]>;
 
 //===----------------------------------------------------------------------===//
+// Instruction Formats
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormats.td"
+
+//===----------------------------------------------------------------------===//
 // Instruction Class Templates
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class BranchCC_rri<bits<3> funct3, string opcodestr>
     : RVInstB<funct3, OPC_BRANCH, (outs),
               (ins GPR:$rs1, GPR:$rs2, simm13_lsb0:$imm12),
               opcodestr, "$rs1, $rs2, $imm12"> {
def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
   let rd = 0;
 }
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 // TODO la
-// TODO lb lh lw
-// TODO RV64I: ld
-// TODO sb sh sw
-// TODO RV64I: sd
 
 def : InstAlias<"nop",           (ADDI      X0,      X0,       0)>;
 
 // Note that the size is 32 because up to 8 32-bit instructions are needed to
 // generate an arbitrary 64-bit immediate. However, the size does not really
 // matter since PseudoLI is currently only used in the AsmParser where it gets
 // expanded to real instructions immediately.
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 32,
     isCodeGenOnly = 0, isAsmParserOnly = 1 in
 def PseudoLI : Pseudo<(outs GPR:$rd), (ins ixlenimm:$imm), [],
                       "li", "$rd, $imm">;
 
+def PseudoLB  : PseudoLOAD<"lb">;
+def PseudoLBU : PseudoLOAD<"lbu">;
+def PseudoLH  : PseudoLOAD<"lh">;
+def PseudoLHU : PseudoLOAD<"lhu">;
+def PseudoLW  : PseudoLOAD<"lw">;
+
+def PseudoSB  : PseudoSTORE<"sb">;
+def PseudoSH  : PseudoSTORE<"sh">;
+def PseudoSW  : PseudoSTORE<"sw">;
+
+let Predicates = [IsRV64] in {
+def PseudoLWU : PseudoLOAD<"lwu">;
+def PseudoLD  : PseudoLOAD<"ld">;
+def PseudoSD  : PseudoSTORE<"sd">;
+} // Predicates = [IsRV64]
+
 def : InstAlias<"mv $rd, $rs",   (ADDI GPR:$rd, GPR:$rs,       0)>;
 def : InstAlias<"not $rd, $rs",  (XORI GPR:$rd, GPR:$rs,      -1)>;
 def : InstAlias<"neg $rd, $rs",  (SUB  GPR:$rd,      X0, GPR:$rs)>;
 
 let Predicates = [IsRV64] in {
 def : InstAlias<"negw $rd, $rs",   (SUBW  GPR:$rd,      X0, GPR:$rs)>;
 def : InstAlias<"sext.w $rd, $rs", (ADDIW GPR:$rd, GPR:$rs,       0)>;
 } // Predicates = [IsRV64]

lib/Target/RISCV/RISCVInstrInfoD.td

 }
 } // Predicates = [HasStdExtD, IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtD] in {
-// TODO fld
-// TODO fsd
-
 def : InstAlias<"fmv.d $rd, $rs",  (FSGNJ_D  FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fabs.d $rd, $rs", (FSGNJX_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 def : InstAlias<"fneg.d $rd, $rs", (FSGNJN_D FPR64:$rd, FPR64:$rs, FPR64:$rs)>;
 
 // fgt.d/fge.d are recognised by the GNU assembler but the canonical
 // flt.d/fle.d forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.d $rd, $rs, $rt",
                 (FLT_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
 def : InstAlias<"fge.d $rd, $rs, $rt",
                 (FLE_D GPR:$rd, FPR64:$rt, FPR64:$rs), 0>;
+
+def PseudoFLD  : PseudoLOAD<"fld">;
+def PseudoFSD  : PseudoSTORE<"fsd">;
 } // Predicates = [HasStdExtD]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 class PatFpr64Fpr64<SDPatternOperator OpNode, RVInstR Inst>
     : Pat<(OpNode FPR64:$rs1, FPR64:$rs2), (Inst $rs1, $rs2)>;

lib/Target/RISCV/RISCVInstrInfoF.td

 def           : FPUnaryOpDynFrmAlias<FCVT_S_LU, "fcvt.s.lu", FPR32, GPR>;
 } // Predicates = [HasStdExtF, IsRV64]
 
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtF] in {
-// TODO flw
-// TODO fsw
-
 def : InstAlias<"fmv.s $rd, $rs",  (FSGNJ_S  FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fabs.s $rd, $rs", (FSGNJX_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 def : InstAlias<"fneg.s $rd, $rs", (FSGNJN_S FPR32:$rd, FPR32:$rs, FPR32:$rs)>;
 
 // fgt.s/fge.s are recognised by the GNU assembler but the canonical
 // flt.s/fle.s forms will always be printed. Therefore, set a zero weight.
 def : InstAlias<"fgt.s $rd, $rs, $rt",
                 (FLT_S GPR:$rd, FPR32:$rt, FPR32:$rs), 0>;

 def : InstAlias<"fsflags $rs",        (CSRRW       X0, 0x001, GPR:$rs), 2>;
 def : InstAlias<"fsflagsi $rd, $imm", (CSRRWI GPR:$rd, 0x001, uimm5:$imm)>;
 def : InstAlias<"fsflagsi $imm",      (CSRRWI      X0, 0x001, uimm5:$imm), 2>;
 
 // fmv.w.x and fmv.x.w were previously known as fmv.s.x and fmv.x.s. Both
 // spellings should be supported by standard tools.
 def : MnemonicAlias<"fmv.s.x", "fmv.w.x">;
 def : MnemonicAlias<"fmv.x.s", "fmv.x.w">;
+
+def PseudoFLW  : PseudoLOAD<"flw">;
+def PseudoFSW  : PseudoSTORE<"fsw">;
 } // Predicates = [HasStdExtF]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 /// Generic pattern classes
 class PatFpr32Fpr32<SDPatternOperator OpNode, RVInstR Inst>

test/MC/RISCV/rv32d-invalid.s

 # RUN: not llvm-mc -triple riscv32 -mattr=+d < %s 2>&1 | FileCheck %s
 
 # Out of range immediates
 ## simm12
 fld ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
 fsd ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
 
 # Memory operand not formatted correctly
-fld ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
-fsd ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
+fld ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsd ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 # Invalid register names
 fld ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 fld ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
 fsgnjn.d fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
 # Integer registers where FP regs are expected
 fadd.d a2, a1, a0 # CHECK: :[[@LINE]]:8: error: invalid operand for instruction
 
 # FP registers where integer regs are expected
 fcvt.wu.d ft2, a1 # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

test/MC/RISCV/rv32f-invalid.s

 # RUN: not llvm-mc -triple riscv32 -mattr=+f < %s 2>&1 | FileCheck %s
 
 # Out of range immediates
 ## simm12
 flw ft1, -2049(a0) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
 fsw ft2, 2048(a1) # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
 
 # Memory operand not formatted correctly
-flw ft1, a0, -200 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
-fsw ft2, a1, 100 # CHECK: :[[@LINE]]:10: error: immediate must be an integer in the range [-2048, 2047]
+flw ft1, a0, -200 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
+fsw ft2, a1, 100 # CHECK: :[[@LINE]]:14: error: invalid operand for instruction
 
 # Invalid register names
 flw ft15, 100(a0) # CHECK: :[[@LINE]]:5: error: invalid operand for instruction
 flw ft1, 100(a10) # CHECK: :[[@LINE]]:14: error: expected register
 fsgnjn.s fa100, fa2, fa3 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
 # Integer registers where FP regs are expected
 fmv.x.w fs7, a2 # CHECK: :[[@LINE]]:9: error: invalid operand for instruction

test/MC/RISCV/rv32i-invalid.s

 xori sp, 22, 220 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 sub t0, t2, 1 # CHECK: :[[@LINE]]:13: error: invalid operand for instruction
 
 # Too many operands
 add ra, zero, zero, zero # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
 sltiu s2, s3, 0x50, 0x60 # CHECK: :[[@LINE]]:21: error: invalid operand for instruction
 
 # Memory operand not formatted correctly
-lw a4, a5, 111 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2048, 2047]
+lw a4, a5, 111 # CHECK: :[[@LINE]]:12: error: invalid operand for instruction
 
 # Too few operands
 ori a0, a1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 xor s2, s2 # CHECK: :[[@LINE]]:1: error: too few operands for instruction
 
 # Instruction not in the base ISA
 mul a4, ra, s0 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 amomaxu.w s5, s4, (s3) # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 fadd.s ft0, ft1, ft2 # CHECK: :[[@LINE]]:1: error: instruction use requires an option to be enabled
 
 # Using floating point registers when integer registers are expected
 addi a2, ft0, 24 # CHECK: :[[@LINE]]:10: error: invalid operand for instruction
 
 # fence.tso accepts no operands
 fence.tso rw, rw # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

test/MC/RISCV/rv64i-pseudos.s

+# RUN: llvm-mc %s -triple=riscv64 | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: lwu  a2, %pcrel_lo(.Lpcrel_hi0)(a2)
+lwu a2, a_symbol
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: ld  a3, %pcrel_lo(.Lpcrel_hi1)(a3)
+ld a3, a_symbol
+
+# CHECK: .Lpcrel_hi2:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sd  a3, %pcrel_lo(.Lpcrel_hi2)(a4)
+sd a3, a_symbol, a4

test/MC/RISCV/rvd-pseudos.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+d | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+d | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: fld  a2, %pcrel_lo(.Lpcrel_hi0)(a2)
+fld a2, a_symbol
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: fsd  a2, %pcrel_lo(.Lpcrel_hi1)(a3)
+fsd a2, a_symbol, a3

test/MC/RISCV/rvf-pseudos.s

+# RUN: llvm-mc %s -triple=riscv32 -mattr=+f | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+f | FileCheck %s
+
+# CHECK: .Lpcrel_hi0:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: flw  a2, %pcrel_lo(.Lpcrel_hi0)(a2)
+flw a2, a_symbol
+
+# CHECK: .Lpcrel_hi1:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: fsw  a2, %pcrel_lo(.Lpcrel_hi1)(a3)
+fsw a2, a_symbol, a3

test/MC/RISCV/rvi-pseudos-invalid.s

+# RUN: not llvm-mc -triple=riscv32 < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s
+
+# Non bare symbols must be rejected
+sw a2, %hi(a_symbol), a3 # CHECK: :[[@LINE]]:8: error: immediate must be an integer in the range [-2048, 2047]
+sw a2, %lo(a_symbol), a3 # CHECK: :[[@LINE]]:23: error: invalid operand for instruction
+sw a2, %lo(a_symbol)(a4), a3 # CHECK: :[[@LINE]]:27: error: invalid operand for instruction
+
+# Too fwe operands must be rejected
+sw a2, a_symbol # CHECK: :[[@LINE]]:1: error: too few operands for instruction

test/MC/RISCV/rvi-pseudos.s

 # CHECK: auipc a3, %pcrel_hi(ra)
 # CHECK: addi  a3, a3, %pcrel_lo(.Lpcrel_hi3)
 lla a3, ra
 
 # CHECK: .Lpcrel_hi4:
 # CHECK: auipc a4, %pcrel_hi(f1)
 # CHECK: addi  a4, a4, %pcrel_lo(.Lpcrel_hi4)
 lla a4, f1
+
+# CHECK: .Lpcrel_hi5:
+# CHECK: auipc a0, %pcrel_hi(a_symbol)
+# CHECK: lb  a0, %pcrel_lo(.Lpcrel_hi5)(a0)
+lb a0, a_symbol
+
+# CHECK: .Lpcrel_hi6:
+# CHECK: auipc a1, %pcrel_hi(a_symbol)
+# CHECK: lh  a1, %pcrel_lo(.Lpcrel_hi6)(a1)
+lh a1, a_symbol
+
+# CHECK: .Lpcrel_hi7:
+# CHECK: auipc a2, %pcrel_hi(a_symbol)
+# CHECK: lhu  a2, %pcrel_lo(.Lpcrel_hi7)(a2)
+lhu a2, a_symbol
+
+# CHECK: .Lpcrel_hi8:
+# CHECK: auipc a3, %pcrel_hi(a_symbol)
+# CHECK: lw  a3, %pcrel_lo(.Lpcrel_hi8)(a3)
+lw a3, a_symbol
+
+# CHECK: .Lpcrel_hi9:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sb  a3, %pcrel_lo(.Lpcrel_hi9)(a4)
+sb a3, a_symbol, a4
+
+# CHECK: .Lpcrel_hi10:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sh  a3, %pcrel_lo(.Lpcrel_hi10)(a4)
+sh a3, a_symbol, a4
+
+# CHECK: .Lpcrel_hi11:
+# CHECK: auipc a4, %pcrel_hi(a_symbol)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi11)(a4)
+sw a3, a_symbol, a4
+
+# Check that we can load the address of symbols that are spelled like a register
+# CHECK: .Lpcrel_hi12:
+# CHECK: auipc a2, %pcrel_hi(zero)
+# CHECK: lw  a2, %pcrel_lo(.Lpcrel_hi12)(a2)
+lw a2, zero
+
+# CHECK: .Lpcrel_hi13:
+# CHECK: auipc a4, %pcrel_hi(zero)
+# CHECK: sw  a3, %pcrel_lo(.Lpcrel_hi13)(a4)
+sw a3, zero, a4