AMDHSA Code Object v3 assembler syntax update

[scott.linder]

Summary

Update assembler syntax for code object v3 to match https://reviews.llvm.org/D47566

• Replace/rename most AMDGPU assembler directives/symbols and document them
• Provide more diagnostics (e.g. for values out of range, missing required values, repeated values, mismatching command-line options)

The new syntax should allow us to remain backwards compatible, even if the underlying descriptor changes.

[arsenm]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

243–246

Can we start omitting entries when they are the default value? One thing that's been bothering me for a while is how much junk always printed out

[scott.linder]

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

243–246

I think that is reasonable, the only caveat being that you might see fewer directives coming out than you explicitly provided (if you specify a default value explicitly). I will enumerate the directives and their default values somewhere and change this to only emit required and non-default values.

[scott.linder]

Do not output default values when printing .amdhsa_kernel directives

[scott.linder]

I missed reverting to the original AMDHSAKernelDescriptor.h

[kzhuravl]

include/llvm/Support/AMDHSAKernelDescriptor.h

153–154

Can this be moved to lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h/cpp?

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2631

Yes.

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

137

My guess would be yes for this one, since we do it in other similar places.

221

probably no, as our current directive *amdgpu_hsa_kernel* does not do that.

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

71

Can STI be made the first argument?

[scott.linder]

Address feedback

I am still not sure where "quote a string so that MC understands it" is; there is a static function PrintQuotedString in lib/MC/MCAsmStreamer.cpp that should maybe be moved somewhere else? For now I do what we do for other quoted strings (quote but not escape).

[kzhuravl]

Missing codegen tests.

[scott.linder]

Rebase, update syntax, expand tests

[kzhuravl]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2688

I think we should not be emitting this for v3.

[scott.linder]

Don't emit v2 kernel symbol type

[kzhuravl]

docs/AMDGPUUsage.rst

4373

GroupSegmentFixedSize -> GROUP_SEGMENT_FIXED_SIZE

4375

PrivateSegmentFixedSize -> PRIVATE_SEGMENT_FIXED_SIZE

4377

EnableSGPRPrivateSegmentBuffer -> ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER

4379

EnableSGPRDispatchPtr -> ENABLE_SGPR_DISPATCH_PTR

4381

EnableSGPRQueuePtr -> ENABLE_SGPR_QUEUE_PTR

4383

EnableSGPRKernargSegmentPtr -> ENABLE_SGPR_KERNARG_SEGMENT_PTR

4385

EnableSGPRDispatchID -> ENABLE_SGPR_DISPATCH_ID

4387

ditto

4389

ditto

4391

EnableSGPRGridWorkgroupCountX -> ENABLE_SGPR_GRID_WORKGROUP_COUNT_X

It is currently not implemented in the CP and must always be 0. What is the point of making this directive available to the user at this time?

4393

ditto

4395

ditto

4399

Should default to 1. Is it actually ok to provide this directive? amdhsa_system_sgpr_workgroup_id_x is always initialized.

[kzhuravl]

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

2740

sizeof returns number of bytes. isUint (and similar) take in number of bits.

[kzhuravl]

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

218

Use CurrentProgramInfo instead.

222–223

Info.NumVGPR -> CurrentProgramInfo.NumVGPRsForWavesPerEU
Info.NumExplicitSGPR -> CurrentProgramInfo. NumSGPRsForWavesPerEU - IsaInfo::getNumExtraSGPRs...
Info.UsesVCC -> CurrentProgramInfo.VCCUsed
Info.UsesFlatScratch -> CurrentProgramInfo.FlatUsed

Otherwise you are not honoring requested waves per eu.

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

1838

Did you mean .amdgcn.next_free_{v, s}gpr?

1841

Same as above.

2659

Make less than 80 chars.

2782–2795

amdhsa_user_sgpr_grid_workgroup_count_x/y/z should be removed. see https://reviews.llvm.org/D48191

[scott.linder]

Address feedback

• Update KD field names in asm directive docs
• Remove directives which effect ENABLE_SGPR_GRID_WORKGROUP_COUNT_{X,Y,Z}
• Default .amdhsa_system_sgpr_workgroup_id_x to 1
• Fix bug with using sizeof in context of bit count
• Honor default/requested waves per EU in AsmPrinter
• Fix formatting

[kzhuravl]

LGTM

[artem.tamazov]

Is it so that the updated documentation is valid only if code-object-v3 is specified?
Is the V3 code object compatible with the latest ROCm release?

[kzhuravl]

In D47736#1140847, @artem.tamazov wrote:

Is it so that the updated documentation is valid only if code-object-v3 is specified?

Yes

Is the V3 code object compatible with the latest ROCm release?

Not yet

[artem.tamazov]

In D47736#1140852, @kzhuravl wrote:

In D47736#1140847, @artem.tamazov wrote:

Is it so that the updated documentation is valid only if code-object-v3 is specified?

Yes

Is the V3 code object compatible with the latest ROCm release?

Not yet

So this change could confuse AMDGPU asm programmers.

[kzhuravl]

In D47736#1140911, @artem.tamazov wrote:

In D47736#1140852, @kzhuravl wrote:

In D47736#1140847, @artem.tamazov wrote:

Is it so that the updated documentation is valid only if code-object-v3 is specified?

Yes

Is the V3 code object compatible with the latest ROCm release?

Not yet

So this change could confuse AMDGPU asm programmers.

https://reviews.llvm.org/D48497

docs/AMDGPUUsage.rst

 (see :ref:`amdgpu-target-triples`).
 
 AMDHSA
 ------
 
 This section provides code conventions used when the target triple OS is
 ``amdhsa`` (see :ref:`amdgpu-target-triples`).
 
-.. _amdgpu-amdhsa-hsa-code-object-metadata:
+.. _amdgpu-code-object-target-identification:
 
 Code Object Target Identification
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The AMDHSA OS uses the following syntax to specify the code object
 target as a single string:
 
   ``<Architecture>-<Vendor>-<OS>-<Environment>-<Processor><Target Features>``
- ``<Target Features>`` is a list of the enabled *Target Features*
     in the table :ref:`amdgpu-target-feature-table`. Note that *Target
     Features* must be included in the list if they are enabled even if
     that is the default for *Processor*.
 
 For example:
 
   ``"amdgcn-amd-amdhsa--gfx902+xnack"``
 
+.. _amdgpu-amdhsa-hsa-code-object-metadata:
+
 Code Object Metadata
 ~~~~~~~~~~~~~~~~~~~~
 
 The code object metadata specifies extensible metadata associated with the code
 objects executed on HSA [HSA]_ compatible runtimes such as AMD's ROCm
 [AMD-ROCm]_. It is specified by the ``NT_AMD_AMDGPU_HSA_METADATA`` note record
 (see :ref:`amdgpu-note-records`) and is required when the target triple OS is
 ``amdhsa`` (see :ref:`amdgpu-target-triples`). It must contain the minimum

 
 Kernel Descriptor
 ~~~~~~~~~~~~~~~~~
 
 A kernel descriptor consists of the information needed by CP to initiate the
 execution of a kernel, including the entry point address of the machine code
 that implements the kernel.
 
+.. _amdgpu-amdhsa-kernel-descriptor-register-counts:
+
+SGPR and VGPR Counts
+++++++++++++++++++++
+
+For the purposes of calculating granulated register counts
+(GRANULATED_WORKITEM_VGPR_COUNT and GRANULATED_WAVEFRONT_SGPR_COUNT in
+:ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`) the terms `vgpr_count`
+and `sgpr_count` are defined, respectively, as being the highest VGPR and SGPR
+numbers explicitly referenced, plus one. That is, in code where the highest
+VGPR number referenced is v7 and the highest SGPR number referenced is s3,
+`vgpr_count` would be 8, and `sgpr_count` would be 4. As a special case, either
+or both counts may be 0; for the purposes of calculating the granularity
+counts, a value of 0 should be treated as 1.
+
 Kernel Descriptor for GFX6-GFX9
 +++++++++++++++++++++++++++++++
 
-CP microcode requires the Kernel descritor to be allocated on 64 byte alignment.
+CP microcode requires the Kernel descriptor to be allocated on 64 byte
+alignment.
 
   .. table:: Kernel Descriptor for GFX6-GFX9
      :name: amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table
 
      ======= ======= =============================== ============================
      Bits    Size    Field Name                      Description
      ======= ======= =============================== ============================
      31:0    4 bytes GROUP_SEGMENT_FIXED_SIZE        The amount of fixed local
.. table:: compute_pgm_rsrc1 for GFX6-GFX9
      Bits    Size    Field Name                      Description
      ======= ======= =============================== ===========================================================================
      5:0     6 bits  GRANULATED_WORKITEM_VGPR_COUNT  Number of vector registers
                                                      used by each work-item,
                                                      granularity is device
                                                      specific:
 
                                                      GFX6-GFX9
-                                                       - max_vgpr 1..256
-                                                       - roundup((max_vgpg + 1)
-                                                         / 4) - 1
+                                                       - vgpr_count 1..256
+                                                       - ceil(vgpr_count / 4) - 1
+
+                                                     vgpr_count is defined in
+                                                     :ref:`amdgpu-amdhsa-kernel-descriptor-register-counts`
 
                                                      Used by CP to set up
                                                      ``COMPUTE_PGM_RSRC1.VGPRS``.
      9:6     4 bits  GRANULATED_WAVEFRONT_SGPR_COUNT Number of scalar registers
                                                      used by a wavefront,
                                                      granularity is device
                                                      specific:
 
                                                      GFX6-GFX8
-                                                       - max_sgpr 1..112
-                                                       - roundup((max_sgpg + 1)
-                                                         / 8) - 1
+                                                       - sgpr_count 1..112
+                                                       - ceil(sgpr_count / 8) - 1
                                                      GFX9
-                                                       - max_sgpr 1..112
-                                                       - roundup((max_sgpg + 1)
-                                                         / 16) - 1
+                                                       - sgpr_count 1..112
+                                                       - ceil(sgpr_count / 16) - 1
 
                                                      Includes the special SGPRs
                                                      for VCC, Flat Scratch (for
                                                      GFX7 onwards) and XNACK
                                                      (for GFX8 onwards). It does
                                                      not include the 16 SGPR
                                                      added if a trap handler is
                                                      enabled.
 
+                                                     sgpr_count is defined in
+                                                     :ref:`amdgpu-amdhsa-kernel-descriptor-register-counts`
+
                                                      Used by CP to set up
                                                      ``COMPUTE_PGM_RSRC1.SGPRS``.
      11:10   2 bits  PRIORITY                        Must be 0.
 
                                                      Start executing wavefront
                                                      at the specified priority.
 
                                                      CP is responsible for
.. code-block:: nasm
   v_mov_b32 v1, v2 dst_sel:BYTE_0 dst_unused:UNUSED_PRESERVE src0_sel:DWORD
   v_min_u32 v200, v200, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
   v_sin_f32 v0, v0 dst_unused:UNUSED_PAD src0_sel:WORD_1
   v_fract_f32 v0, |v0| dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1
   v_cmpx_le_u32 vcc, v1, v2 src0_sel:BYTE_2 src1_sel:WORD_0
 
 For full list of supported instructions, refer to "Vector ALU instructions".
 
-HSA Code Object Directives
-~~~~~~~~~~~~~~~~~~~~~~~~~~
+Predefined Symbols
+~~~~~~~~~~~~~~~~~~
 
-AMDGPU ABI defines auxiliary data in output code object. In assembly source,
-one can specify them with assembler directives.
+The AMDGPU assembler defines and updates some symbols automatically. These
+symbols do not affect code generation.
 
-.hsa_code_object_version major, minor
-+++++++++++++++++++++++++++++++++++++
+.amdgcn.machine_version_major
++++++++++++++++++++++++++++++
 
-*major* and *minor* are integers that specify the version of the HSA code
-object that will be generated by the assembler.
+Set to the major version number of the target being assembled for. For example,
+when assembling for "gfx902" this will be set to the integer value "9".
 
-.hsa_code_object_isa [major, minor, stepping, vendor, arch]
-+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+.amdgcn.machine_version_minor
++++++++++++++++++++++++++++++
 
+Set to the minor version number of the target being assembled for. For example,
+when assembling for "gfx902" this will be set to the integer value "0".
 
-*major*, *minor*, and *stepping* are all integers that describe the instruction
-set architecture (ISA) version of the assembly program.
+.amdgcn.machine_version_stepping
+++++++++++++++++++++++++++++++++
 
-*vendor* and *arch* are quoted strings.  *vendor* should always be equal to
-"AMD" and *arch* should always be equal to "AMDGPU".
+Set to the stepping version number of the target being assembled for. For
+example, when assembling for "gfx902" this will be set to the integer value
+"2".
 
-By default, the assembler will derive the ISA version, *vendor*, and *arch*
-from the value of the -mcpu option that is passed to the assembler.
+.amdgcn.vgpr_count
+++++++++++++++++++
 
-.amdgpu_hsa_kernel (name)
-+++++++++++++++++++++++++
+Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal to the maximum VGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that VGPR number plus one.
 
-This directives specifies that the symbol with given name is a kernel entry point
-(label) and the object should contain corresponding symbol of type STT_AMDGPU_HSA_KERNEL.
+May be set at any time, e.g. manually set to zero after each kernel.
 
-.amd_kernel_code_t
+.amdgcn.sgpr_count
 ++++++++++++++++++
 
-This directive marks the beginning of a list of key / value pairs that are used
-to specify the amd_kernel_code_t object that will be emitted by the assembler.
-The list must be terminated by the *.end_amd_kernel_code_t* directive.  For
-any amd_kernel_code_t values that are unspecified a default value will be
-used.  The default value for all keys is 0, with the following exceptions:
-
-- *kernel_code_version_major* defaults to 1.
-- *machine_kind* defaults to 1.
-- *machine_version_major*, *machine_version_minor*, and
-  *machine_version_stepping* are derived from the value of the -mcpu option
-  that is passed to the assembler.
-- *kernel_code_entry_byte_offset* defaults to 256.
-- *wavefront_size* defaults to 6.
-- *kernarg_segment_alignment*, *group_segment_alignment*, and
-  *private_segment_alignment* default to 4. Note that alignments are specified
-  as a power of two, so a value of **n** means an alignment of 2^ **n**.
-
-The *.amd_kernel_code_t* directive must be placed immediately after the
-function label and before any instructions.
-
-For a full list of amd_kernel_code_t keys, refer to AMDGPU ABI document,
-comments in lib/Target/AMDGPU/AmdKernelCodeT.h and test/CodeGen/AMDGPU/hsa.s.
-
-Here is an example of a minimal amd_kernel_code_t specification:
-
-.. code-block:: none
-
-   .hsa_code_object_version 1,0
-   .hsa_code_object_isa
-
-   .hsatext
-   .globl  hello_world
-   .p2align 8
-   .amdgpu_hsa_kernel hello_world
-
-   hello_world:
-
-      .amd_kernel_code_t
-         enable_sgpr_kernarg_segment_ptr = 1
-         is_ptr64 = 1
-         compute_pgm_rsrc1_vgprs = 0
-         compute_pgm_rsrc1_sgprs = 0
-         compute_pgm_rsrc2_user_sgpr = 2
-         kernarg_segment_byte_size = 8
-         wavefront_sgpr_count = 2
-         workitem_vgpr_count = 3
-     .end_amd_kernel_code_t
-
-     s_load_dwordx2 s[0:1], s[0:1] 0x0
-     v_mov_b32 v0, 3.14159
-     s_waitcnt lgkmcnt(0)
-     v_mov_b32 v1, s0
-     v_mov_b32 v2, s1
-     flat_store_dword v[1:2], v0
-     s_endpgm
-   .Lfunc_end0:
-        .size   hello_world, .Lfunc_end0-hello_world
+Set to zero before assembly begins. At each instruction, if the current value
+of this symbol is less than or equal the maximum SGPR number explicitly
+referenced within that instruction then the symbol value is updated to equal
+that SGPR number plus one.
+
+May be set at any time, e.g. manually set to zero after each kernel.
+
+Code Object Directives
+~~~~~~~~~~~~~~~~~~~~~~
+
+Directives which begin with ``.amdgcn`` are valid for all GCN targets, and are
+not OS-specific. Directives which begin with ``.amdhsa`` are specific to
+GCN targets with the ``amdhsa`` OS in their triple.
+
+.amdgcn_target <target>
++++++++++++++++++++++++
+
+Declares the target supported by the containing assembler source file. Valid
+values are described in :ref:`amdgpu-code-object-target-identification`. Used
+by the assembler to validate command-line options such as ``-triple``,
+``-mcpu``, and those which specify target features.
+
+.amdhsa_kernel <name>
++++++++++++++++++++++
+
+Creates a correctly aligned AMDHSA kernel descriptor and a symbol,
+``<name>@kd``, in the current location of the current section. Only valid when
+the target OS is ``amdhsa``.
+
+Marks the beginning of a list of directives used to generate the bytes of a
+kernel descriptor, as described in :ref:`amdgpu-amdhsa-kernel-descriptor`.
+Directives which may appear in this list are described in
+:ref:`amdhsa-kernel-directives-table`. Directives may appear in any order, must
+be valid for the target being assembled for, and cannot be repeated. Directives
+support the range of values specified by the field they reference in
+:ref:`amdgpu-amdhsa-kernel-descriptor`. If a directive is not specified, it is
+assumed to have its default value, unless it is marked as "Required", in which
+case it is an error to omit the directive. This list of directives is
+terminated by an ``.end_amdhsa_kernel`` directive.
+
+  .. table:: AMDHSA Kernel Assembler Directives
+     :name: amdhsa-kernel-directives-table
+
+     ======================================================== ================ ============ ===================
+     Directive                                                Default          Supported On Description
+     ======================================================== ================ ============ ===================
+     ``.amdhsa_group_segment_fixed_size``                     0                GFX6-GFX9    Controls GroupSegmentFixedSize in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_private_segment_fixed_size``                   0                GFX6-GFX9    Controls PrivateSegmentFixedSize in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_private_segment_buffer``             0                GFX6-GFX9    Controls EnableSGPRPrivateSegmentBuffer in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_dispatch_ptr``                       0                GFX6-GFX9    Controls EnableSGPRDispatchPtr in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_queue_ptr``                          0                GFX6-GFX9    Controls EnableSGPRQueuePtr in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_kernarg_segment_ptr``                0                GFX6-GFX9    Controls EnableSGPRKernargSegmentPtr in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_dispatch_id``                        0                GFX6-GFX9    Controls EnableSGPRDispatchID in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_flat_scratch_init``                  0                GFX6-GFX9    Controls EnableSGPRFlatScratchInit in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_private_segment_size``               0                GFX6-GFX9    Controls EnableSGPRPrivateSegmentSize in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_grid_workgroup_count_x``             0                GFX6-GFX9    Controls EnableSGPRGridWorkgroupCountX in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_grid_workgroup_count_y``             0                GFX6-GFX9    Controls EnableSGPRGridWorkgroupCountY in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_user_sgpr_grid_workgroup_count_z``             0                GFX6-GFX9    Controls EnableSGPRGridWorkgroupCountZ in
+                                                                                            :ref:`amdgpu-amdhsa-kernel-descriptor-gfx6-gfx9-table`
+     ``.amdhsa_system_sgpr_private_segment_wavefront_offset`` 0                GFX6-GFX9    Controls ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_system_sgpr_workgroup_id_x``                   0                GFX6-GFX9    Controls ENABLE_SGPR_WORKGROUP_ID_X in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_system_sgpr_workgroup_id_y``                   0                GFX6-GFX9    Controls ENABLE_SGPR_WORKGROUP_ID_Y in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_system_sgpr_workgroup_id_z``                   0                GFX6-GFX9    Controls ENABLE_SGPR_WORKGROUP_ID_Z in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_system_sgpr_workgroup_info``                   0                GFX6-GFX9    Controls ENABLE_SGPR_WORKGROUP_INFO in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_system_vgpr_workitem_id``                      0                GFX6-GFX9    Controls ENABLE_VGPR_WORKITEM_ID in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_vgpr_count``                                   Required         GFX6-GFX9    Maximum VGPR number used, plus one. Used to calculate
+                                                                                            GRANULATED_WORKITEM_VGPR_COUNT in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_sgpr_count``                                   Required         GFX6-GFX9    Maximum SGPR number used, plus one. Used to calculate
+                                                                                            GRANULATED_WAVEFRONT_SGPR_COUNT in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_float_round_mode_32``                          0                GFX6-GFX9    Controls FLOAT_ROUND_MODE_32 in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_float_round_mode_16_64``                       0                GFX6-GFX9    Controls FLOAT_ROUND_MODE_16_64 in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_float_denorm_mode_32``                         0                GFX6-GFX9    Controls FLOAT_DENORM_MODE_32 in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_float_denorm_mode_16_64``                      3                GFX6-GFX9    Controls FLOAT_DENORM_MODE_16_64 in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_dx10_clamp``                                   1                GFX6-GFX9    Controls ENABLE_DX10_CLAMP in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_ieee_mode``                                    1                GFX6-GFX9    Controls ENABLE_IEEE_MODE in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_fp16_overflow``                                0                GFX9         Controls FP16_OVFL in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_ieee_invalid_op``                 0                GFX6-GFX9    Controls ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_denorm_src``                      0                GFX6-GFX9    Controls ENABLE_EXCEPTION_FP_DENORMAL_SOURCE in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_ieee_div_zero``                   0                GFX6-GFX9    Controls ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_ieee_overflow``                   0                GFX6-GFX9    Controls ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_ieee_underflow``                  0                GFX6-GFX9    Controls ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_fp_ieee_inexact``                    0                GFX6-GFX9    Controls ENABLE_EXCEPTION_IEEE_754_FP_INEXACT in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ``.amdhsa_exception_int_div_zero``                       0                GFX6-GFX9    Controls ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO in
+                                                                                            :ref:`amdgpu-amdhsa-compute_pgm_rsrc2-gfx6-gfx9-table`
+     ======================================================== ================ ============ ===================
 
 Additional Documentation
 ========================
 
 .. [AMD-RADEON-HD-2000-3000] `AMD R6xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R600_Instruction_Set_Architecture.pdf>`__
 .. [AMD-RADEON-HD-4000] `AMD R7xx shader ISA <http://developer.amd.com/wordpress/media/2012/10/R700-Family_Instruction_Set_Architecture.pdf>`__
 .. [AMD-RADEON-HD-5000] `AMD Evergreen shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_Evergreen-Family_Instruction_Set_Architecture.pdf>`__
 .. [AMD-RADEON-HD-6000] `AMD Cayman/Trinity shader ISA <http://developer.amd.com/wordpress/media/2012/10/AMD_HD_6900_Series_Instruction_Set_Architecture.pdf>`__

include/llvm/Support/AMDHSAKernelDescriptor.h

 
 #ifndef LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
 #define LLVM_SUPPORT_AMDHSAKERNELDESCRIPTOR_H
 
 #include <cstdint>
 
 // Gets offset of specified member in specified type.
 #ifndef offsetof
-#define offsetof(TYPE, MEMBER) ((size_t)&((TYPE*)0)->MEMBER)
+#define offsetof(TYPE, MEMBER) ((std::size_t) & ((TYPE *)0)->MEMBER)
 #endif // offsetof
 
 // Creates enumeration entries used for packing bits into integers. Enumeration
 // entries include bit shift amount, bit width, and bit mask.
 #ifndef AMDHSA_BITS_ENUM_ENTRY
 #define AMDHSA_BITS_ENUM_ENTRY(NAME, SHIFT, WIDTH) \
   NAME ## _SHIFT = (SHIFT),                        \
   NAME ## _WIDTH = (WIDTH),                        \
struct kernel_descriptor_t {
   int64_t kernel_code_entry_byte_offset;
   uint8_t reserved1[24];
   uint32_t compute_pgm_rsrc1;
   uint32_t compute_pgm_rsrc2;
   uint16_t kernel_code_properties;
   uint8_t reserved2[6];
 };
 
+/// Overwrite \p KD with default values.
+void setDefaultKernelDescriptor(kernel_descriptor_t &KD);
+
 static_assert(
     sizeof(kernel_descriptor_t) == 64,
     "invalid size for kernel_descriptor_t");
 static_assert(
     offsetof(kernel_descriptor_t, group_segment_fixed_size) == 0,
     "invalid offset for group_segment_fixed_size");
 static_assert(
     offsetof(kernel_descriptor_t, private_segment_fixed_size) == 4,

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

 
 void AMDGPUAsmPrinter::EmitFunctionBodyEnd() {
   const SIMachineFunctionInfo &MFI = *MF->getInfo<SIMachineFunctionInfo>();
   if (!MFI.isEntryFunction())
     return;
   if (!IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits()))
     return;
 
   SmallString<128> KernelName;
   getNameWithPrefix(KernelName, &MF->getFunction());
   getTargetStreamer()->EmitAmdhsaKernelDescriptor(
-      KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo));
+      KernelName, getAmdhsaKernelDescriptor(*MF, CurrentProgramInfo),
+      *getSTI());
 }
 
 void AMDGPUAsmPrinter::EmitFunctionEntryLabel() {
   if (IsaInfo::hasCodeObjectV3(getSTI()->getFeatureBits())) {
     AsmPrinter::EmitFunctionEntryLabel();
     return;
   }
 
   const SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

 #include "llvm/MC/MCParser/MCAsmParserExtension.h"
 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/AMDGPUMetadata.h"
+#include "llvm/Support/AMDHSAKernelDescriptor.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/SMLoc.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
 #include <cstring>
 #include <iterator>
 #include <map>
 #include <memory>
 #include <string>
 
 using namespace llvm;
 using namespace llvm::AMDGPU;
+using namespace llvm::amdhsa;
 
 namespace {
 
 class AMDGPUAsmParser;
 
 enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_TTMP, IS_SPECIAL };
 
 //===----------------------------------------------------------------------===//

 
 #define GET_ASSEMBLER_HEADER
 #include "AMDGPUGenAsmMatcher.inc"
 
   /// }
 
 private:
   bool ParseAsAbsoluteExpression(uint32_t &Ret);
+  bool OutOfRangeError(SMRange Range);
+  bool ParseDirectiveAMDGCNTarget();
+  bool ParseDirectiveAMDHSAKernel();
   bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
   bool ParseDirectiveHSACodeObjectVersion();
   bool ParseDirectiveHSACodeObjectISA();
   bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
   bool ParseDirectiveAMDKernelCodeT();
   bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo) const;
   bool ParseDirectiveAMDGPUHsaKernel();
 
   bool ParseDirectiveISAVersion();
   bool ParseDirectiveHSAMetadata();
   bool ParseDirectivePALMetadata();
 
   bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
                              RegisterKind RegKind, unsigned Reg1,
                              unsigned RegNum);
   bool ParseAMDGPURegister(RegisterKind& RegKind, unsigned& Reg,
                            unsigned& RegNum, unsigned& RegWidth,
                            unsigned *DwordRegIndex);
+  Optional<StringRef> getGprCountSymbolName(RegisterKind RegKind);
+  void initializeGprCountSymbol(RegisterKind RegKind);
+  bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,
+                             unsigned RegWidth);
   void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
                     bool IsAtomic, bool IsAtomicReturn, bool IsLds = false);
   void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
                  bool IsGdsHardcoded);
 
 public:
   enum AMDGPUMatchResultTy {
     Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
     {
       // TODO: make those pre-defined variables read-only.
       // Currently there is none suitable machinery in the core llvm-mc for this.
       // MCSymbol::isRedefinable is intended for another purpose, and
       // AsmParser::parseDirectiveSet() cannot be specialized for specific target.
       AMDGPU::IsaInfo::IsaVersion ISA =
           AMDGPU::IsaInfo::getIsaVersion(getFeatureBits());
       MCContext &Ctx = getContext();
+      if (AMDGPU::IsaInfo::hasCodeObjectV3(getFeatureBits())) {
+        MCSymbol *Sym =
+            Ctx.getOrCreateSymbol(Twine(".amdgcn.machine_version_major"));
+        Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
+        Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.machine_version_minor"));
+        Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
+        Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.machine_version_stepping"));
+        Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
+      } else {
         MCSymbol *Sym =
             Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
         Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
         Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
       }
+    }
+    if (AMDGPU::IsaInfo::hasCodeObjectV3(getFeatureBits())) {
+      initializeGprCountSymbol(IS_VGPR);
+      initializeGprCountSymbol(IS_SGPR);
+    } else
       KernelScope.initialize(getContext());
   }
 
   bool hasXNACK() const {
     return AMDGPU::hasXNACK(getSTI());
   }
 
   bool hasMIMG_R128() const {
     return AMDGPU::hasMIMG_R128(getSTI());
default:
     llvm_unreachable("unexpected register kind");
   }
 
   if (!subtargetHasRegister(*TRI, Reg))
     return false;
   return true;
 }
 
+Optional<StringRef>
+AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {
+  switch (RegKind) {
+  case IS_VGPR:
+    return StringRef(".amdgcn.vgpr_count");
+  case IS_SGPR:
+    return StringRef(".amdgcn.sgpr_count");
+  default:
+    return None;
+  }
+}
+
+void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {
+  auto SymbolName = getGprCountSymbolName(RegKind);
+  assert(SymbolName && "initializing invalid register kind");
+  MCSymbol *Sym = getContext().getOrCreateSymbol(*SymbolName);
+  Sym->setVariableValue(MCConstantExpr::create(0, getContext()));
+}
+
+bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
+                                            unsigned DwordRegIndex,
+                                            unsigned RegWidth) {
+  auto SymbolName = getGprCountSymbolName(RegKind);
+  if (!SymbolName)
+    return true;
+  MCSymbol *Sym = getContext().getOrCreateSymbol(*SymbolName);
+
+  int64_t NewMax = DwordRegIndex + RegWidth - 1;
+  int64_t OldCount;
+
+  if (!Sym->isVariable())
+    return !Error(getParser().getTok().getLoc(),
+                  ".amdgcn.{v,s}grp_count symbols must be variable");
+  if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))
+    return !Error(
+        getParser().getTok().getLoc(),
+        ".amdgcn.{v,s}gpr_count symbols must be absolute expressions");
+
+  if (OldCount <= NewMax)
+    Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));
+
+  return true;
+}
+
 std::unique_ptr<AMDGPUOperand> AMDGPUAsmParser::parseRegister() {
   const auto &Tok = Parser.getTok();
   SMLoc StartLoc = Tok.getLoc();
   SMLoc EndLoc = Tok.getEndLoc();
   RegisterKind RegKind;
   unsigned Reg, RegNum, RegWidth, DwordRegIndex;
 
   if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, &DwordRegIndex)) {
     return nullptr;
   }
+  if (AMDGPU::IsaInfo::hasCodeObjectV3(getFeatureBits())) {
+    if (!updateGprCountSymbols(RegKind, DwordRegIndex, RegWidth))
+      return nullptr;
+  } else
     KernelScope.usesRegister(RegKind, DwordRegIndex, RegWidth);
   return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc, false);
 }
 
 bool
 AMDGPUAsmParser::parseAbsoluteExpr(int64_t &Val, bool AbsMod) {
   if (AbsMod && getLexer().peekTok().is(AsmToken::Pipe) &&
       (getLexer().getKind() == AsmToken::Integer ||
        getLexer().getKind() == AsmToken::Real)) {
bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
   Lex();
 
   if (ParseAsAbsoluteExpression(Minor))
     return TokError("invalid minor version");
 
   return false;
 }
 
+bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
+  if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
+    return TokError("directive only supported for amdgcn architecture");
+
+  std::string Target;
+
+  SMLoc TargetStart = getTok().getLoc();
+  if (getParser().parseEscapedString(Target))
+    return true;
+  SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
+
+  std::string ExpectedTarget;
+  raw_string_ostream ExpectedTargetOS(ExpectedTarget);
+  IsaInfo::streamIsaVersion(&getSTI(), ExpectedTargetOS);
+
+  // TODO(scott.linder): should this be in streamIsaVersion?
+  if (hasXNACK())
+    ExpectedTargetOS << "+xnack";
+
+  if (Target != ExpectedTargetOS.str())
+    return getParser().Error(TargetRange.Start, "target must match options",
+                             TargetRange);
+
+  getTargetStreamer().EmitDirectiveAMDGCNTarget(Target);
+  return false;
+}
+
+bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
+  return getParser().Error(Range.Start, "value out of range", Range);
+}
+
+bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
+  if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)
+    return TokError("directive only supported for amdhsa OS");
+
+  StringRef SymbolName;
+  if (getParser().parseIdentifier(SymbolName))
+    return true;
+
+  kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor();
+
+  StringSet<> Seen;
+
+  while (true) {
+    while (getLexer().is(AsmToken::EndOfStatement))
+      Lex();
+
+    if (getLexer().isNot(AsmToken::Identifier))
+      return TokError("expected .amdhsa_ directive or .end_amdhsa_kernel");
+
+    StringRef ID = getTok().getIdentifier();
+    SMRange IDRange = getTok().getLocRange();
+    Lex();
+
+    if (ID == ".end_amdhsa_kernel")
+      break;
+
+    if (Seen.find(ID) != Seen.end())
+      return TokError(".amdhsa_ directives cannot be repeated");
+    Seen.insert(ID);
+
+    SMLoc ValStart = getTok().getLoc();
+    int64_t IVal;
+    if (getParser().parseAbsoluteExpression(IVal))
+      return true;
+    SMLoc ValEnd = getTok().getLoc();
+    SMRange ValRange = SMRange(ValStart, ValEnd);
+
+    if (IVal < 0)
+      return OutOfRangeError(ValRange);
+
+    uint64_t Val = IVal;
+
+#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE)                           \
+  if (!isUInt<ENTRY##_WIDTH>(VALUE))                                           \
+    return OutOfRangeError(RANGE);                                             \
+  AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);
+
+    if (ID == ".amdhsa_group_segment_fixed_size") {
+      if (!isUInt<sizeof(KD.group_segment_fixed_size)>(Val))
+        return OutOfRangeError(ValRange);
+      KD.group_segment_fixed_size = Val;
+    } else if (ID == ".amdhsa_private_segment_fixed_size") {
+      if (!isUInt<sizeof(KD.private_segment_fixed_size)>(Val))
+        return OutOfRangeError(ValRange);
+      KD.private_segment_fixed_size = Val;
+    } else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_queue_ptr") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_dispatch_id") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_private_segment_size") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_grid_workgroup_count_x") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_grid_workgroup_count_y") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_user_sgpr_grid_workgroup_count_z") {
+      PARSE_BITS_ENTRY(KD.kernel_code_properties,
+                       KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {
+      PARSE_BITS_ENTRY(
+          KD.compute_pgm_rsrc2,
+          COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET, Val,
+          ValRange);
+    } else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_system_sgpr_workgroup_info") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_system_vgpr_workitem_id") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_vgpr_count") {
+      if (Val == 0)
+        Val = 1;
+      Val = divideCeil(Val, IsaInfo::getVGPRAllocGranule(getFeatureBits())) - 1;
+      if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT_WIDTH>(Val))
+        return OutOfRangeError(ValRange);
+      AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
+                      COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, Val);
+    } else if (ID == ".amdhsa_sgpr_count") {
+      if (Val == 0)
+        Val = 1;
+      Val = divideCeil(Val, IsaInfo::getSGPRAllocGranule(getFeatureBits())) - 1;
+      if (!isUInt<COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT_WIDTH>(Val))
+        return OutOfRangeError(ValRange);
+      AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
+                      COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT, Val);
+    } else if (ID == ".amdhsa_float_round_mode_32") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+                       COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);
+    } else if (ID == ".amdhsa_float_round_mode_16_64") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+                       COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);
+    } else if (ID == ".amdhsa_float_denorm_mode_32") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+                       COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);
+    } else if (ID == ".amdhsa_float_denorm_mode_16_64") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+                       COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_dx10_clamp") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
+                       COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);
+    } else if (ID == ".amdhsa_ieee_mode") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_fp16_overflow") {
+      if (!isGFX9())
+        return getParser().Error(IDRange.Start, "directive requires gfx9",
+                                 IDRange);
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,
+                       ValRange);
+    } else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {
+      PARSE_BITS_ENTRY(
+          KD.compute_pgm_rsrc2,
+          COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,
+          ValRange);
+    } else if (ID == ".amdhsa_exception_fp_denorm_src") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {
+      PARSE_BITS_ENTRY(
+          KD.compute_pgm_rsrc2,
+          COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,
+          ValRange);
+    } else if (ID == ".amdhsa_exception_fp_ieee_overflow") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_exception_fp_ieee_underflow") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_exception_fp_ieee_inexact") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
+                       Val, ValRange);
+    } else if (ID == ".amdhsa_exception_int_div_zero") {
+      PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
+                       COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
+                       Val, ValRange);
+    } else {
+      return getParser().Error(IDRange.Start,
+                               "unknown .amdhsa_kernel directive", IDRange);
+    }
+  }
+#undef PARSE_BITS_ENTRY
+
+  if (Seen.find(".amdhsa_vgpr_count") == Seen.end())
+    return TokError(".amdhsa_vgpr_count directive is required");
+
+  if (Seen.find(".amdhsa_sgpr_count") == Seen.end())
+    return TokError(".amdhsa_sgpr_count directive is required");
+
+  getTargetStreamer().EmitAmdhsaKernelDescriptor(SymbolName, KD, getSTI());
+  return false;
+}
+
 bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
   uint32_t Major;
   uint32_t Minor;
 
   if (ParseDirectiveMajorMinor(Major, Minor))
     return true;
 
   getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
   if (getLexer().isNot(AsmToken::Identifier))
     return TokError("expected symbol name");
 
   StringRef KernelName = Parser.getTok().getString();
 
   getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
                                            ELF::STT_AMDGPU_HSA_KERNEL);
   Lex();
+  if (!AMDGPU::IsaInfo::hasCodeObjectV3(getFeatureBits()))
     KernelScope.initialize(getContext());
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
   if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
     return Error(getParser().getTok().getLoc(),
                  ".amd_amdgpu_isa directive is not available on non-amdgcn "
                  "architectures");
bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
   }
   getTargetStreamer().EmitPALMetadata(PALMetadata);
   return false;
 }
 
 bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getString();
 
+  if (AMDGPU::IsaInfo::hasCodeObjectV3(getFeatureBits())) {
+    if (IDVal == ".amdgcn_target")
+      return ParseDirectiveAMDGCNTarget();
+
+    if (IDVal == ".amdhsa_kernel")
+      return ParseDirectiveAMDHSAKernel();
+  } else {
     if (IDVal == ".hsa_code_object_version")
       return ParseDirectiveHSACodeObjectVersion();
 
     if (IDVal == ".hsa_code_object_isa")
       return ParseDirectiveHSACodeObjectISA();
 
     if (IDVal == ".amd_kernel_code_t")
       return ParseDirectiveAMDKernelCodeT();
 
     if (IDVal == ".amdgpu_hsa_kernel")
       return ParseDirectiveAMDGPUHsaKernel();
 
     if (IDVal == ".amd_amdgpu_isa")
       return ParseDirectiveISAVersion();
+  }
 
   if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)
     return ParseDirectiveHSAMetadata();
 
   if (IDVal == PALMD::AssemblerDirective)
     return ParseDirectivePALMetadata();
 
   return true;

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h

protected:
   unsigned getMACH(StringRef GPU) const;
 
 public:
   /// \returns Equivalent GPU name for an EF_AMDGPU_MACH_* value.
   static const char *getMachName(unsigned Mach);
 
   AMDGPUTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
 
+  virtual void EmitDirectiveAMDGCNTarget(StringRef Target) = 0;
+
   virtual void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                                  uint32_t Minor) = 0;
 
   virtual void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                              uint32_t Stepping,
                                              StringRef VendorName,
                                              StringRef ArchName) = 0;
 
public:
 
   /// \returns True on success, false on failure.
   virtual bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) = 0;
 
   /// \returns True on success, false on failure.
   virtual bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) = 0;
 
   virtual void EmitAmdhsaKernelDescriptor(
-      StringRef KernelName,
-      const amdhsa::kernel_descriptor_t &KernelDescriptor) = 0;
+      StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor,
+      const MCSubtargetInfo &STI) = 0;
 };
 
 class AMDGPUTargetAsmStreamer final : public AMDGPUTargetStreamer {
   formatted_raw_ostream &OS;
 public:
   AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
+
+  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
   /// \returns True on success, false on failure.
   bool EmitISAVersion(StringRef IsaVersionString) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
 
   void EmitAmdhsaKernelDescriptor(
-      StringRef KernelName,
-      const amdhsa::kernel_descriptor_t &KernelDescriptor) override;
+      StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor,
+      const MCSubtargetInfo &STI) override;
 };
 
 class AMDGPUTargetELFStreamer final : public AMDGPUTargetStreamer {
   MCStreamer &Streamer;
 
   void EmitAMDGPUNote(const MCExpr *DescSize, unsigned NoteType,
                       function_ref<void(MCELFStreamer &)> EmitDesc);
 
 public:
   AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
 
   MCELFStreamer &getStreamer();
 
+  void EmitDirectiveAMDGCNTarget(StringRef Target) override;
+
   void EmitDirectiveHSACodeObjectVersion(uint32_t Major,
                                          uint32_t Minor) override;
 
   void EmitDirectiveHSACodeObjectISA(uint32_t Major, uint32_t Minor,
                                      uint32_t Stepping, StringRef VendorName,
                                      StringRef ArchName) override;
 
   void EmitAMDKernelCodeT(const amd_kernel_code_t &Header) override;
 
   void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override;
 
   /// \returns True on success, false on failure.
   bool EmitISAVersion(StringRef IsaVersionString) override;
 
   /// \returns True on success, false on failure.
   bool EmitHSAMetadata(const AMDGPU::HSAMD::Metadata &HSAMetadata) override;
 
   /// \returns True on success, false on failure.
   bool EmitPALMetadata(const AMDGPU::PALMD::Metadata &PALMetadata) override;
 
   void EmitAmdhsaKernelDescriptor(
-      StringRef KernelName,
-      const amdhsa::kernel_descriptor_t &KernelDescriptor) override;
+      StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor,
+      const MCSubtargetInfo &STI) override;
 };
 
 }
 #endif

lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp

 //===----------------------------------------------------------------------===//
 // AMDGPUTargetAsmStreamer
 //===----------------------------------------------------------------------===//
 
 AMDGPUTargetAsmStreamer::AMDGPUTargetAsmStreamer(MCStreamer &S,
                                                  formatted_raw_ostream &OS)
     : AMDGPUTargetStreamer(S), OS(OS) { }
 
-void
-AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(uint32_t Major,
-                                                           uint32_t Minor) {
+void AMDGPUTargetAsmStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {
+  // TODO: quote/escape Target?
+  OS << "\t.amdgcn_target \"" << Target << "\"\n";
+}
+
+void AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectVersion(
+    uint32_t Major, uint32_t Minor) {
   OS << "\t.hsa_code_object_version " <<
         Twine(Major) << "," << Twine(Minor) << '\n';
 }
 
 void
 AMDGPUTargetAsmStreamer::EmitDirectiveHSACodeObjectISA(uint32_t Major,
                                                        uint32_t Minor,
                                                        uint32_t Stepping,
bool AMDGPUTargetAsmStreamer::EmitPALMetadata(
   if (PALMD::toString(PALMetadata, PALMetadataString))
     return false;
 
   OS << '\t' << PALMD::AssemblerDirective << PALMetadataString << '\n';
   return true;
 }
 
 void AMDGPUTargetAsmStreamer::EmitAmdhsaKernelDescriptor(
-    StringRef KernelName,
-    const amdhsa::kernel_descriptor_t &KernelDescriptor) {
-  // FIXME: not supported yet.
+    StringRef KernelName, const amdhsa::kernel_descriptor_t &KD,
+    const MCSubtargetInfo &STI) {
+  amdhsa::kernel_descriptor_t DefaultKD = getDefaultAmdhsaKernelDescriptor();
+
+  uint32_t GranulatedVgpr =
+      AMDHSA_BITS_GET(KD.compute_pgm_rsrc1,
+                      amdhsa::COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT);
+  uint32_t VgprCount =
+      (GranulatedVgpr + 1) *
+      AMDGPU::IsaInfo::getVGPRAllocGranule(STI.getFeatureBits());
+  uint32_t GranulatedSgpr = AMDHSA_BITS_GET(
+      KD.compute_pgm_rsrc1,
+      amdhsa::COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT);
+  uint32_t SgprCount =
+      (GranulatedSgpr + 1) *
+      AMDGPU::IsaInfo::getSGPRAllocGranule(STI.getFeatureBits());
+
+  // TODO: quote/escape KernelName?
+  OS << "\t.amdhsa_kernel " << KernelName << '\n';
+
+#define PRINT_IF_NOT_DEFAULT(STREAM, DIRECTIVE, KERNEL_DESC,                   \
+                             DEFAULT_KERNEL_DESC, MEMBER_NAME, FIELD_NAME)     \
+  if (AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) !=                  \
+      AMDHSA_BITS_GET(DEFAULT_KERNEL_DESC.MEMBER_NAME, FIELD_NAME))            \
+    STREAM << "\t\t" << DIRECTIVE << " "                                       \
+           << AMDHSA_BITS_GET(KERNEL_DESC.MEMBER_NAME, FIELD_NAME) << '\n';
+
+  if (KD.group_segment_fixed_size != DefaultKD.group_segment_fixed_size)
+    OS << "\t\t.amdhsa_group_segment_fixed_size " << KD.group_segment_fixed_size
+       << '\n';
+  if (KD.private_segment_fixed_size != DefaultKD.private_segment_fixed_size)
+    OS << "\t\t.amdhsa_private_segment_fixed_size "
+       << KD.private_segment_fixed_size << '\n';
+
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_private_segment_buffer", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_ptr", KD, DefaultKD,
+                       kernel_code_properties,
+                       amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_queue_ptr", KD, DefaultKD,
+                       kernel_code_properties,
+                       amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_kernarg_segment_ptr", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_user_sgpr_dispatch_id", KD, DefaultKD,
+                       kernel_code_properties,
+                       amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_flat_scratch_init", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_private_segment_size", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_grid_workgroup_count_x", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_grid_workgroup_count_y", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_user_sgpr_grid_workgroup_count_z", KD, DefaultKD,
+      kernel_code_properties,
+      amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_system_sgpr_private_segment_wavefront_offset", KD, DefaultKD,
+      compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_PRIVATE_SEGMENT_WAVEFRONT_OFFSET);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_x", KD, DefaultKD,
+                       compute_pgm_rsrc2,
+                       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_y", KD, DefaultKD,
+                       compute_pgm_rsrc2,
+                       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_id_z", KD, DefaultKD,
+                       compute_pgm_rsrc2,
+                       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_sgpr_workgroup_info", KD, DefaultKD,
+                       compute_pgm_rsrc2,
+                       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_system_vgpr_workitem_id", KD, DefaultKD,
+                       compute_pgm_rsrc2,
+                       amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID);
+
+  // These directives are required.
+  OS << "\t\t.amdhsa_vgpr_count " << VgprCount << '\n';
+  OS << "\t\t.amdhsa_sgpr_count " << SgprCount << '\n';
+
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_32", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_round_mode_16_64", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_32", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_float_denorm_mode_16_64", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_dx10_clamp", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP);
+  PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_ieee_mode", KD, DefaultKD,
+                       compute_pgm_rsrc1,
+                       amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE);
+  if (isGFX9(STI))
+    PRINT_IF_NOT_DEFAULT(OS, ".amdhsa_fp16_overflow", KD, DefaultKD,
+                         compute_pgm_rsrc1,
+                         amdhsa::COMPUTE_PGM_RSRC1_FP16_OVFL);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_ieee_invalid_op", KD, DefaultKD,
+      compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_denorm_src", KD, DefaultKD, compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_ieee_div_zero", KD, DefaultKD,
+      compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_ieee_overflow", KD, DefaultKD,
+      compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_ieee_underflow", KD, DefaultKD,
+      compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_fp_ieee_inexact", KD, DefaultKD, compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT);
+  PRINT_IF_NOT_DEFAULT(
+      OS, ".amdhsa_exception_int_div_zero", KD, DefaultKD, compute_pgm_rsrc2,
+      amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO);
+#undef PRINT_IF_NOT_DEFAULT
+
+  OS << "\t.end_amdhsa_kernel\n";
 }
 
 //===----------------------------------------------------------------------===//
 // AMDGPUTargetELFStreamer
 //===----------------------------------------------------------------------===//
 
 AMDGPUTargetELFStreamer::AMDGPUTargetELFStreamer(
     MCStreamer &S, const MCSubtargetInfo &STI)
void AMDGPUTargetELFStreamer::EmitAMDGPUNote(
   S.EmitIntValue(NoteType, 4);                                // type
   S.EmitBytes(StringRef(ElfNote::NoteName, NameSZ));          // name
   S.EmitValueToAlignment(4, 0, 1, 0);                         // padding 0
   EmitDesc(S);                                                // desc
   S.EmitValueToAlignment(4, 0, 1, 0);                         // padding 0
   S.PopSection();
 }
 
-void
-AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(uint32_t Major,
-                                                           uint32_t Minor) {
+void AMDGPUTargetELFStreamer::EmitDirectiveAMDGCNTarget(StringRef Target) {}
+
+void AMDGPUTargetELFStreamer::EmitDirectiveHSACodeObjectVersion(
+    uint32_t Major, uint32_t Minor) {
 
   EmitAMDGPUNote(
     MCConstantExpr::create(8, getContext()),
     ElfNote::NT_AMDGPU_HSA_CODE_OBJECT_VERSION,
     [&](MCELFStreamer &OS){
       OS.EmitIntValue(Major, 4);
       OS.EmitIntValue(Minor, 4);
     }
[&](MCELFStreamer &OS){
       for (auto I : PALMetadata)
         OS.EmitIntValue(I, sizeof(uint32_t));
     }
   );
   return true;
 }
 
 void AMDGPUTargetELFStreamer::EmitAmdhsaKernelDescriptor(
-    StringRef KernelName,
-    const amdhsa::kernel_descriptor_t &KernelDescriptor) {
+    StringRef KernelName, const amdhsa::kernel_descriptor_t &KernelDescriptor,
+    const MCSubtargetInfo &STI) {
   auto &Streamer = getStreamer();
   auto &Context = Streamer.getContext();
   auto &ObjectFileInfo = *Context.getObjectFileInfo();
   auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
 
   Streamer.PushSection();
   Streamer.SwitchSection(&ReadOnlySection);
 

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h

 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
 
 #include "AMDGPU.h"
 #include "AMDKernelCodeT.h"
 #include "SIDefines.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Support/AMDHSAKernelDescriptor.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/ErrorHandling.h"
 #include <cstdint>
 #include <string>
 #include <utility>
 
 namespace llvm {
 
int getMaskedMIMGAtomicOp(const MCInstrInfo &MII,
                           unsigned Opc, unsigned NewChannels);
 
 LLVM_READONLY
 int getMCOpcode(uint16_t Opcode, unsigned Gen);
 
 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
                                const FeatureBitset &Features);
 
+amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor();
+
 bool isGroupSegment(const GlobalValue *GV);
 bool isGlobalSegment(const GlobalValue *GV);
 bool isReadOnlySegment(const GlobalValue *GV);
 
 /// \returns True if constants should be emitted to .text section for given
 /// target triple \p TT, false otherwise.
 bool shouldEmitConstantsToTextSection(const Triple &TT);
 

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
 
   // These alignment values are specified in powers of two, so alignment =
   // 2^n.  The minimum alignment is 2^4 = 16.
   Header.kernarg_segment_alignment = 4;
   Header.group_segment_alignment = 4;
   Header.private_segment_alignment = 4;
 }
 
+amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor() {
+  amdhsa::kernel_descriptor_t KD;
+  memset(&KD, 0, sizeof(KD));
+  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
+                  amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
+                  amdhsa::FLOAT_DENORM_MODE_FLUSH_NONE);
+  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
+                  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, 1);
+  AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
+                  amdhsa::COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE, 1);
+  return KD;
+}
+
 bool isGroupSegment(const GlobalValue *GV) {
   return GV->getType()->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
 }
 
 bool isGlobalSegment(const GlobalValue *GV) {
   return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
 }
 

test/MC/AMDGPU/hsa-diag-v3.s

+// RUN: not llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s
+// RUN: not llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd- -mcpu=gfx803 -mattr=+xnack -show-encoding %s 2>&1 >/dev/null | FileCheck %s --check-prefix=NOT-AMDHSA
+
+.text
+
+.amdgcn_target "amdgcn--amdhsa-gfx803+xnack"
+// CHECK: error: target must match options
+
+.amdhsa_kernel
+// CHECK: error: unknown directive
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  .amdhsa_group_segment_fixed_size -1
+  // CHECK: error: value out of range
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  .amdhsa_group_segment_fixed_size 10000000000 + 1
+  // CHECK: error: value out of range
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  // NOT-AMDHSA: error: directive only supported for amdhsa OS
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  .amdhsa_group_segment_fixed_size 1
+  .amdhsa_group_segment_fixed_size 1
+  // CHECK: error: .amdhsa_ directives cannot be repeated
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  // CHECK: error: .amdhsa_vgpr_count directive is required
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  .amdhsa_vgpr_count 0
+  // CHECK: error: .amdhsa_sgpr_count directive is required
+.end_amdhsa_kernel
+
+.amdhsa_kernel foo
+  1
+  // CHECK: error: expected .amdhsa_ directive or .end_amdhsa_kernel
+.end_amdhsa_kernel

test/MC/AMDGPU/hsa-v3.s

+// RUN: llvm-mc -mattr=+code-object-v3 -triple amdgcn-amd-amdhsa -mcpu=gfx803 -mattr=+xnack -show-encoding %s | FileCheck %s
+
+.amdgcn_target "amdgcn-amd-amdhsa--gfx803+xnack"
+// CHECK: .amdgcn_target "amdgcn-amd-amdhsa--gfx803+xnack"
+
+.rodata
+// CHECK: .rodata
+
+.amdhsa_kernel minimal
+  .amdhsa_vgpr_count 0
+  .amdhsa_sgpr_count 0
+.end_amdhsa_kernel
+
+// CHECK: .amdhsa_kernel minimal
+// CHECK-NEXT: .amdhsa_vgpr_count 4
+// CHECK-NEXT: .amdhsa_sgpr_count 16
+// CHECK-NEXT: .end_amdhsa_kernel
+
+
+.amdhsa_kernel complete
+  .amdhsa_group_segment_fixed_size 1
+  .amdhsa_private_segment_fixed_size 1
+  .amdhsa_user_sgpr_private_segment_buffer 1
+  .amdhsa_user_sgpr_dispatch_ptr 1
+  .amdhsa_user_sgpr_queue_ptr 1
+  .amdhsa_user_sgpr_kernarg_segment_ptr 1
+  .amdhsa_user_sgpr_dispatch_id 1
+  .amdhsa_user_sgpr_flat_scratch_init 1
+  .amdhsa_user_sgpr_private_segment_size 1
+  .amdhsa_user_sgpr_grid_workgroup_count_x 1
+  .amdhsa_user_sgpr_grid_workgroup_count_y 1
+  .amdhsa_user_sgpr_grid_workgroup_count_z 1
+  .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+  .amdhsa_system_sgpr_workgroup_id_x 1
+  .amdhsa_system_sgpr_workgroup_id_y 1
+  .amdhsa_system_sgpr_workgroup_id_z 1
+  .amdhsa_system_sgpr_workgroup_info 1
+  .amdhsa_system_vgpr_workitem_id 1
+  .amdhsa_vgpr_count 5
+  .amdhsa_sgpr_count 17
+  .amdhsa_float_round_mode_32 1
+  .amdhsa_float_round_mode_16_64 1
+  .amdhsa_float_denorm_mode_32 1
+  .amdhsa_float_denorm_mode_16_64 0
+  .amdhsa_dx10_clamp 0
+  .amdhsa_ieee_mode 0
+  .amdhsa_exception_fp_ieee_invalid_op 1
+  .amdhsa_exception_fp_denorm_src 1
+  .amdhsa_exception_fp_ieee_div_zero 1
+  .amdhsa_exception_fp_ieee_overflow 1
+  .amdhsa_exception_fp_ieee_underflow 1
+  .amdhsa_exception_fp_ieee_inexact 1
+  .amdhsa_exception_int_div_zero 1
+.end_amdhsa_kernel
+
+// CHECK: .amdhsa_kernel complete
+// CHECK-NEXT: .amdhsa_group_segment_fixed_size 1
+// CHECK-NEXT: .amdhsa_private_segment_fixed_size 1
+// CHECK-NEXT: .amdhsa_user_sgpr_private_segment_buffer 1
+// CHECK-NEXT: .amdhsa_user_sgpr_dispatch_ptr 1
+// CHECK-NEXT: .amdhsa_user_sgpr_queue_ptr 1
+// CHECK-NEXT: .amdhsa_user_sgpr_kernarg_segment_ptr 1
+// CHECK-NEXT: .amdhsa_user_sgpr_dispatch_id 1
+// CHECK-NEXT: .amdhsa_user_sgpr_flat_scratch_init 1
+// CHECK-NEXT: .amdhsa_user_sgpr_private_segment_size 1
+// CHECK-NEXT: .amdhsa_user_sgpr_grid_workgroup_count_x 1
+// CHECK-NEXT: .amdhsa_user_sgpr_grid_workgroup_count_y 1
+// CHECK-NEXT: .amdhsa_user_sgpr_grid_workgroup_count_z 1
+// CHECK-NEXT: .amdhsa_system_sgpr_private_segment_wavefront_offset 1
+// CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_x 1
+// CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_y 1
+// CHECK-NEXT: .amdhsa_system_sgpr_workgroup_id_z 1
+// CHECK-NEXT: .amdhsa_system_sgpr_workgroup_info 1
+// CHECK-NEXT: .amdhsa_system_vgpr_workitem_id 1
+// CHECK-NEXT: .amdhsa_vgpr_count 8
+// CHECK-NEXT: .amdhsa_sgpr_count 32
+// CHECK-NEXT: .amdhsa_float_round_mode_32 1
+// CHECK-NEXT: .amdhsa_float_round_mode_16_64 1
+// CHECK-NEXT: .amdhsa_float_denorm_mode_32 1
+// CHECK-NEXT: .amdhsa_float_denorm_mode_16_64 0
+// CHECK-NEXT: .amdhsa_dx10_clamp 0
+// CHECK-NEXT: .amdhsa_ieee_mode 0
+// CHECK-NEXT: .amdhsa_exception_fp_ieee_invalid_op 1
+// CHECK-NEXT: .amdhsa_exception_fp_denorm_src 1
+// CHECK-NEXT: .amdhsa_exception_fp_ieee_div_zero 1
+// CHECK-NEXT: .amdhsa_exception_fp_ieee_overflow 1
+// CHECK-NEXT: .amdhsa_exception_fp_ieee_underflow 1
+// CHECK-NEXT: .amdhsa_exception_fp_ieee_inexact 1
+// CHECK-NEXT: .amdhsa_exception_int_div_zero 1
+// CHECK-NEXT: .end_amdhsa_kernel