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artem.tamazov (Artem Tamazov)
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User Since
Jan 15 2016, 6:28 AM (188 w, 8 h)

Recent Activity

Jul 17 2019

artem.tamazov accepted D64629: [AMDGPU][MC] Corrected parsing of branch offsets.

LGTM

Jul 17 2019, 7:05 AM · Restricted Project

Jul 15 2019

artem.tamazov accepted D64729: [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL message.

LGTM

Jul 15 2019, 7:05 AM · Restricted Project
artem.tamazov accepted D64716: [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions.

LGTM!

Jul 15 2019, 7:05 AM · Restricted Project

Jun 14 2019

artem.tamazov accepted D62735: [AMDGPU][MC] Corrected parsing of sendmsg.

LGTM!

Jun 14 2019, 4:56 AM · Restricted Project

Jun 5 2019

artem.tamazov accepted D61125: [AMDGPU][MC] Enabled constant expressions as operands of s_getreg/s_setreg.

Please make this small fix and go ahead.

Jun 5 2019, 7:32 AM · Restricted Project

May 24 2019

artem.tamazov accepted D61017: [AMDGPU][MC] Enabled constant expressions as operands of s_waitcnt.
May 24 2019, 4:56 AM · Restricted Project
artem.tamazov added a comment to D61017: [AMDGPU][MC] Enabled constant expressions as operands of s_waitcnt.

LGTM

May 24 2019, 4:56 AM · Restricted Project

May 20 2019

artem.tamazov accepted D61012: [AMDGPU][MC] Corrected parsing of op_sel* and neg_* modifiers.

Very good, thanks!

May 20 2019, 8:24 AM · Restricted Project

May 16 2019

artem.tamazov accepted D62016: [AMDGPU][MC] Enabled labels as operands of s_call_b64 and s_cbranch_i_fork.

Great, thanks!

May 16 2019, 12:56 PM · Restricted Project
artem.tamazov added a comment to D62016: [AMDGPU][MC] Enabled labels as operands of s_call_b64 and s_cbranch_i_fork.

What would occur if offset exceeds int16 due to destination label is too far?

May 16 2019, 11:16 AM · Restricted Project
artem.tamazov accepted D61009: [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiers.

Looks good.

May 16 2019, 11:10 AM · Restricted Project

Apr 26 2019

artem.tamazov accepted D60768: [AMDGPU][MC] Enabled generic constant expressions as operands.

LGTM. Recommendation: it would be nice if error message will be more descriptive (where is does not require too much work)

Apr 26 2019, 5:14 AM · Restricted Project

Apr 15 2019

artem.tamazov accepted D60624: [AMDGPU][MC] Corrected parsing of SP3 'neg' modifier.

LGTM

Apr 15 2019, 7:16 AM · Restricted Project
artem.tamazov accepted D60621: [AMDGPU][MC] Corrected parsing of registers.

Looks good.

Apr 15 2019, 7:16 AM · Restricted Project
artem.tamazov accepted D60622: [AMDGPU][MC] Corrected handling of "-" before expressions.

LGTM

Apr 15 2019, 7:16 AM · Restricted Project

Mar 27 2019

artem.tamazov accepted D59878: [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes.

None objections.

Mar 27 2019, 12:30 PM · Restricted Project
artem.tamazov accepted D59786: [AMDGPU][MC] Corrected truncation rules for integer inlinable constants to match rules for literals.

LGTM

Mar 27 2019, 12:25 PM · Restricted Project

Mar 14 2019

artem.tamazov added a comment to D59305: [AMDGPU][MC] Corrected handling of tied src for atomic return MUBUF opcodes.
In D59305#1428852, @dp wrote:

Shader programming documents state that MUBUF SOFFSET is "SGPR to supply unsigned byte offset. Must be an SGPR, M0 or inline constant."
Also note that our tests are based on SP3 tables which also allow inline constants.
Of course, using fp inline constants in this context is meaningless.

Mar 14 2019, 5:49 AM · Restricted Project

Feb 21 2019

artem.tamazov accepted D58288: [AMDGPU][MC][GFX8+] Added syntactic sugar for 'vgpr index' operand of instructions s_set_gpr_idx_on and s_set_gpr_idx_mode.

LGTM

Feb 21 2019, 11:19 AM · Restricted Project

Feb 7 2019

artem.tamazov accepted D57889: [AMDGPU][MC] Added support of lds_direct operand.

Looks good from assember's side.

Feb 7 2019, 6:58 AM · Restricted Project

Feb 6 2019

artem.tamazov accepted D57826: [AMDGPU][MC][CODEOBJECT] Added predefined symbols to access GPU minor and stepping numbers.

Good, thanks!

Feb 6 2019, 12:25 PM · Restricted Project

Jan 17 2019

artem.tamazov accepted D56794: [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands.

LGTM

Jan 17 2019, 6:26 AM
artem.tamazov accepted D56847: [AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions.

This patch LGTM

Jan 17 2019, 5:08 AM
artem.tamazov added a comment to D56847: [AMDGPU][MC] Disabled use of 2 different literals with SOP2/SOPC instructions.

Do we support different constants if one is literal and another one is inline constant?

s_and_b32 s2, 2, 1234

AFAIR gpu supports arbitrary number of inline constants.

Jan 17 2019, 5:08 AM
artem.tamazov requested changes to D56794: [AMDGPU][MC][GFX8+][DISASSEMBLER] Corrected 1/2pi value for 64-bit operands.
Jan 17 2019, 4:59 AM

Oct 17 2018

artem.tamazov accepted D53386: AMDGPU: Add options to enable/disable code object v3.

Perhaps I am not the right person to approve this, but LGTM provided that this enables CO v2/v3 switching.
Would it work with "clang -x assembler..." as well?

Oct 17 2018, 2:16 PM

Jul 25 2018

artem.tamazov accepted D49759: Fix llvm::ComputeNumSignBits with some operations and llvm.assume.

Good job, thanks!

Jul 25 2018, 7:53 AM
artem.tamazov accepted D49761: [AMDGPU] Use AssumptionCacheTracker in the divrem32 expansion.

LGTM

Jul 25 2018, 7:47 AM

Jul 5 2018

artem.tamazov reopened D48573: [AMDGPU] Add llvm.amdgcn.fmad.ftz intrinsic.

Perhaps fixes needed.

Jul 5 2018, 10:17 AM

Jun 22 2018

artem.tamazov accepted D48497: AMDHSA: Put old assembler docs back.

LGTM, thanks.

Jun 22 2018, 11:00 AM
artem.tamazov added a comment to D47736: AMDHSA Code Object v3 assembler syntax update.

Is it so that the updated documentation is valid only if code-object-v3 is specified?

Yes

Is the V3 code object compatible with the latest ROCm release?

Not yet

Jun 22 2018, 10:44 AM
artem.tamazov added a comment to D47736: AMDHSA Code Object v3 assembler syntax update.

Is it so that the updated documentation is valid only if code-object-v3 is specified?
Is the V3 code object compatible with the latest ROCm release?

Jun 22 2018, 10:10 AM

Jun 7 2018

artem.tamazov accepted D47885: [AMDGPU][GFX8][GFX9] Allow LDS direct reads for DWORDX2/X3/X4.

LGTM

Jun 7 2018, 10:39 AM
artem.tamazov accepted D47884: [AMDGPU][MC] Enabled parsing of relocations on VALU instructions.

LGTM

Jun 7 2018, 10:15 AM

May 30 2018

artem.tamazov resigned from D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand.

Adding Dmitry as he is more fluent in this domain.

May 30 2018, 3:52 AM

Apr 10 2018

artem.tamazov accepted D45477: AMDGPU/MC: Allow disassembling without symbol info.

LGTM.

Apr 10 2018, 6:23 AM

Apr 9 2018

artem.tamazov accepted D45452: AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header.

LGTM

Apr 9 2018, 1:48 PM
artem.tamazov added a comment to D45452: AMDGPU: Remove max_scratch_backing_memory_byte_size from kernel header.

Is it so that max_scratch_backing_memory_byte_size is not needed at all for Gfx7-9?

Apr 9 2018, 1:27 PM
artem.tamazov accepted D45443: [AMDGPU][MC][GFX9] Added v_screen_partition_4se_b32.

LGTM

Apr 9 2018, 12:02 PM
artem.tamazov accepted D45446: [AMDGPU][MC][VI][GFX9] Added support of SDWA/DPP for v_cndmask_b32.

Looks good.

Apr 9 2018, 11:56 AM

Apr 5 2018

artem.tamazov accepted D45249: [AMDGPU][MC][VI][GFX9] Added s_atc_probe* instructions.

Great, thanks.

Apr 5 2018, 8:56 AM
artem.tamazov accepted D45313: [AMDGPU][MC][GFX9] Added instruction s_endpgm_ordered_ps_done.

Looks good.

Apr 5 2018, 8:55 AM
artem.tamazov accepted D45268: [AMDGPU][MC][GFX9] Added s_call_b64.

LGTM

Apr 5 2018, 8:53 AM

Apr 4 2018

artem.tamazov added a comment to D45250: [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*.
In D45250#1056997, @dp wrote:

Corrected asm tests to use traditional notation (GFX89 instead of VI)

Apr 4 2018, 11:54 AM
artem.tamazov accepted D45250: [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*.

LGTM

Apr 4 2018, 11:54 AM
artem.tamazov added inline comments to D45250: [AMDGPU][MC][GFX9] Added instructions *saveexec*, *wrexec* and *bitreplicate*.
Apr 4 2018, 7:15 AM
artem.tamazov accepted D45251: [AMDGPU][MC][GFX9] Added instructions s_mul_hi_*32, s_lshl*_add_u32.

Looks good.

Apr 4 2018, 7:02 AM
artem.tamazov accepted D45247: [AMDGPU][MC][GFX9] Added s_dcache_discard* instructions.

LGTM.

Apr 4 2018, 5:45 AM

Apr 3 2018

artem.tamazov accepted D45099: [AMDGPU][MC] Enabled instruction TBUFFER_LOAD_FORMAT_XYZ for SI/CI.

Looks good.

Apr 3 2018, 9:22 AM
artem.tamazov accepted D45084: [AMDGPU][MC] Added support of 3-element addresses for MIMG instructions.

Looks good.

Apr 3 2018, 9:20 AM

Mar 27 2018

artem.tamazov accepted D44795: [AMDGPU][MC] Added PCK variants of image load/store instructions.

LGTM

Mar 27 2018, 6:51 AM
artem.tamazov accepted D44832: [AMDGPU][MC][GFX9] Added s_scratch* instructions.

LGTM

Mar 27 2018, 6:44 AM

Mar 26 2018

artem.tamazov accepted D44685: [AMDGPU] Improve disassembler error handling.

Looks good.

Mar 26 2018, 8:42 AM

Mar 23 2018

artem.tamazov accepted D44825: [AMDGPU][MC][GFX9] Added buffer_*_format_d16_hi_x.

LGTM

Mar 23 2018, 7:52 AM
artem.tamazov accepted D44779: [AMDGPU][MC] Added ds_add_src2_f32.

LGTM

Mar 23 2018, 7:50 AM
artem.tamazov added inline comments to D44685: [AMDGPU] Improve disassembler error handling.
Mar 23 2018, 6:46 AM
artem.tamazov added a comment to D44779: [AMDGPU][MC] Added ds_add_src2_f32.
In D44779#1046500, @dp wrote:

But maybe it would be safer to support this opcode for gfx8/9 only to mimic SP3 assembler?

Mar 23 2018, 6:42 AM

Mar 20 2018

artem.tamazov added inline comments to D44685: [AMDGPU] Improve disassembler error handling.
Mar 20 2018, 10:19 AM
artem.tamazov added a comment to D44685: [AMDGPU] Improve disassembler error handling.

This implements Bug 36347

Mar 20 2018, 9:31 AM
artem.tamazov added a comment to D44685: [AMDGPU] Improve disassembler error handling.

Does this resolve any bugzilla?

Mar 20 2018, 9:19 AM
artem.tamazov added a reviewer for D44685: [AMDGPU] Improve disassembler error handling: dp.

Adding Dmitry.

Mar 20 2018, 9:19 AM

Mar 15 2018

artem.tamazov accepted D44529: [AMDGPU][MC][GFX8][GFX9][DISASSEMBLER] Added "_e32" suffix to 32-bit VINTRP opcodes.

LGTM

Mar 15 2018, 11:49 AM
artem.tamazov accepted D44481: [AMDGPU][MC] Corrected default values for unused SDWA operands.

LGTM

Mar 15 2018, 5:10 AM

Mar 7 2018

artem.tamazov added a comment to D44163: [AMDGPU] Add default ISA version targets.

It seems that -mattr corrupts the design. What is the purpose of this option?

Mar 7 2018, 5:24 AM

Mar 6 2018

artem.tamazov added a comment to D43950: [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction.

Dmitry, I believe you can go ahead.

Mar 6 2018, 5:36 AM

Mar 5 2018

artem.tamazov accepted D44020: [AMDGPU][MC][DOC] Updated AMD GPU assembler description.

LGTM

Mar 5 2018, 5:46 AM

Mar 1 2018

artem.tamazov accepted D43950: [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction.
In D43950#1024132, @dp wrote:

Regarding TFE, documentation says that TFE is valid for "fetch" instructions only. By design, TFE is useless with stores.
I believe this instruction is not a "fetch".

Mar 1 2018, 11:30 AM
artem.tamazov requested changes to D43950: [AMDGPU][MC][GFX8] Added BUFFER_STORE_LDS_DWORD Instruction.

The change requires LDS bit in BUFFER_STORE_LDS_DWORD. This looks incorrect. LDS bit affects only MUBUF reads.

Mar 1 2018, 10:07 AM
artem.tamazov accepted D43874: [AMDGPU][MC] Corrected definition of GATHER4 opcodes.

LGTM

Mar 1 2018, 5:44 AM
artem.tamazov added inline comments to D43874: [AMDGPU][MC] Corrected definition of GATHER4 opcodes.
Mar 1 2018, 4:42 AM

Feb 20 2018

artem.tamazov added a comment to D43472: [AMDGPU][MC] Added lds support for MUBUF.
In D43472#1013187, @dp wrote:

LGTM. I recommend adding an erratic case with both "lds" and "tfe" to the tests.

Added...

Feb 20 2018, 7:38 AM
artem.tamazov accepted D43472: [AMDGPU][MC] Added lds support for MUBUF.

LGTM. I recommend adding an erratic case with both "lds" and "tfe" to the tests.

Feb 20 2018, 4:29 AM

Feb 3 2018

artem.tamazov accepted D42847: [AMDGPU][MC] Corrected dst/data size for MIMG opcodes with d16 modifier.

Looks good except come comments.

Feb 3 2018, 4:44 AM

Feb 2 2018

artem.tamazov accepted D42692: [AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes.
Feb 2 2018, 4:19 AM

Feb 1 2018

artem.tamazov added inline comments to D42692: [AMDGPU][MC] Added validation of d16 and r128 modifiers of MIMG opcodes.
Feb 1 2018, 8:52 AM

Jan 25 2018

artem.tamazov accepted D42483: [AMDGPU][MC] Added validation of image dst/data size (must match dmask and tfe).
Jan 25 2018, 7:19 AM
artem.tamazov accepted D42469: [AMDGPU][MC] Added support of 64-bit image atomics.
Jan 25 2018, 7:19 AM
artem.tamazov accepted D42186: [AMDGPU][MC] Enabled disassembler for image atomic operations.

LGTM.
BTW it would be nice to have a comment explaining the limitations of MIMG support. In short:

  • There is a fundamental limitation: only index of the beginning VGPR of address and data is specified/encoded. The number of actually used VGPRs are set implicitly (in the T#) and thus not known during assembling and disassembling.
  • This limitation can not be overcame unless violation of the SP3 compatibility requirement
  • Also there is a drawback related to CodeGen: the number of used VGPRs can be set to the power of 2 only, but actual number of VGPRs used is more diverse.
Jan 25 2018, 6:46 AM

Jan 18 2018

artem.tamazov added a comment to D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

I believe the source of inconsistency is the original definition of ID_SYMBOLIC_LAST_, which does not point to a last value in the enum, but a last + 1. This can be changed in a separate patch.

Jan 18 2018, 7:52 AM
artem.tamazov added a comment to D42186: [AMDGPU][MC] Enabled disassembler for image atomic operations.
In D42186#980293, @dp wrote:

This is an interesting idea, but T# is assumed to be in registers. Also note that GFX10 added a 'dim' field to encode address size.

Jan 18 2018, 7:38 AM
artem.tamazov added a comment to D42186: [AMDGPU][MC] Enabled disassembler for image atomic operations.

Dmitry, please consider the following (excerpt from GCN ISA manual):

Jan 18 2018, 6:59 AM
artem.tamazov accepted D42184: [AMDGPU][MC] Corrected parsing of image opcode modifiers and encoding of image atomics.

LGTM

Jan 18 2018, 6:28 AM

Jan 16 2018

artem.tamazov added a comment to D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

Let's reach consensus.

Jan 16 2018, 1:29 AM

Jan 15 2018

artem.tamazov accepted D42058: [AMDGPU][MC][GFX9] Enable inline constants for SDWA.

If possible, please add some negative test(s), i.e. SDWA with non-inlineable constant(s). See also style-related recommendation. Otherwise fine.

Jan 15 2018, 7:01 AM

Jan 9 2018

artem.tamazov accepted D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

Some style-related fixes are desirable, otherwise LGTM.

Jan 9 2018, 8:20 AM
artem.tamazov accepted D41614: [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support.
Jan 9 2018, 8:01 AM

Dec 29 2017

artem.tamazov added a comment to D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

Please also add some testcases to test\MC\AMDGPU\sopk.s and, possibly, to sopk-err.s.

Dec 29 2017, 5:37 AM
artem.tamazov requested changes to D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.
Dec 29 2017, 5:36 AM
artem.tamazov added a comment to D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

Actually HW_REG_SH_MEM_BASES is available starting from Gfx9. Is it possible to make it unavailable for Gfx7/8?

Dec 29 2017, 5:29 AM
artem.tamazov accepted D41617: [AMDGPU] Add HW_REG_SH_MEM_BASES symbolic name for s_getreg_b32.

LGTM

Dec 29 2017, 5:23 AM

Dec 28 2017

artem.tamazov added inline comments to D41614: [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support.
Dec 28 2017, 8:57 AM
artem.tamazov accepted D41598: [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers.
In D41598#964823, @dp wrote:

Note that the following code is assembled ok, though 'glc' is omitted:

flat_atomic_cmpswap v0, v[1:2], v[3:4]

This would not be easy to fix, and I think we should presume this a 'feature' :-)

Dec 28 2017, 7:07 AM
artem.tamazov accepted D41614: [AMDGPU][MC][GFX8][GFX9] Added XNACK_MASK support.
Dec 28 2017, 5:13 AM
artem.tamazov requested changes to D41598: [AMDGPU][MC] Incorrect parsing of flat/global atomic modifiers.

Please add negative tests: (a) VDST present but none GLC and (b) none VDST but GLC presents. Otherwise fine.

Dec 28 2017, 5:04 AM

Dec 21 2017

artem.tamazov accepted D41488: [AMDGPU][MC] Corrected handling of negative expressions.
Dec 21 2017, 7:16 AM

Dec 20 2017

artem.tamazov accepted D41437: [AMDGPU][MC] Added support of 256- and 512-bit tuples of ttmp registers.

LGTM. I see that SGPR and VGPR support also reworked here. Please mention that in the commit.

Dec 20 2017, 5:48 AM

Dec 14 2017

artem.tamazov accepted D41186: [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32.

LGTM.

Dec 14 2017, 7:28 AM

Dec 8 2017

artem.tamazov accepted D41007: [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma.
Dec 8 2017, 8:37 AM
artem.tamazov added inline comments to D41007: [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma.
Dec 8 2017, 8:35 AM
artem.tamazov added inline comments to D41007: [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma.
Dec 8 2017, 7:57 AM