- User Since
- Jan 15 2016, 6:28 AM (188 w, 8 h)
Jul 17 2019
Jul 15 2019
Jun 14 2019
Jun 5 2019
Please make this small fix and go ahead.
May 24 2019
May 20 2019
Very good, thanks!
May 16 2019
What would occur if offset exceeds int16 due to destination label is too far?
Apr 26 2019
LGTM. Recommendation: it would be nice if error message will be more descriptive (where is does not require too much work)
Apr 15 2019
Mar 27 2019
Mar 14 2019
Feb 21 2019
Feb 7 2019
Looks good from assember's side.
Feb 6 2019
Jan 17 2019
This patch LGTM
Do we support different constants if one is literal and another one is inline constant?
s_and_b32 s2, 2, 1234
AFAIR gpu supports arbitrary number of inline constants.
Oct 17 2018
Perhaps I am not the right person to approve this, but LGTM provided that this enables CO v2/v3 switching.
Would it work with "clang -x assembler..." as well?
Jul 25 2018
Good job, thanks!
Jul 5 2018
Perhaps fixes needed.
Jun 22 2018
Is it so that the updated documentation is valid only if code-object-v3 is specified?
Is the V3 code object compatible with the latest ROCm release?
Jun 7 2018
May 30 2018
Adding Dmitry as he is more fluent in this domain.
Apr 10 2018
Apr 9 2018
Is it so that max_scratch_backing_memory_byte_size is not needed at all for Gfx7-9?
Apr 5 2018
Apr 4 2018
Apr 3 2018
Mar 27 2018
Mar 26 2018
Mar 23 2018
Mar 20 2018
Does this resolve any bugzilla?
Mar 15 2018
Mar 7 2018
It seems that -mattr corrupts the design. What is the purpose of this option?
Mar 6 2018
Dmitry, I believe you can go ahead.
Mar 5 2018
Mar 1 2018
The change requires LDS bit in BUFFER_STORE_LDS_DWORD. This looks incorrect. LDS bit affects only MUBUF reads.
Feb 20 2018
LGTM. I recommend adding an erratic case with both "lds" and "tfe" to the tests.
Feb 3 2018
Looks good except come comments.
Feb 2 2018
Feb 1 2018
Jan 25 2018
BTW it would be nice to have a comment explaining the limitations of MIMG support. In short:
- There is a fundamental limitation: only index of the beginning VGPR of address and data is specified/encoded. The number of actually used VGPRs are set implicitly (in the T#) and thus not known during assembling and disassembling.
- This limitation can not be overcame unless violation of the SP3 compatibility requirement
- Also there is a drawback related to CodeGen: the number of used VGPRs can be set to the power of 2 only, but actual number of VGPRs used is more diverse.
Jan 18 2018
Dmitry, please consider the following (excerpt from GCN ISA manual):
Jan 16 2018
Let's reach consensus.
Jan 15 2018
If possible, please add some negative test(s), i.e. SDWA with non-inlineable constant(s). See also style-related recommendation. Otherwise fine.
Jan 9 2018
Some style-related fixes are desirable, otherwise LGTM.
Dec 29 2017
Please also add some testcases to test\MC\AMDGPU\sopk.s and, possibly, to sopk-err.s.
Actually HW_REG_SH_MEM_BASES is available starting from Gfx9. Is it possible to make it unavailable for Gfx7/8?
Dec 28 2017
Please add negative tests: (a) VDST present but none GLC and (b) none VDST but GLC presents. Otherwise fine.
Dec 21 2017
Dec 20 2017
LGTM. I see that SGPR and VGPR support also reworked here. Please mention that in the commit.
Dec 14 2017