AMDGPU/AMDHSA: Remove GridWorkGroupCountX/Y/Z

[kzhuravl]

Summary

and everything that comes with it from implementation and v3 header files.

Leave definition in v2 header files for backwards compatibility.

[scott.linder]

LGTM

llvm/trunk/docs/AMDGPUUsage.rst

448     1 bit   ENABLE_SGPR_PRIVATE_SEGMENT     Enable the setup of the
                                                      will be ignored.
      449     1 bit   ENABLE_SGPR_DISPATCH_PTR        *see above*
      450     1 bit   ENABLE_SGPR_QUEUE_PTR           *see above*
      451     1 bit   ENABLE_SGPR_KERNARG_SEGMENT_PTR *see above*
      452     1 bit   ENABLE_SGPR_DISPATCH_ID         *see above*
      453     1 bit   ENABLE_SGPR_FLAT_SCRATCH_INIT   *see above*
      454     1 bit   ENABLE_SGPR_PRIVATE_SEGMENT     *see above*
                      _SIZE
-     455     1 bit   ENABLE_SGPR_GRID_WORKGROUP      Not implemented in CP and
-                     _COUNT_X                        should always be 0.
-     456     1 bit   ENABLE_SGPR_GRID_WORKGROUP      Not implemented in CP and
-                     _COUNT_Y                        should always be 0.
-     457     1 bit   ENABLE_SGPR_GRID_WORKGROUP      Not implemented in CP and
-                     _COUNT_Z                        should always be 0.
-     463:458 6 bits                                  Reserved, must be 0.
-     511:464 6                                       Reserved, must be 0.
-             bytes
+     455     1 bit                                   Reserved, must be 0.
+     511:456 8 bytes                                 Reserved, must be 0.
      512     **Total size 64 bytes.**
      ======= ====================================================================
 
 ..
 
   .. table:: compute_pgm_rsrc1 for GFX6-GFX9
      :name: amdgpu-amdhsa-compute_pgm_rsrc1-gfx6-gfx9-table
 

llvm/trunk/include/llvm/Support/AMDHSAKernelDescriptor.h

 enum : int32_t {
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER, 0, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_PTR, 1, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_QUEUE_PTR, 2, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_KERNARG_SEGMENT_PTR, 3, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_DISPATCH_ID, 4, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_FLAT_SCRATCH_INIT, 5, 1),
   KERNEL_CODE_PROPERTY(ENABLE_SGPR_PRIVATE_SEGMENT_SIZE, 6, 1),
-  KERNEL_CODE_PROPERTY(ENABLE_SGPR_GRID_WORKGROUP_COUNT_X, 7, 1),
-  KERNEL_CODE_PROPERTY(ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y, 8, 1),
-  KERNEL_CODE_PROPERTY(ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z, 9, 1),
-  KERNEL_CODE_PROPERTY(RESERVED, 10, 6),
+  KERNEL_CODE_PROPERTY(RESERVED, 7, 9),
 };
 #undef KERNEL_CODE_PROPERTY
 
 // Kernel descriptor. Must be kept backwards compatible.
 struct kernel_descriptor_t {
   uint32_t group_segment_fixed_size;
   uint32_t private_segment_fixed_size;
   uint8_t reserved0[8];

llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h

struct AMDGPUFunctionArgInfo {
   // XXX - Can these require argument spills?
   ArgDescriptor PrivateSegmentBuffer;
   ArgDescriptor DispatchPtr;
   ArgDescriptor QueuePtr;
   ArgDescriptor KernargSegmentPtr;
   ArgDescriptor DispatchID;
   ArgDescriptor FlatScratchInit;
   ArgDescriptor PrivateSegmentSize;
-  ArgDescriptor GridWorkGroupCountX;
-  ArgDescriptor GridWorkGroupCountY;
-  ArgDescriptor GridWorkGroupCountZ;
 
   // System SGPRs in kernels.
   ArgDescriptor WorkGroupIDX;
   ArgDescriptor WorkGroupIDY;
   ArgDescriptor WorkGroupIDZ;
   ArgDescriptor WorkGroupInfo;
   ArgDescriptor PrivateSegmentWaveByteOffset;
 

llvm/trunk/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp

for (const auto &FI : ArgInfoMap) {
     OS << "Arguments for " << FI.first->getName() << '\n'
        << "  PrivateSegmentBuffer: " << FI.second.PrivateSegmentBuffer
        << "  DispatchPtr: " << FI.second.DispatchPtr
        << "  QueuePtr: " << FI.second.QueuePtr
        << "  KernargSegmentPtr: " << FI.second.KernargSegmentPtr
        << "  DispatchID: " << FI.second.DispatchID
        << "  FlatScratchInit: " << FI.second.FlatScratchInit
        << "  PrivateSegmentSize: " << FI.second.PrivateSegmentSize
-       << "  GridWorkgroupCountX: " << FI.second.GridWorkGroupCountX
-       << "  GridWorkgroupCountY: " << FI.second.GridWorkGroupCountY
-       << "  GridWorkgroupCountZ: " << FI.second.GridWorkGroupCountZ
        << "  WorkGroupIDX: " << FI.second.WorkGroupIDX
        << "  WorkGroupIDY: " << FI.second.WorkGroupIDY
        << "  WorkGroupIDZ: " << FI.second.WorkGroupIDZ
        << "  WorkGroupInfo: " << FI.second.WorkGroupInfo
        << "  PrivateSegmentWaveByteOffset: "
           << FI.second.PrivateSegmentWaveByteOffset
        << "  ImplicitBufferPtr: " << FI.second.ImplicitBufferPtr
        << "  ImplicitArgPtr: " << FI.second.ImplicitArgPtr

llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
   if (MFI.hasDispatchID()) {
     KernelCodeProperties |=
         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
   }
   if (MFI.hasFlatScratchInit()) {
     KernelCodeProperties |=
         amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
   }
-  if (MFI.hasGridWorkgroupCountX()) {
-    KernelCodeProperties |=
-        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
-  }
-  if (MFI.hasGridWorkgroupCountY()) {
-    KernelCodeProperties |=
-        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
-  }
-  if (MFI.hasGridWorkgroupCountZ()) {
-    KernelCodeProperties |=
-        amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
-  }
 
   return KernelCodeProperties;
 }
 
 amdhsa::kernel_descriptor_t AMDGPUAsmPrinter::getAmdhsaKernelDescriptor(
     const MachineFunction &MF,
     const SIProgramInfo &PI) const {
   amdhsa::kernel_descriptor_t KernelDescriptor;
if (MFI->hasKernargSegmentPtr())
     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
 
   if (MFI->hasDispatchID())
     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
 
   if (MFI->hasFlatScratchInit())
     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
 
-  if (MFI->hasGridWorkgroupCountX()) {
-    Out.code_properties |=
-      AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_X;
-  }
-
-  if (MFI->hasGridWorkgroupCountY()) {
-    Out.code_properties |=
-      AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Y;
-  }
-
-  if (MFI->hasGridWorkgroupCountZ()) {
-    Out.code_properties |=
-      AMD_CODE_PROPERTY_ENABLE_SGPR_GRID_WORKGROUP_COUNT_Z;
-  }
-
   if (MFI->hasDispatchPtr())
     Out.code_properties |= AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
 
   if (STM.debuggerSupported())
     Out.code_properties |= AMD_CODE_PROPERTY_IS_DEBUG_SUPPORTED;
 
   if (STM.isXNACKEnabled())
     Out.code_properties |= AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED;

llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h

private:
 
   // Feature bits required for inputs passed in user SGPRs.
   bool PrivateSegmentBuffer : 1;
   bool DispatchPtr : 1;
   bool QueuePtr : 1;
   bool KernargSegmentPtr : 1;
   bool DispatchID : 1;
   bool FlatScratchInit : 1;
-  bool GridWorkgroupCountX : 1;
-  bool GridWorkgroupCountY : 1;
-  bool GridWorkgroupCountZ : 1;
 
   // Feature bits required for inputs passed in system SGPRs.
   bool WorkGroupIDX : 1; // Always initialized.
   bool WorkGroupIDY : 1;
   bool WorkGroupIDZ : 1;
   bool WorkGroupInfo : 1;
   bool PrivateSegmentWaveByteOffset : 1;
 
public:
   bool hasDispatchID() const {
     return DispatchID;
   }
 
   bool hasFlatScratchInit() const {
     return FlatScratchInit;
   }
 
-  bool hasGridWorkgroupCountX() const {
-    return GridWorkgroupCountX;
-  }
-
-  bool hasGridWorkgroupCountY() const {
-    return GridWorkgroupCountY;
-  }
-
-  bool hasGridWorkgroupCountZ() const {
-    return GridWorkgroupCountZ;
-  }
-
   bool hasWorkGroupIDX() const {
     return WorkGroupIDX;
   }
 
   bool hasWorkGroupIDY() const {
     return WorkGroupIDY;
   }
 

llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
   : AMDGPUMachineFunction(MF),
     PrivateSegmentBuffer(false),
     DispatchPtr(false),
     QueuePtr(false),
     KernargSegmentPtr(false),
     DispatchID(false),
     FlatScratchInit(false),
-    GridWorkgroupCountX(false),
-    GridWorkgroupCountY(false),
-    GridWorkgroupCountZ(false),
     WorkGroupIDX(false),
     WorkGroupIDY(false),
     WorkGroupIDZ(false),
     WorkGroupInfo(false),
     PrivateSegmentWaveByteOffset(false),
     WorkItemIDX(false),
     WorkItemIDY(false),
     WorkItemIDZ(false),