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[AArch64][SVE] Asm: Support for contiguous ST1 (scalar+imm) store instructions.
ClosedPublic

Authored by sdesmalen on Apr 9 2018, 2:35 AM.

Details

Summary

Added instructions for contiguous stores, ST1, with scalar+imm addressing
modes and corresponding tests. The patch also adds parsing of
'mul vl' as needed for the VL-scaled immediate.

This is patch [6/6] in a series to add assembler/disassembler support for
SVE's contiguous ST1 (scalar+imm) instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

sdesmalen created this revision.Apr 9 2018, 2:35 AM
rengolin added inline comments.Apr 12 2018, 9:21 AM
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
3121 ↗(On Diff #141607)

So mul vl is exclusive with shift or extend? I ask because you return if you find it.

sdesmalen added inline comments.Apr 12 2018, 9:24 AM
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
3121 ↗(On Diff #141607)

Correct, they are mutually exclusive.

rengolin accepted this revision.Apr 13 2018, 3:20 AM

LTM, thanks!

This revision is now accepted and ready to land.Apr 13 2018, 3:20 AM
This revision was automatically updated to reflect the committed changes.