[SchedModel] Remove instregex entries that don't match any instructions (WIP)

[RKSimon]

Summary

This patch throws a fatal error if an instregex entry doesn't actually match any instructions. This is part of the work to reduce the compile time impact of increased instregex usage (PR35955), although the x86 models seem to be relatively clean.

I've included hacks for all the cases I encountered, I don't know if I've fixed them correctly though (e.g. AArch64SchedThunderX2T99 has a lot of duplicate patterns for its ALU instructions).

I've also included a disabled error for cases where the instregex only matches one instruction - which IMO should probably be replaced with a instrs entry - this might be worth just a warning or we remove it from the patch completely (but it'd definitely improve compile time).

[andreadb]

The changes to CodeGenSchedule.cpp looks good to me. I will let other people review the AArch64/ARM scheduling model changes.
P.s.: I also like the idea of having a warning (at least in debug mode) for when there is only one matching instruction.

[craig.topper]

utils/TableGen/CodeGenSchedule.cpp

107–109

Do we need two loops here? Why are we building a list of Regexs and the iterating over it?

[RKSimon]

utils/TableGen/CodeGenSchedule.cpp

107–109

I haven't looked into the history of this code, although I think @bkramer refactored some of it not so long ago.

I agree that the loops should probably be merged, I'm happy to cleanup this up as long as it doesn't get in the way of people investigating the issues in the models.

[craig.topper]

I'd like to see the loops merged to get rid of the nested std::pairs. But yeah I don't want to get in the way of fixing all the targets.

The X86 changes look to me. That FMA was one in Zen is interesting. Does the the ZnWriteResFpuPair for FMA have the right information that prevented that from affecting tests?

[RKSimon]

In D44687#1043542, @craig.topper wrote:

I'd like to see the loops merged to get rid of the nested std::pairs. But yeah I don't want to get in the way of fixing all the targets.

The X86 changes look to me. That FMA was one in Zen is interesting. Does the the ZnWriteResFpuPair for FMA have the right information that prevented that from affecting tests?

Yes, the override is probably redundant - see PR35548

[RKSimon]

Rebased

[fhahn]

lib/Target/AArch64/AArch64SchedThunderX2T99.td

426 ↗

(On Diff #139217)

Those changes should be fine (and similar changes below), as they just remove invalid patterns.

1264 ↗

(On Diff #139217)

MOV (AdvSIMD) is an alias for INS. MVN is an alias of NOT. So I think to keep the model unchanged, we should use INS and NOT here.

@joelkevinjones @steleman could you have a quick look to confirm?

Also, the comment just above needs updating.

1516 ↗

(On Diff #139217)

Looks OK, MOVIv should match vector versions of MOVI.

[RKSimon]

@fhahn Would you be willing to commit those scheduler fixes yourself? Ideally I should be able to commit this patch as just the CodeGenSchedule.cpp changes with all the model fixes already in.

[fhahn]

In D44687#1044233, @RKSimon wrote:

@fhahn Would you be willing to commit those scheduler fixes yourself? Ideally I should be able to commit this patch as just the CodeGenSchedule.cpp changes with all the model fixes already in.

Yep, I can commit the AArch64 changes. I'll wait till tomorrow, in case Joel or Stefan have any concerns.

[javed.absar]

Thanks for this. If I am getting this right, just like CompleteModel ensures no instruction has a missing schedule, this patch will ensure no instruction has multiple schedule (instregex) assigned?

lib/Target/ARM/ARMScheduleR52.td

224

Not sure why you removed 't2MOV_ga_pcrel_ldr' ? Is it repeated somewhere else ?

283

t2MLALBB missing?

utils/TableGen/CodeGenSchedule.cpp

153

Just wondering why having 'just one match' would be a problem?

[RKSimon]

In D44687#1044503, @javed.absar wrote:

Thanks for this. If I am getting this right, just like CompleteModel ensures no instruction has a missing schedule, this patch will ensure no instruction has multiple schedule (instregex) assigned?

Not quite (thats another check that I'll be adding soon....) - this patch just errors out if the instregex is not used at all - from the cases I've seen its usually a mixture of copy+paste (not all instructions have all the same variations) and typos in the regex pattern.

[craig.topper]

This patch makes sure each regular expression covers at least one instruction. We already checked that each InstRW line matched at least one instruction. But if there were multiple regular expressions listed, we didn't check it.

Making sure each instruction is only covered by one instregex or instrs match is already being done. And a hole in it was fixed recently with r327808. Though I had to disable the improved check on some models. Look for FullInstRWOverlapCheck = 0 in the SchedMachineModel in the td files to see if I disabled it for any schedulers you care about. I need to collect the effected schedulers and start getting people to fix it.

lib/Target/ARM/ARMScheduleR52.td

224

According to ARMGenInstrInfo.inc, there is no t2MOV_ga_pcrel_ldr

283

t2MLALBB doesn't exist in ARMGenInstrInfo.inc

utils/TableGen/CodeGenSchedule.cpp

153

Having just one match means you should probably be using "(instrs" instead of "(instregex". The regular expression has to get tried on every instruction name that is defined. If there's ever only going to be one match that just wastes tablegen build time.

[RKSimon]

lib/Target/ARM/ARMScheduleR52.td

224

Searching through ARMGenInstrInfo.inc I could see MOV_ga_pcrel_ldr but not t2MOV_ga_pcrel_ldr - that was what caused the error.

283

Yup - doesn't exist in ARMGenInstrInfo.inc

utils/TableGen/CodeGenSchedule.cpp

153

Every regex pattern has to match against every instruction string - its quite costly - we're looking at ways to speed this up (PR35955).

I'm not sure about enabling this - that's (a) why its currently #if'd out and (b) why I might reduce this to a warning if we keep it at all.

[javed.absar]

In D44687#1044554, @craig.topper wrote:

This patch makes sure each regular expression covers at least one instruction. We already checked that each InstRW line matched at least one instruction. But if there were multiple regular expressions listed, we didn't check it.

Making sure each instruction is only covered by one instregex or instrs match is already being done. And a hole in it was fixed recently with r327808. Though I had to disable the improved check on some models. Look for FullInstRWOverlapCheck = 0 in the SchedMachineModel in the td files to see if I disabled it for any schedulers you care about. I need to collect the effected schedulers and start getting people to fix it.

OK, I missed that. Please add R52 to your list. FullInstRWOverlapCheck idea is great. When there is overlap, would it be possible to check if the Defs are identical (less serious case) as opposed to two conflicting sched for same instruction? Sorry, maybe i should ask in a separate review (please point me to it).

[GGanesh]

lib/Target/X86/X86ScheduleZnver1.td

919 ↗

(On Diff #139217)

Looks okay to me.

[fhahn]

In D44687#1044247, @fhahn wrote:

In D44687#1044233, @RKSimon wrote:

@fhahn Would you be willing to commit those scheduler fixes yourself? Ideally I should be able to commit this patch as just the CodeGenSchedule.cpp changes with all the model fixes already in.

Yep, I can commit the AArch64 changes. I'll wait till tomorrow, in case Joel or Stefan have any concerns.

Done, rL328303

[RKSimon]

Rebased after recent scheduler fixes - just the ARM cases still need to be reviewed/committed now.

I've removed the single match code - we can revisit this in the future but for now the number of warnings is just too much for a buildtime performance issues. I'll try to work on at least fixing the x86 cases.

[javed.absar]

LGTM

[GGanesh]

Looks good to me!

lib/Target/ARM/ARMScheduleA9.td

 
 def : SchedAlias<WriteCMP, A9WriteALU>;
 def : SchedAlias<WriteCMPsi, A9WriteALU>;
 def : SchedAlias<WriteCMPsr, A9WriteALU>;
 
 def : InstRW< [A9WriteIsr], (instregex "MOVsr", "MOVsi", "MVNsr", "MOVCCsi",
                                        "MOVCCsr")>;
 def : InstRW< [WriteALU, A9ReadALU], (instregex "MVNr")>;
-def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm",
-                                      "MOV_ga_dyn")>;
+def : InstRW< [A9WriteI2], (instregex "MOVCCi32imm", "MOVi32imm")>;
 def : InstRW< [A9WriteI2pc], (instregex "MOV_ga_pcrel")>;
 def : InstRW< [A9WriteI2ld], (instregex "MOV_ga_pcrel_ldr")>;
 
 def : InstRW< [WriteALU], (instregex "SEL")>;
 
 def : InstRW< [WriteALUsi], (instregex "BFC", "BFI", "UBFX", "SBFX")>;
 
 def : InstRW< [A9WriteM],
       (instregex "MUL", "MULv5", "SMMUL", "SMMULR", "MLA", "MLAv5", "MLS",
       "SMMLA", "SMMLAR", "SMMLS", "SMMLSR")>;
 def : InstRW< [A9WriteM, A9WriteMHi],
       (instregex "SMULL", "SMULLv5", "UMULL", "UMULLv5", "SMLAL$", "UMLAL",
-      "UMAAL", "SMLALv5", "UMLALv5", "UMAALv5", "SMLALBB", "SMLALBT", "SMLALTB",
+      "UMAAL", "SMLALv5", "UMLALv5", "SMLALBB", "SMLALBT", "SMLALTB",
       "SMLALTT")>;
 // FIXME: These instructions used to have NoItinerary. Just copied the one from above.
 def : InstRW< [A9WriteM, A9WriteMHi],
       (instregex "SMLAD", "SMLADX", "SMLALD", "SMLALDX", "SMLSD", "SMLSDX",
-      "SMLSLD", "SMLLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
+      "SMLSLD", "SMLSLDX", "SMUAD", "SMUADX", "SMUSD", "SMUSDX")>;
 
 def : InstRW<[A9WriteM16, A9WriteM16Hi],
       (instregex "SMULBB", "SMULBT", "SMULTB", "SMULTT", "SMULWB", "SMULWT")>;
 def : InstRW<[A9WriteM16, A9WriteM16Hi],
       (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLAWB", "SMLAWT")>;
 
 def : InstRW<[A9WriteL], (instregex "LDRi12", "PICLDR$")>;
 def : InstRW<[A9WriteLsi], (instregex "LDRrs")>;

lib/Target/ARM/ARMScheduleR52.td

 //
 def : InstRW<[WriteALU], (instrs COPY)>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS],
       (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
       "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH", "t2UXTB16")>;
 
 def : InstRW<[R52WriteALU_EX1, R52Read_ISS],
-      (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi",
-      "t2MOVi", "t2MOV_ga_dyn")>;
+      (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi", "t2MOVi")>;
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1],
-      (instregex "MOV_ga_pcrel$", "t2MOV_ga_pcrel$")>;
+      (instregex "MOV_ga_pcrel$")>;
 def : InstRW<[R52WriteLd,R52Read_ISS],
-      (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
+      (instregex "MOV_ga_pcrel_ldr")>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "SEL", "t2SEL")>;
 
 def : InstRW< [R52WriteALU_EX2, R52Read_ISS, R52Read_ISS],
       (instregex "BFC", "BFI", "UBFX", "SBFX", "(t|t2)BFC", "(t|t2)BFI",
       "(t|t2)UBFX", "(t|t2)SBFX")>;
 
 // Saturating arithmetic
def : InstRW< [R52WriteALU_EX2, R52Read_EX1, R52Read_EX1],
       "SXTAB", "SXTAB16", "SXTAH", "UHADD8", "UHADD16", "UHSUB8", "UHSUB16",
       "UHASX", "UHSAX", "UXTAB", "UXTAB16", "UXTAH", "t2SHADD8", "t2SHADD16",
       "t2SHSUB8", "t2SHSUB16", "t2SHASX", "t2SHSAX", "t2SXTAB", "t2SXTAB16",
       "t2SXTAH", "t2UHADD8", "t2UHADD16", "t2UHSUB8", "t2UHSUB16", "t2UHASX",
       "t2UHSAX", "t2UXTAB", "t2UXTAB16", "t2UXTAH")>;
 
 // Sum of Absolute Difference
 def : InstRW< [R52WriteALU_WRI, R52Read_ISS, R52Read_ISS, R52Read_ISS],
-      (instregex "USAD8", "t2USAD8", "tUSAD8","USADA8", "t2USADA8", "tUSADA8") >;
+      (instregex "USAD8", "t2USAD8", "USADA8", "t2USADA8") >;
 
 // Integer Multiply
 def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS],
-      (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
-      "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL",
+      (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
+      "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL",
       "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT",
       "t2SMULWB", "t2SMULWT", "t2SMUSD")>;
 
 // Multiply Accumulate
 // Even for 64-bit accumulation (or Long), the single MAC is used (not ALUs).
 // The store pipeline is used partly for 64-bit operations.
 def : InstRW<[R52WriteMAC, R52Read_ISS, R52Read_ISS, R52Read_ISS],
-      (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
-      "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR",
+      (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
+      "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS", "t2SMMLSR",
       "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX",
       "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX",
       "SMLAWB", "SMLAWT", "t2SMLABB", "t2SMLABT", "t2SMLATB", "t2SMLATT",
       "t2SMLSD", "t2SMLSDX", "t2SMLAWB", "t2SMLAWT",
       "SMLAD", "SMLADX", "t2SMLAD", "t2SMLADX",
       "SMULL$", "UMULL$", "t2SMULL$", "t2UMULL$",
-      "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
+      "SMLAL", "UMLAL", "SMLALBT",
       "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
-      "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB",
+      "UMAAL", "t2SMLAL", "t2UMLAL",
       "t2SMLALBT", "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX",
       "t2SMLSLD", "t2SMLSLDX", "t2UMAAL")>;
 
 def : InstRW <[R52WriteDIV, R52Read_ISS, R52Read_ISS],
       (instregex "t2SDIV", "t2UDIV")>;
 
 // Loads (except POST) with SHL > 2, or ror, require 2 extra cycles.
 // However, that's non-trivial to specify, so we keep it uniform
 def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_ISS],
       (instregex "LDR(i12|rs)$", "LDRB(i12|rs)$", "t2LDR(i8|i12|s|pci)",
       "t2LDR(H|B)(i8|i12|s|pci)", "LDREX", "t2LDREX",
       "tLDR[BH](r|i|spi|pci|pciASM)", "tLDR(r|i|spi|pci|pciASM)",
       "LDRH$",  "PICLDR$", "PICLDR(H|B)$", "LDRcp$",
       "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
       "t2LDRpci_pic", "tLDRS(B|H)", "t2LDRDi8", "LDRD$", "LDA", "t2LDA")>;
 def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_ISS],
       (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
       "LDRBT_POST$", "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
       "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T",
       "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
-      "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T",
+      "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?",
       "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "MOVS?sr", "t2MOVS?sr")>;
 def : InstRW<[R52WriteALU_WRI, R52Read_EX2], (instregex "MOVT", "t2MOVT")>;
 
-def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri","ANDS?ri",
+def : InstRW<[R52WriteALU_EX2, R52Read_EX1], (instregex "AD(C|D)S?ri", "ANDS?ri",
       "BICS?ri", "CLZ", "EORri", "MVNS?r", "ORRri", "RSBS?ri", "RSCri", "SBCri",
       "t2AD(C|D)S?ri", "t2ANDS?ri", "t2BICS?ri","t2CLZ", "t2EORri", "t2MVN",
       "t2ORRri", "t2RSBS?ri", "t2SBCri")>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_EX1], (instregex "AD(C|D)S?rr",
-      "ANDS?rr", "BICS?rr", "CRC*", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
+      "ANDS?rr", "BICS?rr", "CRC", "EORrr", "ORRrr", "RSBrr", "RSCrr", "SBCrr",
       "t2AD(C|D)S?rr", "t2ANDS?rr", "t2BICS?rr", "t2CRC", "t2EORrr", "t2SBCrr")>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS], (instregex "AD(C|D)S?rsi",
       "ANDS?rsi", "BICS?rsi", "EORrsi", "ORRrsi", "RSBrsi", "RSCrsi", "SBCrsi",
-      "t2AD(|D)S?rsi", "t2ANDS?rsi", "t2BICS?rsi", "t2EORrsi", "t2ORRrsi", "t2RSBrsi", "t2SBCrsi")>;
+      "t2AD(C|D)S?rs", "t2ANDS?rs", "t2BICS?rs", "t2EORrs", "t2ORRrs", "t2RSBrs", "t2SBCrs")>;
 
 def : InstRW<[R52WriteALU_EX2, R52Read_EX1, R52Read_ISS, R52Read_ISS],
       (instregex "AD(C|D)S?rsr", "ANDS?rsr", "BICS?rsr", "EORrsr", "MVNS?sr",
-      "ORRrsrr", "RSBrsr", "RSCrsr", "SBCrsr")>;
+      "ORRrsr", "RSBrsr", "RSCrsr", "SBCrsr")>;
 
 def : InstRW<[R52WriteALU_EX1],
-    (instregex "ADR", "MOVSi", "MOVSsi", "MOVST?i16*", "MVNS?s?i", "t2MOVS?si")>;
+    (instregex "ADR", "MOVsi", "MVNS?s?i", "t2MOVS?si")>;
 
 def : InstRW<[R52WriteALU_EX1, R52Read_ISS], (instregex "ASRi", "RORS?i")>;
 def : InstRW<[R52WriteALU_EX1, R52Read_ISS, R52Read_ISS],
       (instregex "ASRr", "RORS?r", "LSR", "LSL")>;
 
 def : InstRW<[R52WriteCC, R52Read_EX1], (instregex "CMPri", "CMNri")>;
 def : InstRW<[R52WriteCC, R52Read_EX1, R52Read_EX1], (instregex "CMPrr", "CMNzrr")>;
 def : InstRW<[R52WriteCC, R52Read_EX1, R52Read_ISS], (instregex "CMPrsi", "CMNzrsi")>;

 ]>;
 
 def : InstRW<[R52WriteILDM, R52Read_ISS],
       (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
       "(t|sys)LDM(IA|DA|DB|IB)$")>;
 def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS],
       (instregex "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
 def : InstRW<[R52WriteILDM, R52WriteAdr, R52Read_ISS],
-        (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>;
+        (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>;
 
 // Integer Store, Single Element
 def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2],
       (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX", "SRS", "t2SRS",
       "t2SRSDB", "t2STREX", "t2STREXB", "t2STREXD", "t2STREXH", "t2STR(i12|i8|s)$",
       "RFE", "t2RFE", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
 
 def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2],
       (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
       "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
       "STR(BT|HT|T)", "t2STR_(PRE|POST)", "t2STR[BH]_(PRE|POST)",
       "t2STR_preidx", "t2STR[BH]_preidx", "t2ST(RB|RH|R)T")>;
 
 // Integer Store, Dual
 def : InstRW<[R52WriteLd, R52Read_ISS, R52Read_EX2],
-    (instregex "STRD$", "t2STRDi8", "STL", "t2STRD$", "t2STL")>;
+    (instregex "STRD$", "t2STRDi8", "STL", "t2STL")>;
 def : InstRW<[R52WriteLd, R52WriteAdr, R52Read_ISS, R52Read_EX2],
     (instregex "(t2|t)STRD_(POST|PRE)", "STRD_(POST|PRE)")>;
 
 def : InstRW<[R52WriteISTM, R52Read_ISS, R52Read_EX2],
     (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
 def : InstRW<[R52WriteISTM, R52WriteAdr, R52Read_ISS, R52Read_EX2],
     (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
-    "PUSH", "tPUSH")>;
+    "tPUSH")>;
 
 // LDRLIT pseudo instructions, they expand to LDR + PICADD
 def : InstRW<[R52WriteLd],
       (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel$")>;
 // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
 def : InstRW<[R52WriteLd], (instregex "LDRLIT_ga_pcrel_ldr")>;
 
 

lib/Target/ARM/ARMScheduleSwift.td

let SchedModel = SwiftModel in {
   //  MOVT
   // Sign/Zero extension
   def : InstRW<[SwiftWriteP01OneCycle],
                (instregex "SXTB", "SXTH", "SXTB16", "UXTB", "UXTH", "UXTB16",
                           "t2SXTB", "t2SXTH", "t2SXTB16", "t2UXTB", "t2UXTH",
                           "t2UXTB16")>;
   // Pseudo instructions.
   def : InstRW<[SwiftWriteP01OneCycle2x],
-        (instregex "MOVCCi32imm", "MOVi32imm", "MOV_ga_dyn", "t2MOVCCi32imm",
-                   "t2MOVi32imm", "t2MOV_ga_dyn")>;
+        (instregex "MOVCCi32imm", "MOVi32imm", "t2MOVCCi32imm",
+                   "t2MOVi32imm")>;
   def : InstRW<[SwiftWriteP01OneCycle3x],
         (instregex "MOV_ga_pcrel", "t2MOV_ga_pcrel", "t2MOVi16_ga_pcrel")>;
   def : InstRW<[SwiftWriteP01OneCycle2x_load],
-        (instregex "MOV_ga_pcrel_ldr", "t2MOV_ga_pcrel_ldr")>;
+        (instregex "MOV_ga_pcrel_ldr")>;
 
   def SwiftWriteP0TwoCycleTwoUops : WriteSequence<[SwiftWriteP0OneCycle], 2>;
 
   def SwiftPredP0OneOrTwoCycle : SchedWriteVariant<[
     SchedVar<IsPredicatedPred, [ SwiftWriteP0TwoCycleTwoUops ]>,
     SchedVar<NoSchedPred,     [ SwiftWriteP0OneCycle ]>
   ]>;
 
let SchedModel = SwiftModel in {
   // 4.2.11 Sum of Absolute Difference
   def : InstRW< [SwiftWriteP0P1FourCycle], (instregex "USAD8") >;
   def : InstRW<[SwiftWriteP0P1FourCycle, ReadALU, ReadALU, SchedReadAdvance<2>],
         (instregex "USADA8")>;
 
   // 4.2.12 Integer Multiply (32-bit result)
   // Two sources.
   def : InstRW< [SwiftWriteP0FourCycle],
-        (instregex "MULS", "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
-        "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDXi", "t2MUL",
+        (instregex "MUL", "SMMUL", "SMMULR", "SMULBB", "SMULBT",
+        "SMULTB", "SMULTT", "SMULWB", "SMULWT", "SMUSD", "SMUSDX", "t2MUL",
         "t2SMMUL", "t2SMMULR", "t2SMULBB", "t2SMULBT", "t2SMULTB", "t2SMULTT",
         "t2SMULWB", "t2SMULWT", "t2SMUSD")>;
 
   def SwiftWriteP0P01FiveCycleTwoUops :
       SchedWriteRes<[SwiftUnitP0, SwiftUnitP01]>  {
     let Latency = 5;
   }
 
   def SwiftPredP0P01FourFiveCycle : SchedWriteVariant<[
     SchedVar<IsPredicatedPred, [ SwiftWriteP0P01FiveCycleTwoUops ]>,
     SchedVar<NoSchedPred,      [ SwiftWriteP0FourCycle ]>
   ]>;
 
   def SwiftReadAdvanceFourCyclesPred : SchedReadVariant<[
      SchedVar<IsPredicatedPred, [SchedReadAdvance<4>]>,
      SchedVar<NoSchedPred,      [ReadALU]>
   ]>;
 
   // Multiply accumulate, three sources
   def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
                  SwiftReadAdvanceFourCyclesPred],
-        (instregex "MLAS", "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
-        "t2MLA", "t2MLS", "t2MLAS", "t2SMMLA", "t2SMMLAR", "t2SMMLS",
+        (instregex "MLA", "MLS", "SMMLA", "SMMLAR", "SMMLS", "SMMLSR",
+        "t2MLA", "t2MLS", "t2SMMLA", "t2SMMLAR", "t2SMMLS",
         "t2SMMLSR")>;
 
   // 4.2.13 Integer Multiply (32-bit result, Q flag)
   def : InstRW< [SwiftWriteP0FourCycle],
         (instregex "SMUAD", "SMUADX", "t2SMUAD", "t2SMUADX")>;
   def : InstRW< [SwiftPredP0P01FourFiveCycle, ReadALU, ReadALU,
                  SwiftReadAdvanceFourCyclesPred],
         (instregex "SMLABB", "SMLABT", "SMLATB", "SMLATT", "SMLSD", "SMLSDX",
let SchedModel = SwiftModel in {
   def : SchedAlias<ReadMAC, SwiftReadAdvanceFourCyclesPred>;
 
   // 4.2.15 Integer Multiply Accumulate, Long
   // 4.2.16 Integer Multiply Accumulate, Dual
   // 4.2.17 Integer Multiply Accumulate Accumulate, Long
   // We are being a bit inaccurate here.
   def : InstRW< [SwiftWrite5Cycle, Swift2P03P01FiveCycle, ReadALU, ReadALU,
                  SchedReadAdvance<4>, SchedReadAdvance<3>],
-        (instregex "SMLALS", "UMLALS", "SMLAL", "UMLAL", "MLALBB", "SMLALBT",
+        (instregex "SMLAL", "UMLAL", "SMLALBT",
         "SMLALTB", "SMLALTT", "SMLALD", "SMLALDX", "SMLSLD", "SMLSLDX",
-        "UMAAL", "t2SMLALS", "t2UMLALS", "t2SMLAL", "t2UMLAL", "t2MLALBB", "t2SMLALBT",
+        "UMAAL", "t2SMLAL", "t2UMLAL", "t2SMLALBB", "t2SMLALBT",
         "t2SMLALTB", "t2SMLALTT", "t2SMLALD", "t2SMLALDX", "t2SMLSLD", "t2SMLSLDX",
         "t2UMAAL")>;
 
   def SwiftDiv : SchedWriteRes<[SwiftUnitP0, SwiftUnitDiv]> {
     let NumMicroOps = 1;
     let Latency = 14;
     let ResourceCycles = [1, 14];
   }
def : InstRW<[SwiftWriteP2P01FourCycle],
         (instregex "PICLDRS(H|B)$", "t2LDRS(H|B)(i|r|p|s)", "LDRS(H|B)$",
         "t2LDRpci_pic", "tLDRS(B|H)")>;
   def : InstRW<[SwiftWriteP2P01ThreeCycle,  SwiftWrBackOne],
         (instregex "LD(RB|R)(_|T_)(POST|PRE)_(IMM|REG)", "LDRH(_PRE|_POST)",
         "LDR(T|BT)_POST_(REG|IMM)", "LDRHT(i|r)",
         "t2LD(R|RB|RH)_(PRE|POST)", "t2LD(R|RB|RH)T")>;
   def : InstRW<[SwiftWriteP2P01P01FourCycle, SwiftWrBackOne],
         (instregex "LDR(SH|SB)(_POST|_PRE)", "t2LDR(SH|SB)(_POST|_PRE)",
-        "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)", "t2LDRS(B|H)T")>;
+        "LDRS(B|H)T(i|r)", "t2LDRS(B|H)T(i|r)?")>;
 
   // 4.2.21 Integer Dual Load
   // Not accurate.
   def : InstRW<[SwiftWriteP2P2ThreeCycle, SwiftWriteLdFour],
         (instregex "t2LDRDi8", "LDRD$")>;
   def : InstRW<[SwiftWriteP2P2P01ThreeCycle, SwiftWriteLdFour, SwiftWrBackOne],
         (instregex "LDRD_(POST|PRE)", "t2LDRD_(POST|PRE)")>;
 
let SchedModel = SwiftModel in {
 
   def : InstRW<[SwiftWriteLM, SwiftWriteLDMAddrNoWB],
         (instregex "LDM(IA|DA|DB|IB)$", "t2LDM(IA|DA|DB|IB)$",
         "(t|sys)LDM(IA|DA|DB|IB)$")>;
   def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM],
         (instregex /*"t2LDMIA_RET", "tLDMIA_RET", "LDMIA_RET",*/
         "LDM(IA|DA|DB|IB)_UPD", "(t2|sys|t)LDM(IA|DA|DB|IB)_UPD")>;
   def : InstRW<[SwiftWriteLDMAddrWB, SwiftWriteLM, SwiftWriteP1TwoCycle],
-        (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "POP", "tPOP")>;
+        (instregex "LDMIA_RET", "(t|t2)LDMIA_RET", "tPOP")>;
   // 4.2.23 Integer Store, Single Element
   def : InstRW<[SwiftWriteP2],
         (instregex "PICSTR", "STR(i12|rs)", "STRB(i12|rs)", "STRH$", "STREX",
         "t2STR(i12|i8|s)$", "t2STR[BH](i12|i8|s)$", "tSTR[BH](i|r)", "tSTR(i|r)", "tSTRspi")>;
 
   def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteP2],
         (instregex "STR(B_|_|BT_|T_)(PRE_IMM|PRE_REG|POST_REG|POST_IMM)",
         "STR(i|r)_preidx", "STRB(i|r)_preidx", "STRH_preidx", "STR(H_|HT_)(PRE|POST)",
def SwiftWriteSTM : SchedWriteVariant<[
     SchedVar<SwiftLMAddr16Pred,[SwiftWriteSTM16]>,
     // Unknow number of registers, just use resources for two registers.
     SchedVar<NoSchedPred,      [SwiftWriteSTM2]>
   ]>;
   def : InstRW<[SwiftWriteSTM],
         (instregex "STM(IB|IA|DB|DA)$", "(t2|sys|t)STM(IB|IA|DB|DA)$")>;
   def : InstRW<[SwiftWriteP01OneCycle, SwiftWriteSTM],
         (instregex "STM(IB|IA|DB|DA)_UPD", "(t2|sys|t)STM(IB|IA|DB|DA)_UPD",
-        "PUSH", "tPUSH")>;
+        "tPUSH")>;
 
   // LDRLIT pseudo instructions, they expand to LDR + PICADD
   def : InstRW<[SwiftWriteP2ThreeCycle, WriteALU],
         (instregex "t?LDRLIT_ga_abs", "t?LDRLIT_ga_pcrel")>;
   // LDRLIT_ga_pcrel_ldr expands to LDR + PICLDR
   def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2ThreeCycle],
         (instregex "LDRLIT_ga_pcrel_ldr")>;
 
   // 4.2.26 Branch
   def : WriteRes<WriteBr, [SwiftUnitP1]> { let Latency = 0; }
   def : WriteRes<WriteBrL, [SwiftUnitP1]> { let Latency = 2; }
   def : WriteRes<WriteBrTbl, [SwiftUnitP1, SwiftUnitP2]> { let Latency = 0; }
 
   // 4.2.27 Not issued
   def : WriteRes<WriteNoop, []> { let Latency = 0; let NumMicroOps = 0; }
-  def : InstRW<[WriteNoop], (instregex "t2IT", "IT", "NOP")>;
+  def : InstRW<[WriteNoop], (instregex "t2IT", "IT")>;
 
   // 4.2.28 Advanced SIMD, Integer, 2 cycle
   def : InstRW<[SwiftWriteP0TwoCycle],
         (instregex "VADDv", "VSUBv", "VNEG(s|f|v)", "VADDL", "VSUBL",
                    "VADDW", "VSUBW", "VHADD", "VHSUB", "VRHADD", "VPADDi",
                    "VPADDL", "VAND", "VBIC", "VEOR", "VORN", "VORR", "VTST",
-                   "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL", "VQSHLU", "VBIF",
+                   "VSHL", "VSHR(s|u)", "VSHLL", "VQSHL(s|u)", "VBIF",
                    "VBIT", "VBSL", "VSLI", "VSRI", "VCLS", "VCLZ", "VCNT")>;
 
   def : InstRW<[SwiftWriteP1TwoCycle],
         (instregex "VEXT", "VREV16", "VREV32", "VREV64")>;
 
   // 4.2.29 Advanced SIMD, Integer, 4 cycle
   // 4.2.30 Advanced SIMD, Integer with Accumulate
   def : InstRW<[SwiftWriteP0FourCycle],
         (instregex "VABA", "VABAL", "VPADAL", "VRSRA", "VSRA", "VACGE", "VACGT",
-        "VACLE", "VACLT", "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
+        "VCEQ", "VCGE", "VCGT", "VCLE", "VCLT", "VRSHL",
         "VQRSHL", "VRSHR(u|s)", "VABS(f|v)", "VQABS", "VQNEG", "VQADD",
         "VQSUB")>;
   def : InstRW<[SwiftWriteP1FourCycle],
         (instregex "VRECPE", "VRSQRTE")>;
 
   // 4.2.31 Advanced SIMD, Add and Shift with Narrow
   def : InstRW<[SwiftWriteP0P1FourCycle],
         (instregex "VADDHN", "VSUBHN", "VSHRN")>;
let SchedModel = SwiftModel in {
   def : InstRW<[SwiftWriteP1TwelveCyc], (instregex "VFMAfq", "VFMSfq")>;
 
   // 4.2.36 Advanced SIMD and VFP, Convert
   def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
 
   // 4.2.37 Advanced SIMD and VFP, Move
   def : InstRW<[SwiftWriteP0TwoCycle],
         (instregex "VMOVv", "VMOV(S|D)$", "VMOV(S|D)cc",
-                   "VMVNv", "VMVN(d|q)", "VMVN(S|D)cc",
+                   "VMVNv", "VMVN(d|q)",
                    "FCONST(D|S)")>;
   def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VMOVN", "VMOVL")>;
   def : InstRW<[WriteSequence<[SwiftWriteP0FourCycle, SwiftWriteP1TwoCycle]>],
         (instregex "VQMOVN")>;
-  def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN", "VDUPf")>;
+  def : InstRW<[SwiftWriteP1TwoCycle], (instregex "VDUPLN")>;
   def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP1TwoCycle]>],
         (instregex "VDUP(8|16|32)")>;
   def : InstRW<[SwiftWriteP2ThreeCycle], (instregex "VMOVRS$")>;
   def : InstRW<[WriteSequence<[SwiftWriteP2FourCycle, SwiftWriteP0TwoCycle]>],
         (instregex "VMOVSR$", "VSETLN")>;
   def : InstRW<[SwiftWriteP2ThreeCycle, SwiftWriteP2FourCycle],
         (instregex "VMOVRR(D|S)$")>;
   def : InstRW<[SwiftWriteP2FourCycle], (instregex "VMOVDRR$")>;

utils/TableGen/CodeGenSchedule.cpp

for (Init *Arg : make_range(Expr->arg_begin(), Expr->arg_end())) {
       if (!pat.empty()) {
         // For the rest use a python-style prefix match.
         if (pat[0] != '^') {
           pat.insert(0, "^(");
           pat.insert(pat.end(), ')');
         }
         Regexpr = Regex(pat);
       }
 
+      int NumMatches = 0;
+
       unsigned NumGeneric = Target.getNumFixedInstructions();
       ArrayRef<const CodeGenInstruction *> Generics =
           Target.getInstructionsByEnumValue().slice(0, NumGeneric + 1);
 
       // The generic opcodes are unsorted, handle them manually.
       for (auto *Inst : Generics) {
         StringRef InstName = Inst->TheDef->getName();
         if (InstName.startswith(Prefix) &&
-            (!Regexpr || Regexpr->match(InstName.substr(Prefix.size()))))
+            (!Regexpr || Regexpr->match(InstName.substr(Prefix.size())))) {
           Elts.insert(Inst->TheDef);
+          NumMatches++;
+        }
       }
 
       ArrayRef<const CodeGenInstruction *> Instructions =
           Target.getInstructionsByEnumValue().slice(NumGeneric + 1);
 
       // Target instructions are sorted. Find the range that starts with our
       // prefix.
       struct Comp {
         bool operator()(const CodeGenInstruction *LHS, StringRef RHS) {
           return LHS->TheDef->getName() < RHS;
         }
         bool operator()(StringRef LHS, const CodeGenInstruction *RHS) {
           return LHS < RHS->TheDef->getName() &&
                  !RHS->TheDef->getName().startswith(LHS);
         }
       };
       auto Range = std::equal_range(Instructions.begin(), Instructions.end(),
                                     Prefix, Comp());
 
       // For this range we know that it starts with the prefix. Check if there's
       // a regex that needs to be checked.
       for (auto *Inst : make_range(Range)) {
         StringRef InstName = Inst->TheDef->getName();
-        if (!Regexpr || Regexpr->match(InstName.substr(Prefix.size())))
+        if (!Regexpr || Regexpr->match(InstName.substr(Prefix.size()))) {
           Elts.insert(Inst->TheDef);
+          NumMatches++;
         }
       }
+
+      if (0 == NumMatches)
+        PrintFatalError(Loc, "instregex has no matches: " + Original);
+    }
   }
 };
 
 } // end anonymous namespace
 
 /// CodeGenModels ctor interprets machine model records and populates maps.
 CodeGenSchedModels::CodeGenSchedModels(RecordKeeper &RK,
                                        const CodeGenTarget &TGT):