[GlobalISel][ARM] Adding HPR and QPR regclasses to FPRB regbank

[rtereshin]

Summary

Also bringing ARMRegisterBankInfo::getRegBankFromRegClass implementation up to speed with the *.td-definition.

This is a strict requirement for D44700: Improving InstructionSelect's performance by reducing MatchTable that brings a significant compile time reduction to GlobalISel.

The reason for the dependency is simple: the MatchTable optimization sometimes re-orders some of the rules if it's safe, for instance, if 2 rules are mutually exclusive because they explicitly check different register banks of the same operands of the same instruction sequences (by topology). If let's say the original table has 4 rules in order A1 B1 A2 B2, where A1 and A2 check the same register bank A (therefore not safe to re-order), and B1 and B2 check the same bank B, where A != B it's safe to reorder them as A1 A2 B1 B2 and it's beneficial as the register banks check could be extracted out and checked once for a group (check A (A1' A2') check B (B1' B2'). It could be noticed also that check B (B1' B2') check A (A1' A2') is equally legal. As a portion of a concrete MatchTable is unreachable due to GlobalISel falling back to SelectionDAG ISel on earlier stages (Legalization, Reg Bank Selection, etc) and / or due to selectiveness of the Reg Bank Select some of the register bank checks there were never covered before by the existing tests now will (for instance if A1 hid B1 A2 B2 part of the table, check B could have avoided execution altogether, while in modified check B (B1' B2') check A (A1' A2') table check B could be executed).

And some of those checks fail because they try to look up a register bank for a register class that is not handled by the implementation.

This patch fixes exactly that for ARM.

[rtereshin]

Removing Testgen'erated tests as I'm eliminating the dependency of https://reviews.llvm.org/D44700 (InstructionSelect perf patch) from https://reviews.llvm.org/D43962 (Testgen) and pushing the perf patch sooner and the perf patch depends on this one.

If the perf patch applied in front of this one a number of regression tests will fail therefore this will be immediately tested by the existing tests.

llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp

assert((RegBank->getID() == ARM::GPRRegBankID ||
           RegBank->getID() == ARM::FPRRegBankID) &&
          "Unsupported reg bank");
 
   if (RegBank->getID() == ARM::FPRRegBankID) {
     if (Size == 32)
       return &ARM::SPRRegClass;
     else if (Size == 64)
       return &ARM::DPRRegClass;
+    else if (Size == 128)
+      return &ARM::QPRRegClass;
     else
       llvm_unreachable("Unsupported destination size");
   }
 
   return &ARM::GPRRegClass;
 }
 
 static bool selectCopy(MachineInstr &I, const TargetInstrInfo &TII,

llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp

 }
 
 const RegisterBank &ARMRegisterBankInfo::getRegBankFromRegClass(
     const TargetRegisterClass &RC) const {
   using namespace ARM;
 
   switch (RC.getID()) {
   case GPRRegClassID:
+  case GPRwithAPSRRegClassID:
   case GPRnopcRegClassID:
+  case rGPRRegClassID:
   case GPRspRegClassID:
   case tGPR_and_tcGPRRegClassID:
+  case tcGPRRegClassID:
   case tGPRRegClassID:
     return getRegBank(ARM::GPRRegBankID);
+  case HPRRegClassID:
   case SPR_8RegClassID:
   case SPRRegClassID:
   case DPR_8RegClassID:
   case DPRRegClassID:
+  case QPRRegClassID:
     return getRegBank(ARM::FPRRegBankID);
   default:
     llvm_unreachable("Unsupported register kind");
   }
 
   llvm_unreachable("Switch should handle all register classes");
 }
 

llvm/trunk/lib/Target/ARM/ARMRegisterBanks.td

 //=- ARMRegisterBank.td - Describe the AArch64 Banks ---------*- tablegen -*-=//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //
 //===----------------------------------------------------------------------===//
 
 def GPRRegBank : RegisterBank<"GPRB", [GPR, GPRwithAPSR]>;
-def FPRRegBank : RegisterBank<"FPRB", [SPR, DPR]>;
+def FPRRegBank : RegisterBank<"FPRB", [HPR, SPR, DPR, QPR]>;