This is an archive of the discontinued LLVM Phabricator instance.

The change for LoadPostIdx looks good, I am not entirely sure about StorePostIdx. Could you elaborate why we should remove ReadAdrBase there? Maybe @javed.absar has some thoughts too.

@fhahn, ReadAddrBase is used only for the register offset addressing mode and doesn't apply to either the pre or post indexed addressing modes. This patch makes these classes similar to classes LoadPairPostIdx and StorePairPostIdx.

Ping 🔔

evandro added a subscriber: apinski-cavium.Dec 6 2017, 1:48 PM

¡Ping! 🔔🔔

Ping!!! 🔔🔔🔔

¡¡Ping!! 🔔🔔🔔🔔

Ping! 🔔🔔🔔🔔🔔

LGTM.

I don't expect you have a test case that exposed the problem, right?
(In particular for Cyclone at least WriteAdr is the same as WriteI).

This revision is now accepted and ready to land.Jan 12 2018, 9:46 AM

In D40511#974794, @qcolombet wrote:

I don't expect you have a test case that exposed the problem, right?
(In particular for Cyclone at least WriteAdr is the same as WriteI).

I noticed this issue when working in D39976, where otherwise test cases fail without this change.

Thank you.

Closed by commit rL322392: [AArch64] Fix scheduling resources for post indexed loads and stores (authored by evandro). · Explain WhyJan 12 2018, 11:21 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

lib/

Target/

AArch64/

AArch64InstrFormats.td

4 lines

Diff 124433

llvm/lib/Target/AArch64/AArch64InstrFormats.td

This file is larger than 256 KB, so syntax highlighting is disabled by default.

	Show First 20 Lines • Show All 3,186 Lines • ▼ Show 20 Lines
	let hasSideEffects = 0 in {			let hasSideEffects = 0 in {
	let mayStore = 0, mayLoad = 1 in			let mayStore = 0, mayLoad = 1 in
	class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,			class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
	string asm>			string asm>
	: BaseLoadStorePostIdx<sz, V, opc,			: BaseLoadStorePostIdx<sz, V, opc,
	(outs GPR64sp:$wback, regtype:$Rt),			(outs GPR64sp:$wback, regtype:$Rt),
	(ins GPR64sp:$Rn, simm9:$offset),			(ins GPR64sp:$Rn, simm9:$offset),
	asm, "$Rn = $wback,@earlyclobber $wback", []>,			asm, "$Rn = $wback,@earlyclobber $wback", []>,
	Sched<[WriteLD, WriteI]>;			Sched<[WriteLD, WriteAdr]>;

	let mayStore = 1, mayLoad = 0 in			let mayStore = 1, mayLoad = 0 in
	class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,			class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
	string asm, SDPatternOperator storeop, ValueType Ty>			string asm, SDPatternOperator storeop, ValueType Ty>
	: BaseLoadStorePostIdx<sz, V, opc,			: BaseLoadStorePostIdx<sz, V, opc,
	(outs GPR64sp:$wback),			(outs GPR64sp:$wback),
	(ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),			(ins regtype:$Rt, GPR64sp:$Rn, simm9:$offset),
	asm, "$Rn = $wback,@earlyclobber $wback",			asm, "$Rn = $wback,@earlyclobber $wback",
	[(set GPR64sp:$wback,			[(set GPR64sp:$wback,
	(storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,			(storeop (Ty regtype:$Rt), GPR64sp:$Rn, simm9:$offset))]>,
	Sched<[WriteAdr, WriteST, ReadAdrBase]>;			Sched<[WriteAdr, WriteST]>;
	} // hasSideEffects = 0			} // hasSideEffects = 0


	//---			//---
	// Load/store pair			// Load/store pair
	//---			//---

	// (indexed, offset)			// (indexed, offset)
	▲ Show 20 Lines • Show All 6,319 Lines • Show Last 20 Lines

This is an archive of the discontinued LLVM Phabricator instance.

[AArch64] Fix scheduling resources for post indexed loads and storesClosedPublic

Details

Diff Detail

Event Timeline

Revision Contents

Diff 124433

llvm/lib/Target/AArch64/AArch64InstrFormats.td

[AArch64] Fix scheduling resources for post indexed loads and stores
ClosedPublic