[AArch64] Fix scheduling resources for post indexed loads and stores
ClosedPublic

Authored by evandro on Nov 27 2017, 11:54 AM.

Details

Summary

Fix typos in the default scheduling resources when using the post indexed addressing modes.

Diff Detail

Repository
rL LLVM
evandro created this revision.Nov 27 2017, 11:54 AM
fhahn added a comment.Nov 28 2017, 2:23 PM

The change for LoadPostIdx looks good, I am not entirely sure about StorePostIdx. Could you elaborate why we should remove ReadAdrBase there? Maybe @javed.absar has some thoughts too.

@fhahn, ReadAddrBase is used only for the register offset addressing mode and doesn't apply to either the pre or post indexed addressing modes. This patch makes these classes similar to classes LoadPairPostIdx and StorePairPostIdx.

Ping πŸ””

Β‘Ping! πŸ””πŸ””

Ping!!! πŸ””πŸ””πŸ””

‘‘Ping!! πŸ””πŸ””πŸ””πŸ””

Ping! πŸ””πŸ””πŸ””πŸ””πŸ””

qcolombet accepted this revision.Jan 12 2018, 9:46 AM

LGTM.

I don't expect you have a test case that exposed the problem, right?
(In particular for Cyclone at least WriteAdr is the same as WriteI).

This revision is now accepted and ready to land.Jan 12 2018, 9:46 AM

I don't expect you have a test case that exposed the problem, right?
(In particular for Cyclone at least WriteAdr is the same as WriteI).

I noticed this issue when working in D39976, where otherwise test cases fail without this change.

Thank you.

This revision was automatically updated to reflect the committed changes.