This adds support for the Signal Processing Engine, a non-standard FPU
and vector unit on some PowerPC cores (Freescale e500, maybe others).
- asm parsing and printing for almost all instructions
- Code generation following the SPE ABI at the llvm IR level (function call)
- Single- and Double-precision math at the level supported by the APU, including conversion between precisions and with integers
- Support for some vector operations (float math, some integer math)
Currently not fully compliant with the SPEPIM; anything that takes a
__ev64_opaque argument in intrinsics instead takes a v2i32.
Along with this, add the Freescale e500 scheduler, which is slightly
different from the e500mc scheduler.