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Dec 10 2017, 12:26 PM (93 w, 6 h)

Recent Activity

Feb 24 2018 added a comment to D43005: [ARM] Error out on .arm assembler directives on windows.

I can verify that if execution enters the kernel via trap or otherwise from a program in ARM mode on WinRT or Winphone 8.1 using the default MSVC compilers no ARM->Thumb2 switch occurs and the kernel's Thumb2 code executes in ARM mode, usually causing the system to black screen or hard lock with no dump / bugcheck. The kernel doesn't make any attempt to change the mode on entry or exit. It's been years since I did the research on that but I suspect it hasn't changed extensively and in any event makes the earlier devices flat out disastrous to execute ARM code on from a system perspective; It really doesn't support the mode.

Feb 24 2018, 3:32 PM added a comment to D38778: Implement rudimentary support for the PowerPC SPE APU.

I have a couple of questions (along with a nitpicky inline comment).

Feb 24 2018, 2:46 PM

Feb 23 2018 accepted rL325924: [InstCombine] refactor fmul with negated op folds; NFCI.

I'm not seeing any problems with this.

Feb 23 2018, 12:04 PM

Feb 12 2018 added a comment to rL324864: [X86] Remove check for X86ISD::AND with no flag users from the TEST instruction….

Looks like a short-circuit gone wrong to me, but it got me wondering if there's a usage of ISD::AND that doesn't cover X86ISD::AND entirely. May have just been an artifact. The getResNo() == 0 I'm not familiar with. I can look into it if someone else doesn't get eyes on it first.

Feb 12 2018, 2:10 AM

Feb 11 2018 accepted rL324865: [X86] Don't look for TEST instruction shrinking opportunities when the root….

It appears that sub reg, 0 clears the flags it normally modifies, but that's not really the situation being tested for and is already modeled. There might be weird code floating around that relies on that for some reason, but I kind of doubt it.

Feb 11 2018, 8:53 PM