encode YAML scalars using double quotes so all values can be expressed

[inglorion]

Summary

Previously, our YAML encoder used single quotes to encode scalars that
cannot be expressed as plain scalars. Single-quoted scalars can encode
some values that plain scalars cannot, but fall short of being able to
encode all scalars. This change makes the YAML encoder use
double-quoted scalars instead, which can encode all character values.

[inglorion]

The vast majority of changes here are updating tests to expect double quotes instead of single quotes. The actual change to the encoder is in llvm/lib/Support/YAMLTraits.cpp.

Alternative considered: Use single quotes when sufficient, and double quotes only if necessary. This would complicate the encoder somewhat, because there is an additional decision that needs to be made, and possibly some work to be re-done (e.g. if a double quote has already been included in the string). On the plus side, it would not require all the tests to be updated. In the end, I decided that I prefer to have a single quoting style used in every case, rather than using a not fully expressive quoting style in the common case and a different quoting style in rarer cases. The test changes only have to be made once, and are mostly mechanical.

[zturner]

I know you're working on this because of some issues with a certain PDB symbol. Any chance you could send me the PDB that is triggering the problem?

[zturner]

llvm/lib/Support/YAMLTraits.cpp

624

Is there any reason not to use isprint here (the semantics of isprint are slightly different than your if-case, btw)

625–628

You could use Encoded += "\\x" + toHex(StringRef(&C, 1)); here.

630

It looks like the previous code did not escape backslashes. Was this a bug in the previous code? If so we should add a test for it.

[inglorion]

llvm/lib/Support/YAMLTraits.cpp

624

Not really. I just don't know off the top of my head if isprint checks the same thing as YAML's "printable character". For characters with code points >=0 and <= 127, it seems like it does. Since I'm not handling Unicode here, I could presumably replace the check here with isprint. Would you like me to do that?

625–628

Will do.

630

The old code didn't escape backslashes, which is actually correct - single quotes in YAML don't support any escape sequences, with the exception of two single quotes to encode a single single quote. Backslashes are used in some of the tests, so we know they are handled correctly both before and after this change, but I'll add an explicit test in YAMLIOTest (where I've already added tests for control characters and characters we expect to appear literally).

[inglorion]

Implemented @zturner's suggestions

[inglorion]

zturner: Do you have some time to look at this (D33961) and D34013?

[zturner]

This looks ok to me, but +joerg since there was another patch recently related to quoting and escaping of yaml, and he had some thoughts there. So just want to make sure this doesn't run contrary to any of the ideas he expressed in the other revision.

[inglorion]

@joerg, any comments?

[inglorion]

I think r320996 implements this.

clang-tools-extra/test/clang-tidy/fix.cpp

 // RUN: grep -Ev "// *[A-Z-]+:" %s > %t.cpp
 // RUN: clang-tidy %t.cpp -checks='-*,google-explicit-constructor,llvm-namespace-comment' -fix -export-fixes=%t.yaml -- > %t.msg 2>&1
 // RUN: FileCheck -input-file=%t.cpp %s
 // RUN: FileCheck -input-file=%t.msg -check-prefix=CHECK-MESSAGES %s
 // RUN: FileCheck -input-file=%t.yaml -check-prefix=CHECK-YAML %s
 
 namespace i {
 void f(); // So that the namespace isn't empty.
 }
 // CHECK: } // namespace i
 // CHECK-MESSAGES: note: FIX-IT applied suggested code changes
-// CHECK-YAML: ReplacementText: ' // namespace i'
+// CHECK-YAML: ReplacementText: " // namespace i"
 
 class A { A(int i); };
 // CHECK: class A { explicit A(int i); };
 // CHECK-MESSAGES: note: FIX-IT applied suggested code changes
 // CHECK-MESSAGES: clang-tidy applied 2 of 2 suggested fixes.
-// CHECK-YAML: ReplacementText: 'explicit '
+// CHECK-YAML: ReplacementText: "explicit "

clang-tools-extra/test/clang-tidy/google-module.cpp

 // RUN: clang-tidy -checks='-*,google*' -config='{}' -dump-config - -- | FileCheck %s
 // CHECK: CheckOptions:
 // CHECK: {{- key: *google-readability-braces-around-statements.ShortStatementLines}}
-// CHECK-NEXT: {{value: *'1'}}
+// CHECK-NEXT: {{value: *"1"}}
 // CHECK: {{- key: *google-readability-function-size.StatementThreshold}}
-// CHECK-NEXT: {{value: *'800'}}
+// CHECK-NEXT: {{value: *"800"}}
 // CHECK: {{- key: *google-readability-namespace-comments.ShortNamespaceLines}}
-// CHECK-NEXT: {{value: *'10'}}
+// CHECK-NEXT: {{value: *"10"}}
 // CHECK: {{- key: *google-readability-namespace-comments.SpacesBeforeComments}}
-// CHECK-NEXT: {{value: *'2'}}
+// CHECK-NEXT: {{value: *"2"}}

clang/unittests/Tooling/RefactoringTest.cpp

Err = Change.insert(Context.Sources, DefaultLoc.getLocWithOffset(10), "bb",
                     /*InsertAfter=*/false);
   ASSERT_TRUE(!Err);
   Change.addHeader("a.h");
   Change.removeHeader("b.h");
   std::string YAMLString = Change.toYAMLString();
 
   // NOTE: If this test starts to fail for no obvious reason, check whitespace.
   ASSERT_STREQ("---\n"
-               "Key:             'input.cpp:20'\n"
+               "Key:             \"input.cpp:20\"\n"
                "FilePath:        input.cpp\n"
-               "Error:           ''\n"
+               "Error:           \"\"\n"
                "InsertedHeaders: [ a.h ]\n"
                "RemovedHeaders:  [ b.h ]\n"
                "Replacements:    \n" // Extra whitespace here!
                "  - FilePath:        input.cpp\n"
                "    Offset:          20\n"
                "    Length:          0\n"
                "    ReplacementText: aa\n"
                "  - FilePath:        input.cpp\n"
                "    Offset:          30\n"
                "    Length:          0\n"
                "    ReplacementText: bb\n"
                "...\n",
                YAMLString.c_str());
 }
 
 TEST_F(AtomicChangeTest, YAMLToAtomicChange) {
   std::string YamlContent = "---\n"
-                            "Key:             'input.cpp:20'\n"
+                            "Key:             \"input.cpp:20\"\n"
                             "FilePath:        input.cpp\n"
-                            "Error:           'ok'\n"
+                            "Error:           \"ok\"\n"
                             "InsertedHeaders: [ a.h ]\n"
                             "RemovedHeaders:  [ b.h ]\n"
                             "Replacements:    \n" // Extra whitespace here!
                             "  - FilePath:        input.cpp\n"
                             "    Offset:          20\n"
                             "    Length:          0\n"
                             "    ReplacementText: aa\n"
                             "  - FilePath:        input.cpp\n"

clang/unittests/Tooling/ReplacementsYamlTest.cpp

TEST(ReplacementsYamlTest, serializesReplacements) {
 
   // NOTE: If this test starts to fail for no obvious reason, check whitespace.
   ASSERT_STREQ("---\n"
                "MainSourceFile:  /path/to/source.cpp\n"
                "Replacements:    \n" // Extra whitespace here!
                "  - FilePath:        /path/to/file1.h\n"
                "    Offset:          232\n"
                "    Length:          56\n"
-               "    ReplacementText: 'replacement #1'\n"
+               "    ReplacementText: \"replacement #1\"\n"
                "  - FilePath:        /path/to/file2.h\n"
                "    Offset:          301\n"
                "    Length:          2\n"
-               "    ReplacementText: 'replacement #2'\n"
+               "    ReplacementText: \"replacement #2\"\n"
                "...\n",
                YamlContentStream.str().c_str());
 }
 
 TEST(ReplacementsYamlTest, deserializesReplacements) {
   std::string YamlContent = "---\n"
                             "MainSourceFile:      /path/to/source.cpp\n"
                             "Replacements:\n"
                             "  - FilePath:        /path/to/file1.h\n"
                             "    Offset:          232\n"
                             "    Length:          56\n"
-                            "    ReplacementText: 'replacement #1'\n"
+                            "    ReplacementText: \"replacement #1\"\n"
                             "  - FilePath:        /path/to/file2.h\n"
                             "    Offset:          301\n"
                             "    Length:          2\n"
-                            "    ReplacementText: 'replacement #2'\n"
+                            "    ReplacementText: \"replacement #2\"\n"
                             "...\n";
   TranslationUnitReplacements DocActual;
   yaml::Input YAML(YamlContent);
   YAML >> DocActual;
   ASSERT_FALSE(YAML.error());
   ASSERT_EQ(2u, DocActual.Replacements.size());
   ASSERT_EQ("/path/to/source.cpp", DocActual.MainSourceFile);
   ASSERT_EQ("/path/to/file1.h", DocActual.Replacements[0].getFilePath());

lld/test/COFF/pdb-none.test

 # RUN: yaml2obj < %p/Inputs/pdb1.yaml > %t1.obj
 # RUN: yaml2obj < %p/Inputs/pdb2.yaml > %t2.obj
 # RUN: lld-link /debug /debugtype:pdata /pdb:%t.pdb /dll /out:%t.dll /entry:main /nodefaultlib \
 # RUN:   %t1.obj %t2.obj
 
 # RUN: llvm-pdbutil pdb2yaml -pdb-stream %t.pdb | FileCheck %s
 
 # CHECK:      PdbStream:
 # CHECK-NEXT:   Age:             0
-# CHECK-NEXT:   Guid:            '{00000000-0000-0000-0000-000000000000}'
+# CHECK-NEXT:   Guid:            "{00000000-0000-0000-0000-000000000000}"
 # CHECK-NEXT:   Signature:       0
 # CHECK-NEXT:   Version:         VC70
 

lld/test/COFF/pdb.test

 # CHECK-NEXT:     - Kind:            LF_FUNC_ID
 # CHECK-NEXT:       FuncId:
 # CHECK-NEXT:         ParentScope:     0
 # CHECK-NEXT:         FunctionType:    4097
 # CHECK-NEXT:         Name:            foo
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
-# CHECK-NEXT:         String:          'D:\b'
+# CHECK-NEXT:         String:          "D:\\b"
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
-# CHECK-NEXT:         String:          'C:\vs14\VC\BIN\amd64\cl.exe'
+# CHECK-NEXT:         String:          "C:\\vs14\\VC\\BIN\\amd64\\cl.exe"
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
-# CHECK-NEXT:         String:          '-Z7 -c -MT -IC:\vs14\VC\INCLUDE -IC:\vs14\VC\ATLMFC\INCLUDE -I"C:\Program Files (x86)\Windows Kits\10\include\10.0.10150.0\ucrt" -I"C:\Program Files (x86)\Windows Kits\NETFXSDK\4.6\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\shared"'
+# CHECK-NEXT:         String:          "-Z7 -c -MT -IC:\\vs14\\VC\\INCLUDE -IC:\\vs14\\VC\\ATLMFC\\INCLUDE -I\"C:\\Program Files (x86)\\Windows Kits\\10\\include\\10.0.10150.0\\ucrt\" -I\"C:\\Program Files (x86)\\Windows Kits\\NETFXSDK\\4.6\\include\\um\" -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\shared\""
 # CHECK-NEXT:     - Kind:            LF_SUBSTR_LIST
 # CHECK-NEXT:       StringList:
 # CHECK-NEXT:         StringIndices:   [ 4100 ]
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              4101
-# CHECK-NEXT:         String:          ' -I"C:\Program Files (x86)\Windows Kits\8.1\include\um" -I"C:\Program Files (x86)\Windows Kits\8.1\include\winrt" -TC -X'
+# CHECK-NEXT:         String:          " -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\um\" -I\"C:\\Program Files (x86)\\Windows Kits\\8.1\\include\\winrt\" -TC -X"
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
 # CHECK-NEXT:         String:          ret42-main.c
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
-# CHECK-NEXT:         String:          'D:\b\vc140.pdb'
+# CHECK-NEXT:         String:          "D:\\b\\vc140.pdb"
 # CHECK-NEXT:     - Kind:            LF_BUILDINFO
 # CHECK-NEXT:       BuildInfo:
 # CHECK-NEXT:         ArgIndices:      [ 4098, 4099, 4103, 4104, 4102 ]
 # CHECK-NEXT:     - Kind:            LF_STRING_ID
 # CHECK-NEXT:       StringId:
 # CHECK-NEXT:         Id:              0
 # CHECK-NEXT:         String:          ret42-sub.c
 # CHECK-NEXT:     - Kind:            LF_BUILDINFO

lld/test/ELF/lto/opt-remarks.ll

 ; CHECK-NEXT: }
 
 ; YAML: --- !Analysis
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            CanBeInlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          tinkywinky
-; YAML-NEXT:   - String:          ' can be inlined into '
+; YAML-NEXT:   - String:          " can be inlined into "
 ; YAML-NEXT:   - Caller:          main
-; YAML-NEXT:   - String:          ' with cost='
-; YAML-NEXT:   - Cost:            '0'
-; YAML-NEXT:   - String:          ' (threshold='
-; YAML-NEXT:   - Threshold:       '337'
-; YAML-NEXT:   - String:          ')'
+; YAML-NEXT:   - String:          " with cost="
+; YAML-NEXT:   - Cost:            "0"
+; YAML-NEXT:   - String:          " (threshold="
+; YAML-NEXT:   - Threshold:       "337"
+; YAML-NEXT:   - String:          ")"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          tinkywinky
-; YAML-NEXT:   - String:          ' inlined into '
+; YAML-NEXT:   - String:          " inlined into "
 ; YAML-NEXT:   - Caller:          main
 ; YAML-NEXT: ...
 
 ; YAML-HOT: ...
 ; YAML-HOT: --- !Passed
 ; YAML-HOT: Pass:            inline
 ; YAML-HOT-NEXT: Name:            Inlined
 ; YAML-HOT-NEXT: Function:        main
 ; YAML-HOT-NEXT: Hotness:         300
 ; YAML-HOT-NEXT: Args:
 ; YAML-HOT-NEXT:   - Callee:          tinkywinky
-; YAML-HOT-NEXT:   - String:          ' inlined into '
+; YAML-HOT-NEXT:   - String:          " inlined into "
 ; YAML-HOT-NEXT:   - Caller:          main
 ; YAML-HOT-NEXT: ...
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-scei-ps4"
 
 declare i32 @patatino()
 

lld/test/mach-o/bind-opcodes.yaml

- name:            _fprintf
     scope:           [ N_EXT ]
     value:           0x0000000000000000
 ...
 
 
 # CHECK:   BindOpcodes:
 # CHECK:     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
 # CHECK:       Imm:             1
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 # CHECK:       Imm:             0
 # CHECK:       Symbol:          dyld_stub_binder
 # CHECK:     - Opcode:          BIND_OPCODE_SET_TYPE_IMM
 # CHECK:       Imm:             1
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
 # CHECK:       Imm:             2
 # CHECK:       ULEBExtraData:
 # CHECK:         - 0x0000000000000000
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 # CHECK:       Imm:             0
 # CHECK:       Symbol:          ___stdoutp
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
 # CHECK:       Imm:             2
 # CHECK:       ULEBExtraData:
 # CHECK:         - 0x0000000000000010
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_DONE
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 
 # CHECK:   LazyBindOpcodes:
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
 # CHECK:       Imm:             2
 # CHECK:       ULEBExtraData:
 # CHECK:         - 0x0000000000000018
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
 # CHECK:       Imm:             1
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 # CHECK:       Imm:             0
 # CHECK:       Symbol:          _fprintf
 # CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_DONE
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 # CHECK:     - Opcode:          BIND_OPCODE_DONE
 # CHECK:       Imm:             0
-# CHECK:       Symbol:          ''
+# CHECK:       Symbol:          ""
 No newline at end of file

lld/test/mach-o/eh-frame-relocs-arm64.yaml

- name:            _someData
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            3
     value:           0x000000000000001C
 page-size:       0x00000000
 ...
 
 # CHECK: --- !native
-# CHECK: path:            '<linker-internal>'
+# CHECK: path:            "<linker-internal>"
 # CHECK: defined-atoms:
 # CHECK:   - ref-name:        L000
 # CHECK:     type:            unwind-cfi
 # CHECK:     content:         [ 18, 00, 00, 00, 00, 00, 00, 00, 03, 7A, 50, 4C,
 # CHECK:                        52, 00, 01, 78, 1E, 07, 9B, {{..}}, {{..}}, {{..}}, {{..}}, 10,
 # CHECK:                        10, 0C, 1F, 00 ]
 # CHECK:     alignment:       8
 # CHECK:     references:

 # CHECK:     content:         [ C0, 03, 5F, D6 ]
 # CHECK:     alignment:       4
 # CHECK:   - name:            _main
 # CHECK:     scope:           global
 # CHECK:     content:         [ C0, 03, 5F, D6 ]
 # CHECK:     alignment:       4
 # CHECK: ...
 
-# # Make sure we don't have any relocations in the __eh_frame section
+# # Make sure we don"t have any relocations in the __eh_frame section
 # CODE-NOT: RELOCATION RECORDS FOR [__eh_frame]
 
 # Also make sure the reloc for the CIE->personality function is the
 # correct offset
 # It should be the offset from the fixup location back to the address
 # of the function we are referencing
 # CODE: Contents of section __eh_frame:
 # This is the CIE:
 # CODE-NEXT: {{[0-9abcdef]*}} 18000000 00000000 037a504c 52000178
 # CODE-NEXT: {{[0-9abcdef]*}} 1e079bd1 ffffff10 100c1f00 28000000
 # This is the important offset for CIE->pfunc
 #                                   ^~~~~~~~~
 # Then we have an FDE starting from 28000000 above
 # CODE-NEXT: {{[0-9abcdef]*}} 20000000 c8ffffff ffffffff 04000000
 # CODE-NEXT: {{[0-9abcdef]*}} 00000000 08c3ffff ffffffff ff0e109e
 # And a new CIE starts at this 00000018 right below here
 # CODE-NEXT: {{[0-9abcdef]*}} 019d0200 00000000 18000000 00000000
 # CODE-NEXT: {{[0-9abcdef]*}} 037a504c 52000178 1e079b8d ffffff10
 # This is the important offset for its CIE->pfunc     ^~~~~~~~~
 No newline at end of file

lld/test/mach-o/objc-category-list-atom.yaml

- name:            __category2
     type:            N_UNDF
     scope:           [ N_EXT ]
     value:           0x0000000000000000
 page-size:       0x00000000
 ...
 
 # Make sure we atomize the category list section by pointer sized atoms.
 
-# CHECK: path:            '<linker-internal>'
+# CHECK: path:            "<linker-internal>"
 # CHECK: defined-atoms:
 # CHECK:   - type:            objc-category-list
 # CHECK:     content:         [ 00, 00, 00, 00, 00, 00, 00, 00 ]
 # CHECK:     merge:           by-content
 # CHECK:     alignment:       8
 # CHECK:     references:
 # CHECK:       - kind:            pointer64
 # CHECK:         offset:          0

lld/test/mach-o/objc-image-info-pass-output.yaml

- segment:         __DATA
     section:         __objc_imageinfo
     type:            S_REGULAR
     attributes:      [ S_ATTR_NO_DEAD_STRIP ]
     address:         0x0000000000000100
     content:         [ 0x00, 0x00, 0x00, 0x00, 0x20, 0x02, 0x00, 0x00 ]
 ...
 
 # CHECK: --- !native
-# CHECK: path:            '<linker-internal>'
+# CHECK: path:            "<linker-internal>"
 # CHECK: defined-atoms:
 # CHECK:   - scope:           hidden
 # CHECK:     type:            objc-image-info
 # CHECK:     content:         [ 00, 00, 00, 00, 20, 02, 00, 00 ]
 # CHECK:     alignment:       4
 # CHECK: ...
 No newline at end of file

lld/test/mach-o/parse-tlv-relocs-x86-64.yaml

relocations:
         symbol:          0
       - offset:          0x00000000
         type:            X86_64_RELOC_UNSIGNED
         length:          3
         pc-rel:          false
         extern:          true
         symbol:          3
 local-symbols:
-  - name:            '_x$tlv$init'
+  - name:            "_x$tlv$init"
     type:            N_SECT
     sect:            2
     value:           0x0000000000000014
 global-symbols:
   - name:            _main
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            1

 # CHECK-NEXT:     type:            tlv-thunk
 # CHECK-NOT:    - name:
 # CHECK:          references:
 # CHECK-NEXT:       - kind:            pointer64
 # CHECK-NEXT:         offset:          0
 # CHECK-NEXT:         target:          __tlv_bootstrap
 # CHECK-NEXT:       - kind:            tlvInitSectionOffset
 # CHECK-NEXT:         offset:          16
-# CHECK-NEXT:         target:          '_x$tlv$init'
+# CHECK-NEXT:         target:          "_x$tlv$init"
 # CHECK:        - name:            _main
 # CHECK-NOT:    - name:
 # CHECK-NEXT:     scope:           global
 # CHECK:          references:
 # CHECK-NEXT:      - kind:            ripRel32Tlv
 # CHECK-NEXT:        offset:          7
 # CHECK-NEXT:        target:          _x

lld/test/mach-o/run-tlv-pass-x86-64.yaml

- segment:         __DATA
     type:            S_REGULAR
     attributes:      [  ]
     alignment:       8
     address:         0x00000000000000C0
     content:         [ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
                        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
            0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
 local-symbols:
-  - name:            '_x$tlv$init'
+  - name:            "_x$tlv$init"
     type:            N_SECT
     sect:            2
     value:           0x0000000000000014
 global-symbols:
   - name:            _main
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            1
     value:           0x0000000000000000
   - name:            _x
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            3
     value:           0x0000000000000018
-  - name:            '__tlv_bootstrap'
+  - name:            "__tlv_bootstrap"
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            4
     value:           0x00000000000000C0
-  - name:            'dyld_stub_binder'
+  - name:            "dyld_stub_binder"
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            4
     value:           0x00000000000000C8
-  - name:            'start'
+  - name:            "start"
     type:            N_SECT
     scope:           [ N_EXT ]
     sect:            4
     value:           0x00000000000000D0
 page-size:       0x00000000
 ...
 
 # CHECK:       - name:            _x
 # CHECK-NEXT:    scope:           global
 # CHECK-NEXT:    type:            tlv-thunk
 # CHECK-NOT:   - name:
 # CHECK:         references:
 # CHECK-NEXT:      - kind:            pointer64
 # CHECK-NEXT:         offset:          0
 # CHECK-NEXT:         target:          __tlv_bootstrap
 # CHECK-NEXT:       - kind:            tlvInitSectionOffset
 # CHECK-NEXT:         offset:          16
-# CHECK-NEXT:         target:          '_x$tlv$init'
-# CHECK:       - name:            '_x$tlv$init'
+# CHECK-NEXT:         target:          "_x$tlv$init"
+# CHECK:       - name:            "_x$tlv$init"
 # CHECK-NEXT:    type:            tlv-zero-fill
 # CHECK:        - name:            _main
 # CHECK-NOT:    - name:
 # CHECK:          references:
 # CHECK-NEXT:       - kind:            ripRel32
 # CHECK-NEXT:         offset:          7
 # CHECK-NEXT:         target:          L[[ID:[0-9]+]]
 # CHECK:        - ref-name:        L[[ID]]

lld/test/mach-o/sectcreate.yaml

 # RUN: lld -flavor darwin -r -arch x86_64 -o %t -sectcreate __DATA __data \
 # RUN:   %p/Inputs/hw.raw_bytes -print_atoms | FileCheck %s
 
 # CHECK: --- !native
-# CHECK: path:            '<linker-internal>'
+# CHECK: path:            "<linker-internal>"
 # CHECK: defined-atoms:
 # CHECK:   - scope:           global
 # CHECK:     type:            sectcreate
 # CHECK:     content:         [ 68, 65, 6C, 6C, 6F, 0A ]
 # CHECK:     section-choice:  custom-required
 # CHECK:     section-name:    __DATA/__data
 # CHECK:     dead-strip:      never

lld/test/mach-o/string-table.yaml

 # RUN: lld -flavor darwin -arch i386 %s %p/Inputs/hello-world-x86.yaml -o %t
 # RUN: obj2yaml %t | FileCheck %s
 #
-# Test that the string table contains a ' ' as its first symbol
+# Test that the string table contains a " " as its first symbol
 #
 
 --- !mach-o
 arch:            x86
 file-type:       MH_OBJECT
 flags:           [ MH_SUBSECTIONS_VIA_SYMBOLS ]
 sections:
   - segment:         __TEXT

 undefined-symbols:
   - name:            _printf
     type:            N_UNDF
     scope:           [ N_EXT ]
     value:           0x0000000000000000
 ...
 
 # CHECK:  StringTable:
-# CHECK-NEXT:  - ' '
+# CHECK-NEXT:  - " "
 # CHECK-NEXT:  - __mh_execute_header
 # CHECK-NEXT:  - _main
 # CHECK-NEXT:  - _printf
 # CHECK-NEXT:  - dyld_stub_binder
-# CHECK-NEXT:  - ''
+# CHECK-NEXT:  - ""

llvm/lib/Support/YAMLTraits.cpp

 //===- lib/Support/YAMLTraits.cpp -----------------------------------------===//
 //
 //                             The LLVM Linker
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/YAMLTraits.h"
 #include "llvm/ADT/SmallString.h"
+#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/Format.h"
 #include "llvm/Support/LineIterator.h"
 #include "llvm/Support/YAMLParser.h"
 #include "llvm/Support/raw_ostream.h"

 
 void Output::endBitSetScalar() {
   this->outputUpToEndOfLine(" ]");
 }
 
 void Output::scalarString(StringRef &S, bool MustQuote) {
   this->newLineCheck();
   if (S.empty()) {
-    // Print '' for the empty string because leaving the field empty is not
+    // Print "" for the empty string because leaving the field empty is not
     // allowed.
-    this->outputUpToEndOfLine("''");
+    this->outputUpToEndOfLine("\"\"");
     return;
   }
   if (!MustQuote) {
     // Only quote if we must.
     this->outputUpToEndOfLine(S);
     return;
   }
-  unsigned i = 0;
-  unsigned j = 0;
   unsigned End = S.size();
-  output("'"); // Starting single quote.
+  SmallString<24> Encoded("\"");
   const char *Base = S.data();
-  while (j < End) {
-    // Escape a single quote by doubling it.
-    if (S[j] == '\'') {
-      output(StringRef(&Base[i], j - i + 1));
-      output("'");
-      i = j + 1;
+  for (unsigned i = 0; i < End; i++) {
+    char C = Base[i];
+    if (isprint(C)) {
+      if (C == '\"' || C == '\\') {
+        Encoded += '\\';
+      }
+      Encoded += C;
+    } else {
+      Encoded += "\\x" + toHex(StringRef(&C, 1));
     }
-    ++j;
   }
-  output(StringRef(&Base[i], j - i));
-  this->outputUpToEndOfLine("'"); // Ending single quote.
+  Encoded += '\"';
+  this->outputUpToEndOfLine(Encoded);
 }
 
 void Output::blockScalarString(StringRef &S) {
   if (!StateStack.empty())
     newLineCheck();
   output(" |");
   outputNewLine();
 

llvm/test/CodeGen/MIR/Generic/frame-info.mir

 # CHECK-NEXT: hasStackMap: false
 # CHECK-NEXT: hasPatchPoint: false
 # CHECK-NEXT: stackSize: 0
 # CHECK-NEXT: offsetAdjustment: 0
 # Note: max alignment can be target specific when printed.
 # CHECK-NEXT: maxAlignment:
 # CHECK-NEXT: adjustsStack: false
 # CHECK-NEXT: hasCalls: false
-# CHECK-NEXT: stackProtector:  ''
+# CHECK-NEXT: stackProtector:  ""
 # CHECK-NEXT: maxCallFrameSize:
 # CHECK-NEXT: hasOpaqueSPAdjustment: false
 # CHECK-NEXT: hasVAStart: false
 # CHECK-NEXT: hasMustTailInVarArgFunc: false
-# CHECK-NEXT: savePoint:       ''
-# CHECK-NEXT: restorePoint:    ''
+# CHECK-NEXT: savePoint:       ""
+# CHECK-NEXT: restorePoint:    ""
 # CHECK: body
 frameInfo:
   maxAlignment:    4
 body: |
   bb.0.entry:
 ...
 ---
 name:            test2
 tracksRegLiveness: true
 
 # CHECK: test2
 # CHECK: frameInfo:
 # CHECK-NEXT: isFrameAddressTaken: true
 # CHECK-NEXT: isReturnAddressTaken: true
 # CHECK-NEXT: hasStackMap: true
 # CHECK-NEXT: hasPatchPoint: true
 # CHECK-NEXT: stackSize: 4
 # CHECK-NEXT: offsetAdjustment: 4
 # Note: max alignment can be target specific when printed.
 # CHECK-NEXT: maxAlignment:
 # CHECK-NEXT: adjustsStack: true
 # CHECK-NEXT: hasCalls: true
-# CHECK-NEXT: stackProtector:  ''
+# CHECK-NEXT: stackProtector:  ""
 # CHECK-NEXT: maxCallFrameSize: 4
 # CHECK-NEXT: hasOpaqueSPAdjustment: true
 # CHECK-NEXT: hasVAStart: true
 # CHECK-NEXT: hasMustTailInVarArgFunc: true
 # CHECK: body
 frameInfo:
   isFrameAddressTaken: true
   isReturnAddressTaken: true

llvm/test/CodeGen/MIR/X86/callee-saved-info.mir

 name:            func
 tracksRegLiveness: true
 frameInfo:
   stackSize:       24
   maxAlignment:    4
   adjustsStack:    true
   hasCalls:        true
 # CHECK: fixedStack:
-# CHECK: , callee-saved-register: '%rbx' }
+# CHECK: , callee-saved-register: "%rbx" }
 fixedStack:
-  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%rbx' }
+  - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: "%rbx" }
 # CHECK: stack:
 # CHECK-NEXT: - { id: 0
-# CHECK: callee-saved-register: '%edi'
+# CHECK: callee-saved-register: "%edi"
 stack:
   - { id: 0, name: b, offset: -20, size: 4, alignment: 4 }
-  - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: '%edi' }
+  - { id: 1, offset: -24, size: 4, alignment: 4, callee-saved-register: "%edi" }
 body: |
   bb.0.entry:
     successors: %bb.1.check
     liveins: %edi, %rbx
 
     frame-setup PUSH64r killed %rbx, implicit-def %rsp, implicit %rsp
     %rsp = frame-setup SUB64ri8 %rsp, 16, implicit-def dead %eflags
     %ebx = COPY %edi

llvm/test/CodeGen/MIR/X86/constant-pool.mir

entry:
     %f = fmul double %c, %e
     ret double %f
   }
 ...
 ---
 # CHECK: name: test
 # CHECK: constants:
 # CHECK-NEXT: - id: 0
-# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   value: "double 3.250000e+00"
 # CHECK-NEXT:   alignment: 8
 # CHECK-NEXT: - id: 1
-# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   value: "float 6.250000e+00"
 # CHECK-NEXT:   alignment: 4
 name:            test
 constants:
   - id:          0
-    value:       'double 3.250000e+00'
+    value:       "double 3.250000e+00"
     alignment:   8
   - id:          1
-    value:       'float 6.250000e+00'
+    value:       "float 6.250000e+00"
     alignment:   4
 body: |
   bb.0.entry:
     ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm1 = CVTSS2SDrr killed %xmm1
     %xmm0 = MULSDrr killed %xmm0, killed %xmm1
     RETQ %xmm0
 ...
 ---
 # Verify that alignment can be inferred:
 # CHECK: name: test2
 # CHECK: constants:
 # CHECK-NEXT: - id: 0
-# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   value: "double 3.250000e+00"
 # CHECK-NEXT:   alignment: 8
 # CHECK-NEXT: - id: 1
-# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   value: "float 6.250000e+00"
 # CHECK-NEXT:   alignment: 4
 name:            test2
 constants:
   - id:          0
-    value:       'double 3.250000e+00'
+    value:       "double 3.250000e+00"
   - id:          1
-    value:       'float 6.250000e+00'
+    value:       "float 6.250000e+00"
 body: |
   bb.0.entry:
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm1 = CVTSS2SDrr killed %xmm1
     %xmm0 = MULSDrr killed %xmm0, killed %xmm1
     RETQ %xmm0
 ...
 ---
 # Verify that the non-standard alignments are respected:
 # CHECK: name: test3
 # CHECK: constants:
 # CHECK-NEXT: - id: 0
-# CHECK-NEXT:   value: 'double 3.250000e+00'
+# CHECK-NEXT:   value: "double 3.250000e+00"
 # CHECK-NEXT:   alignment: 128
 # CHECK-NEXT: - id: 1
-# CHECK-NEXT:   value: 'float 6.250000e+00'
+# CHECK-NEXT:   value: "float 6.250000e+00"
 # CHECK-NEXT:   alignment: 1
 name:            test3
 constants:
   - id:          0
-    value:       'double 3.250000e+00'
+    value:       "double 3.250000e+00"
     alignment:   128
   - id:          1
-    value:       'float 6.250000e+00'
+    value:       "float 6.250000e+00"
     alignment:   1
 body: |
   bb.0.entry:
     ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.0, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.1, _
     %xmm1 = CVTSS2SDrr killed %xmm1
     %xmm0 = MULSDrr killed %xmm0, killed %xmm1
     RETQ %xmm0
 ...
 ---
 # CHECK:  name:  test4
 name:            test4
 constants:
   - id:          0
-    value:       'double 3.250000e+00'
+    value:       "double 3.250000e+00"
   - id:          1
-    value:       'float 6.250000e+00'
+    value:       "float 6.250000e+00"
 body: |
   bb.0.entry:
     ; CHECK:      %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
     ; CHECK-NEXT: %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
     %xmm0 = ADDSDrm killed %xmm0, %rip, 1, _, %const.1 - 12, _
     %xmm1 = ADDSSrm killed %xmm1, %rip, 1, _, %const.0 + 8, _
     %xmm1 = CVTSS2SDrr killed %xmm1
     %xmm0 = MULSDrr killed %xmm0, killed %xmm1
     RETQ %xmm0
 ...

llvm/test/CodeGen/MIR/X86/dynamic-regmask.ll

-; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
-; RUN: FileCheck %s < %t.mir
-; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
-; Check that callee saved registers are printed in a format that can then be parsed.
-
-declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
-
-define i32 @caller(i32 %a0) nounwind {
-  %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
-  %b2 = add i32 %b1, %a0
-  ret i32 %b2
-}
-; CHECK:    name: caller
-; CHECK:    CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w)
-; CHECK:    RET 0, %eax
-
-define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
-  %b1 = mul i32 7, %e0
-  %b2 = udiv i32 5, %e0
-  %b3 = mul i32 7, %d0
-  %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
-  %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
-  %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
-  ret {i32, i32, i32} %b6
-}
-; CHECK: name:            test_callee
-; CHECK: calleeSavedRegisters: [ '%rbx', '%rbp', '%rsp', '%r10', '%r11', '%r12',
-; CHECK:                         '%r13', '%r14', '%r15', '%xmm8', '%xmm9', '%xmm10',
-; CHECK:                         '%xmm11', '%xmm12', '%xmm13', '%xmm14', '%xmm15' ]
-; CHECK: RET 0, %eax, %ecx, %edx
+; RUN: llc -mtriple=x86_64-pc-win32 -stop-after machine-sink %s -o %t.mir
+; RUN: FileCheck %s < %t.mir
+; RUN: llc %t.mir -mtriple=x86_64-pc-win32 -run-pass machine-sink
+; Check that callee saved registers are printed in a format that can then be parsed.
+
+declare x86_regcallcc i32 @callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0)
+
+define i32 @caller(i32 %a0) nounwind {
+  %b1 = call x86_regcallcc i32 @callee(i32 %a0, i32 %a0, i32 %a0, i32 %a0, i32 %a0)
+  %b2 = add i32 %b1, %a0
+  ret i32 %b2
+}
+; CHECK:    name: caller
+; CHECK:    CALL64pcrel32 @callee, CustomRegMask(%bh,%bl,%bp,%bpl,%bx,%ebp,%ebx,%esp,%rbp,%rbx,%rsp,%sp,%spl,%r10,%r11,%r12,%r13,%r14,%r15,%xmm8,%xmm9,%xmm10,%xmm11,%xmm12,%xmm13,%xmm14,%xmm15,%r10b,%r11b,%r12b,%r13b,%r14b,%r15b,%r10d,%r11d,%r12d,%r13d,%r14d,%r15d,%r10w,%r11w,%r12w,%r13w,%r14w,%r15w)
+; CHECK:    RET 0, %eax
+
+define x86_regcallcc {i32, i32, i32} @test_callee(i32 %a0, i32 %b0, i32 %c0, i32 %d0, i32 %e0) nounwind {
+  %b1 = mul i32 7, %e0
+  %b2 = udiv i32 5, %e0
+  %b3 = mul i32 7, %d0
+  %b4 = insertvalue {i32, i32, i32} undef, i32 %b1, 0
+  %b5 = insertvalue {i32, i32, i32} %b4, i32 %b2, 1
+  %b6 = insertvalue {i32, i32, i32} %b5, i32 %b3, 2
+  ret {i32, i32, i32} %b6
+}
+; CHECK: name:            test_callee
+; CHECK: calleeSavedRegisters: [ "%rbx", "%rbp", "%rsp", "%r10", "%r11", "%r12",
+; CHECK:                         "%r13", "%r14", "%r15", "%xmm8", "%xmm9", "%xmm10",
+; CHECK:                         "%xmm11", "%xmm12", "%xmm13", "%xmm14", "%xmm15" ]
+; CHECK: RET 0, %eax, %ecx, %edx

llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
 
 --- |
 
   define i32 @test(i32 %a, i32 %b) {
   body:
     %c = mul i32 %a, %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
-  # CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
-  # CHECK: - { id: 2, class: gr32, preferred-register: '%edi' }
-  - { id: 1, class: gr32, preferred-register: '%0' }
-  - { id: 2, class: gr32, preferred-register: '%edi' }
+  # CHECK: - { id: 1, class: gr32, preferred-register: "%0" }
+  # CHECK: - { id: 2, class: gr32, preferred-register: "%edi" }
+  - { id: 1, class: gr32, preferred-register: "%0" }
+  - { id: 2, class: gr32, preferred-register: "%edi" }
 body: |
   bb.0.body:
     liveins: %edi, %esi
 
     %1 = COPY %esi
     %2 = COPY %edi
     %2 = IMUL32rr %2, %1, implicit-def dead %eflags
     %eax = COPY %2
     RETQ killed %eax
 ...

llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir

--- |
 
   declare i32 @doSomething(i32, i32*)
 
 ...
 ---
 name:            foo
 tracksRegLiveness: true
 liveins:
-  - { reg: '%edi' }
-  - { reg: '%esi' }
+  - { reg: "%edi" }
+  - { reg: "%esi" }
 # CHECK: frameInfo:
-# CHECK:      savePoint: '%bb.2.true'
-# CHECK-NEXT: restorePoint: '%bb.2.true'
+# CHECK:      savePoint: "%bb.2.true"
+# CHECK-NEXT: restorePoint: "%bb.2.true"
 # CHECK: stack
 frameInfo:
   maxAlignment:  4
   hasCalls:      true
-  savePoint:     '%bb.2.true'
-  restorePoint:  '%bb.2.true'
+  savePoint:     "%bb.2.true"
+  restorePoint:  "%bb.2.true"
 stack:
   - { id: 0, name: tmp, offset: 0, size: 4, alignment: 4 }
 body: |
   bb.0:
     successors: %bb.2.true, %bb.1
     liveins: %edi, %esi
 
     %eax = COPY %edi

llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir

 tracksRegLiveness: true
 frameInfo:
   stackSize:       40
   maxAlignment:    8
   adjustsStack:    true
   hasCalls:        true
 # CHECK-LABEL: name: test
 # CHECK: frameInfo
-# CHECK: stackProtector: '%stack.0.StackGuardSlot'
-  stackProtector:  '%stack.0.StackGuardSlot'
+# CHECK: stackProtector: "%stack.0.StackGuardSlot"
+  stackProtector:  "%stack.0.StackGuardSlot"
 fixedStack:
   - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16,
-      callee-saved-register: '%rbx' }
+      callee-saved-register: "%rbx" }
 stack:
   - { id: 0, name: StackGuardSlot, offset: -24, size: 8, alignment: 8 }
   - { id: 1, name: test, offset: -40, size: 8, alignment: 8 }
   - { id: 2, name: a, offset: -29, size: 5, alignment: 1 }
 body: |
   bb.0.entry:
     successors: %bb.1.entry, %bb.2.entry
     liveins: %rbx, %rbx

llvm/test/CodeGen/MIR/X86/function-liveins.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses machine function's liveins
+# This test ensures that the MIR parser parses machine function"s liveins
 # correctly.
 
 --- |
 
   define i32 @test(i32 %a, i32 %b) {
   body:
     %c = add i32 %a, %b
     ret i32 %c
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
 # CHECK: liveins:
-# CHECK-NEXT: - { reg: '%edi', virtual-reg: '%0' }
-# CHECK-NEXT: - { reg: '%esi', virtual-reg: '%1' }
+# CHECK-NEXT: - { reg: "%edi", virtual-reg: "%0" }
+# CHECK-NEXT: - { reg: "%esi", virtual-reg: "%1" }
 liveins:
-  - { reg: '%edi', virtual-reg: '%0' }
-  - { reg: '%esi', virtual-reg: '%1' }
+  - { reg: "%edi", virtual-reg: "%0" }
+  - { reg: "%esi", virtual-reg: "%1" }
 body: |
   bb.0.body:
     liveins: %edi, %esi
 
     %1 = COPY %esi
     %0 = COPY %edi
     %2 = ADD32rr %0, %1, implicit-def dead %eflags
     %eax = COPY %2
     RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/generic-instr-type.mir

define void @test_unsized() {
     ret void
   }
 
 ...
 
 ---
 name:            test_vregs
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }

llvm/test/CodeGen/MIR/X86/jump-table-info.mir

 
 ...
 ---
 name:            test_jumptable
 # CHECK:      jumpTable:
 # CHECK-NEXT: kind: label-difference32
 # CHECK-NEXT: entries:
 # CHECK-NEXT: - id: 0
-# CHECK-NEXT: blocks: [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
+# CHECK-NEXT: blocks: [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ]
 # CHECK-NEXT: body:
 jumpTable:
   kind:          label-difference32
   entries:
     - id:        0
-      blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
+      blocks:    [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ]
 body: |
   bb.0.entry:
     successors: %bb.2.def, %bb.1.entry
 
     %eax = MOV32rr %edi, implicit-def %rax
     CMP32ri8 %edi, 3, implicit-def %eflags
     JA_1 %bb.2.def, implicit %eflags
 
bb.6.lbl4:
     RETQ %eax
 ...
 ---
 name:            test_jumptable2
 jumpTable:
   kind:          label-difference32
   entries:
     - id:        1
-      blocks:    [ '%bb.3.lbl1', '%bb.4.lbl2', '%bb.5.lbl3', '%bb.6.lbl4' ]
+      blocks:    [ "%bb.3.lbl1", "%bb.4.lbl2", "%bb.5.lbl3", "%bb.6.lbl4" ]
 body: |
   bb.0.entry:
     successors: %bb.2.def, %bb.1.entry
 
     %eax = MOV32rr %edi, implicit-def %rax
     CMP32ri8 %edi, 3, implicit-def %eflags
     JA_1 %bb.2.def, implicit %eflags
 

llvm/test/CodeGen/MIR/X86/register-operand-class.mir

 # RUN: llc  -o - %s -march=x86-64 -run-pass none | FileCheck %s
 # Test various aspects of register class specification on machine operands.
 --- |
   define void @func() { ret void }
 ...
 ---
 # CHECK-LABEL: name: func
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 1, class: gr64, preferred-register: '' }
-# CHECK:   - { id: 2, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 3, class: gr16, preferred-register: '' }
-# CHECK:   - { id: 4, class: _, preferred-register: '' }
+# CHECK:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK:   - { id: 1, class: gr64, preferred-register: "" }
+# CHECK:   - { id: 2, class: gr32, preferred-register: "" }
+# CHECK:   - { id: 3, class: gr16, preferred-register: "" }
+# CHECK:   - { id: 4, class: _, preferred-register: "" }
 name: func
 body: |
   bb.0:
     %0 : gr32 = COPY %rax
     %1.sub_32bit : gr64 = COPY %eax
     %rdx = COPY %1
     %2 = COPY %ecx
     %ecx = COPY %2 : gr32
 
     %3 : gr16 = COPY %bx
     %bx = COPY %3 : gr16
 
     %4 : _(s32) = COPY %edx
 ...

llvm/test/CodeGen/MIR/X86/roundtrip.mir

 # RUN: llc -o - %s -mtriple=x86_64-- -run-pass=none | llc -o - -x mir - -mtriple=x86_64-- -run-pass=none | FileCheck %s
 ---
 # CHECK-LABEL: name: func0
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK:   - { id: 1, class: gr32, preferred-register: "" }
 # CHECK: body: |
 # CHECK:   bb.0:
 # CHECK:     %0 = MOV32r0 implicit-def %eflags
 # CHECK:     dead %1 = COPY %0
 # CHECK:     MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
 # CHECK:     RETQ undef %eax
 name: func0
 body: |
   bb.0:
     %0 : gr32 = MOV32r0 implicit-def %eflags
     dead %1 : gr32 = COPY %0
     MOV32mr undef %rcx, 1, _, 0, _, killed %0 :: (volatile store 4)
     RETQ undef %eax
 ...

llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir

body:
     ret i32 %c
   }
 
 ...
 ---
 name:            test
 tracksRegLiveness: true
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: '%esi' }
-# CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: '%edi' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:  - { id: 1, class: gr32, preferred-register: "%esi" }
+# CHECK-NEXT:  - { id: 2, class: gr32, preferred-register: "%edi" }
 registers:
   - { id: 0, class: gr32 }
-  - { id: 1, class: gr32, preferred-register: '%esi' }
-  - { id: 2, class: gr32, preferred-register: '%edi' }
+  - { id: 1, class: gr32, preferred-register: "%esi" }
+  - { id: 2, class: gr32, preferred-register: "%edi" }
 body: |
   bb.0.body:
     liveins: %edi, %esi
 
     %1 = COPY %esi
     %2 = COPY %edi
     %2 = IMUL32rr %2, %1, implicit-def dead %eflags
     %eax = COPY %2
     RETQ killed %eax
 ...

llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir

--- |
   attributes #0 = { "no-frame-pointer-elim"="false" }
 
 ...
 ---
 name:            test
 frameInfo:
   maxAlignment:    4
 # CHECK: fixedStack:
-# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: '' }
+# CHECK-NEXT: - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4, callee-saved-register: "" }
 fixedStack:
   - { id: 0, type: spill-slot, offset: 0, size: 4, alignment: 4 }
 stack:
   - { id: 0, offset: -12, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     %eax = COPY %edi
     RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir

 # RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
-# This test ensures that the MIR parser parses the stack object's debug info
+# This test ensures that the MIR parser parses the stack object"s debug info
 # correctly.
 --- |
   declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
 
   define void @foo() #1 {
   entry:
     %x.i = alloca i8, align 1
     %y.i = alloca [256 x i8], align 16

 ---
 name:            foo
 tracksRegLiveness: true
 frameInfo:
   maxAlignment:    16
 # CHECK-LABEL: foo
 # CHECK: stack:
 # CHECK:  - { id: 0, name: y.i, type: default, offset: 0, size: 256, alignment: 16,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '!4', di-expression: '!10',
-# CHECK-NEXT: di-location: '!11' }
+# CHECK-NEXT: callee-saved-register: "", di-variable: "!4", di-expression: "!10",
+# CHECK-NEXT: di-location: "!11" }
 stack:
-  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: '!4',
-      di-expression: '!7', di-location: '!8' }
+  - { id: 0, name: y.i, offset: 0, size: 256, alignment: 16, di-variable: "!4",
+      di-expression: "!7", di-location: "!8" }
 body: |
   bb.0.entry:
     successors: %bb.1.for.body
   bb.1.for.body:
     successors: %bb.1.for.body
 
     DBG_VALUE %stack.0.y.i, 0, !4, !7, debug-location !8
     JMP_1 %bb.1.for.body
 ...

llvm/test/CodeGen/MIR/X86/stack-objects.mir

 
 ...
 ---
 name:            test
 frameInfo:
   maxAlignment:    8
 # CHECK: stack:
 # CHECK-NEXT: - { id: 0, name: b, type: default, offset: -12, size: 4, alignment: 4,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" }
 # CHECK-NEXT: - { id: 1, name: x, type: default, offset: -24, size: 8, alignment: 8,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
-# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
-# CHECK-NEXT: callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" }
+# CHECK-NEXT: - { id: 2, name: "", type: spill-slot, offset: -32, size: 4, alignment: 4,
+# CHECK-NEXT: callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" }
 stack:
   - { id: 0, name: b, offset: -12, size: 4, alignment: 4 }
   - { id: 1, name: x, offset: -24, size: 8, alignment: 8 }
   - { id: 2, type: spill-slot, offset: -32, size: 4, alignment: 4 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     MOV64mi32 %rsp, 1, _, -16, _, 2
     %eax = MOV32rm %rsp, 1, _, -4, _
     RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir

 ---
 name:            test
 frameInfo:
   stackSize:       24
   offsetAdjustment: -16
   maxAlignment:    8
   adjustsStack:    true
 # CHECK: stack:
-# CHECK-NEXT: - { id: 0, name: '', type: default, offset: -20, size: 4, alignment: 4,
-# CHECK-NEXT:  callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
-# CHECK-NEXT: - { id: 1, name: '', type: default, offset: -32, size: 8, alignment: 8,
-# CHECK-NEXT:  callee-saved-register: '', di-variable: '', di-expression: '', di-location: '' }
+# CHECK-NEXT: - { id: 0, name: "", type: default, offset: -20, size: 4, alignment: 4,
+# CHECK-NEXT:  callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" }
+# CHECK-NEXT: - { id: 1, name: "", type: default, offset: -32, size: 8, alignment: 8,
+# CHECK-NEXT:  callee-saved-register: "", di-variable: "", di-expression: "", di-location: "" }
 # CHECK-NEXT: - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1,
 stack:
   - { id: 0, offset: -20, size: 4, alignment: 4 }
   - { id: 1, offset: -32, size: 8, alignment: 8 }
   - { id: 2, name: y, type: variable-sized, offset: -32, alignment: 1 }
 body: |
   bb.0.entry:
     MOV32mr %rsp, 1, _, -4, _, %edi
     MOV64mi32 %rsp, 1, _, -16, _, 2
     %eax = MOV32rm %rsp, 1, _, -4, _
     RETQ %eax
 ...

llvm/test/CodeGen/MIR/X86/virtual-registers.mir

exit:
     ret i32 %a
   }
 
 ...
 ---
 name:            bar
 tracksRegLiveness: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gr32 }
   - { id: 1, class: gr32 }
   - { id: 2, class: gr32 }
 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi
bb.2.exit:
     %eax = COPY %0
     RETQ %eax
 ...
 ---
 name:            foo
 tracksRegLiveness: true
 # CHECK: name: foo
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 2, class: gr32 }
   - { id: 0, class: gr32 }
   - { id: 10, class: gr32 }
 body: |
   bb.0.entry:
     successors: %bb.2.exit, %bb.1.less
     liveins: %edi

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-scalar.mir

 ...
 ---
 name:            test_mul_i16
 # CHECK-LABEL: name:  test_mul_i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s16) = COPY %edi
 # CHECK-NEXT:     %1(s16) = COPY %esi

 ...
 ---
 name:            test_mul_i32
 # CHECK-LABEL: name:  test_mul_i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s32) = COPY %edi
 # CHECK-NEXT:     %1(s32) = COPY %esi

 ...
 ---
 name:            test_mul_i64
 # CHECK-LABEL: name:  test_mul_i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # CHECK:      body:             |
 # CHECK-NEXT:   bb.0 (%ir-block.0):
 # CHECK-NEXT:     %0(s64) = COPY %rdi
 # CHECK-NEXT:     %1(s64) = COPY %rsi

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir

 ...
 ---
 name:            test_mul_v8i16
 # ALL-LABEL: name:  test_mul_v8i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s16>) = COPY %xmm0
 # ALL-NEXT:     %1(<8 x s16>) = COPY %xmm1
 # ALL-NEXT:     %2(<8 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<8 x s16>)

 ...
 ---
 name:            test_mul_v4i32
 # ALL-LABEL: name:  test_mul_v4i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<4 x s32>) = COPY %xmm0
 # ALL-NEXT:     %1(<4 x s32>) = COPY %xmm1
 # ALL-NEXT:     %2(<4 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<4 x s32>)

 ...
 ---
 name:            test_mul_v2i64
 # ALL-LABEL: name:  test_mul_v2i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<2 x s64>) = COPY %xmm0
 # ALL-NEXT:     %1(<2 x s64>) = COPY %xmm1
 # ALL-NEXT:     %2(<2 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %xmm0 = COPY %2(<2 x s64>)

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir

 ...
 ---
 name:            test_mul_v16i16
 # ALL-LABEL: name:  test_mul_v16i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<16 x s16>) = COPY %ymm0
 # ALL-NEXT:     %1(<16 x s16>) = COPY %ymm1
 # ALL-NEXT:     %2(<16 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<16 x s16>)

 ...
 ---
 name:            test_mul_v8i32
 # ALL-LABEL: name:  test_mul_v8i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s32>) = COPY %ymm0
 # ALL-NEXT:     %1(<8 x s32>) = COPY %ymm1
 # ALL-NEXT:     %2(<8 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<8 x s32>)

 ...
 ---
 name:            test_mul_v4i64
 # ALL-LABEL: name:  test_mul_v4i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<4 x s64>) = COPY %ymm0
 # ALL-NEXT:     %1(<4 x s64>) = COPY %ymm1
 # ALL-NEXT:     %2(<4 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %ymm0 = COPY %2(<4 x s64>)

llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir

 ...
 ---
 name:            test_mul_v32i16
 # ALL-LABEL: name:  test_mul_v32i16
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<32 x s16>) = COPY %zmm0
 # ALL-NEXT:     %1(<32 x s16>) = COPY %zmm1
 # ALL-NEXT:     %2(<32 x s16>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<32 x s16>)

 ...
 ---
 name:            test_mul_v16i32
 # ALL-LABEL: name:  test_mul_v16i32
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<16 x s32>) = COPY %zmm0
 # ALL-NEXT:     %1(<16 x s32>) = COPY %zmm1
 # ALL-NEXT:     %2(<16 x s32>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<16 x s32>)

 ...
 ---
 name:            test_mul_v8i64
 # ALL-LABEL: name:  test_mul_v8i64
 alignment:       4
 legalized:       false
 regBankSelected: false
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: _, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: _, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: _, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: _, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 # ALL:          %0(<8 x s64>) = COPY %zmm0
 # ALL-NEXT:     %1(<8 x s64>) = COPY %zmm1
 # ALL-NEXT:     %2(<8 x s64>) = G_MUL %0, %1
 # ALL-NEXT:     %zmm0 = COPY %2(<8 x s64>)

llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX2.mir

 name:            test_mul_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_mul_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_MUL %0, %0
     RET 0
 
 ...
 ---
 name:            test_add_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_ADD %0, %0
     RET 0
 
 ...
 ---
 name:            test_sub_vec256
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_sub_vec256
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_SUB %0, %0
     RET 0
 
 ...
 ---
 name:            test_load_v8i32_noalign
 # CHECK-LABEL: name:  test_load_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<8 x s32>) = G_LOAD %0(p0) :: (load 32 from %ir.p1, align 1)
     %ymm0 = COPY %1(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_store_v8i32_noalign
 # CHECK-LABEL: name:  test_store_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %ymm0
 
     %0(<8 x s32>) = COPY %ymm0
     %1(p0) = COPY %rdi
     G_STORE %0(<8 x s32>), %1(p0) :: (store 32 into %ir.p1, align 1)
     RET 0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/regbankselect-AVX512.mir

 ...
 ---
 name:            test_mul_vec512
 # CHECK-LABEL: name:  test_mul_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_MUL %0, %0
     RET 0
 
 ...
 ---
 name:            test_add_vec512
 # CHECK-LABEL: name:  test_add_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_ADD %0, %0
     RET 0
 
 ...
 ---
 name:            test_sub_vec512
 # CHECK-LABEL: name:  test_sub_vec512
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
 
     %0(<16 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_SUB %0, %0
     RET 0
 ...
 ---
 
 name:            test_load_v16i32_noalign
 # CHECK-LABEL: name:  test_load_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_store_v16i32_noalign
 # CHECK-LABEL: name:  test_store_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:       registers:
-# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# CHECK-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# CHECK-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %zmm0
 
     %0(<16 x s32>) = COPY %zmm0
     %1(p0) = COPY %rdi
     G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
     RET 0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/regbankselect-X32.mir

 # RUN: llc -mtriple=i386-linux-gnu -global-isel                       -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=FAST
 # RUN: llc -mtriple=i386-linux-gnu -global-isel -regbankselect-greedy -run-pass=regbankselect %s -o - | FileCheck %s --check-prefix=CHECK --check-prefix=GREEDY
 
 --- |
   define void @test_uadde_i32() {
     ret void
   }
 
 ...
 ---
 name:            test_uadde_i32
 # CHECK-LABEL: name:  test_uadde_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s32) = IMPLICIT_DEF
     %1(s32) = IMPLICIT_DEF
     %2(s1) = IMPLICIT_DEF
     %3(s32), %4(s1) = G_UADDE %0, %1, %2
     RET 0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir

 name:            test_add_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i8
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s8) = COPY %edi
     %1(s8) = COPY %esi
     %2(s8) = G_ADD %0, %1
     %al = COPY %2(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_add_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i16
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s16) = COPY %edi
     %1(s16) = COPY %esi
     %2(s16) = G_ADD %0, %1
     %ax = COPY %2(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            test_add_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s32) = G_ADD %0, %1
     %eax = COPY %2(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_add_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_i64
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
     %rax = COPY %2(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_mul_gpr
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_mul_gpr
 # CHECK: registers:
-# CHECK:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 3, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 4, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 5, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 6, class: gpr, preferred-register: '' }
-# CHECK:  - { id: 7, class: gpr, preferred-register: '' }
+# CHECK:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 2, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 3, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 4, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 5, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 6, class: gpr, preferred-register: "" }
+# CHECK:  - { id: 7, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
   - { id: 5, class: _ }
   - { id: 6, class: _ }

 name:            test_add_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_float
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 2, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(s32) = COPY %xmm0
     %1(s32) = COPY %xmm1
     %2(s32) = G_FADD %0, %1
     %xmm0 = COPY %2(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_double
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 2, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(s64) = COPY %xmm0
     %1(s64) = COPY %xmm1
     %2(s64) = G_FADD %0, %1
     %xmm0 = COPY %2(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_v4i32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 2, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_ADD %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_add_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 tracksRegLiveness: true
 # CHECK-LABEL: name:            test_add_v4f32
 # CHECK: registers:
-# CHECK:  - { id: 0, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 1, class: vecr, preferred-register: '' }
-# CHECK:  - { id: 2, class: vecr, preferred-register: '' }
+# CHECK:  - { id: 0, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 1, class: vecr, preferred-register: "" }
+# CHECK:  - { id: 2, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_FADD %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i8
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i16
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_load_i64
 alignment:       4
 exposesReturnsTwice: false
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_i64
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_load_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_float
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_double
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_load_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_load_v4i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: vecr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: vecr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
     %xmm0 = COPY %1(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_i32
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %rsi
 
     %0(s32) = COPY %edi
     %1(p0) = COPY %rsi
     G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_store_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_i64
 # CHECK: registers:
-# CHECK:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK:   - { id: 1, class: gpr, preferred-register: '' }
+# CHECK:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK:   - { id: 1, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_float
 # CHECK: registers:
 
-# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
-# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
+# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
+# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: "" }
 
-# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %xmm0
 

 name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: false
 selected:        false
 # CHECK-LABEL: name:            test_store_double
 # CHECK: registers:
 
-# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
-# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: '' }
+# FAST-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# FAST-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
+# FAST-NEXT:    - { id: 2, class: gpr, preferred-register: "" }
 
-# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: '' }
-# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT:    - { id: 0, class: vecr, preferred-register: "" }
+# GREEDY-NEXT:    - { id: 1, class: gpr, preferred-register: "" }
 
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %xmm0
 

 
 ...
 ---
 name:            constInt_check
 alignment:       4
 legalized:       true
 # CHECK-LABEL: name:            constInt_check
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s8) = G_CONSTANT i8 8
     %1(s16) = G_CONSTANT i16 16
     %2(s32) = G_CONSTANT i32 32
     %3(s64) = G_CONSTANT i64 64
     RET 0
 
 ...
 ---
 name:            trunc_check
 alignment:       4
 legalized:       true
 # CHECK-LABEL: name:            trunc_check
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(s32) = IMPLICIT_DEF
     %1(s1) = G_TRUNC %0(s32)
     %2(s8) = G_TRUNC %0(s32)
     %3(s16) = G_TRUNC %0(s32)
     RET 0
 
 ...
 ---
 name:            test_gep
 legalized:       true
 # CHECK-LABEL: name:            test_gep
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 2, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 3, class: gpr, preferred-register: "" }
+# CHECK-NEXT:  - { id: 4, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     %0(p0) = IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
     %2(p0) = G_GEP %0, %1(s32)
     %3(s64) = G_CONSTANT i64 20
     %4(p0) = G_GEP %0, %3(s64)
     RET 0
 
 ...
 ---
 name:            test_icmp_eq_i8
 # CHECK-LABEL: name:  test_icmp_eq_i8
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s8) = COPY %edi
     %1(s8) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s8), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i16
 # CHECK-LABEL: name:  test_icmp_eq_i16
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s16) = COPY %edi
     %1(s16) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s16), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i32
 # CHECK-LABEL: name:  test_icmp_eq_i32
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s32) = COPY %edi
     %1(s32) = COPY %esi
     %2(s1) = G_ICMP intpred(eq), %0(s32), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            test_icmp_eq_i64
 # CHECK-LABEL: name:  test_icmp_eq_i64
 alignment:       4
 legalized:       true
 regBankSelected: false
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gpr, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s1) = G_ICMP intpred(eq), %0(s64), %1
     %al = COPY %2(s1)
     RET 0, implicit %al
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-add-v128.mir

 ...
 ---
 name:            test_add_v16i8
 # ALL-LABEL: name:  test_add_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDBrr %0, %1
 #
 # AVX1:                %2 = VPADDBrr %0, %1
 #

 ...
 ---
 name:            test_add_v8i16
 # ALL-LABEL: name:  test_add_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDWrr %0, %1
 #
 # AVX1:                %2 = VPADDWrr %0, %1
 #

 ...
 ---
 name:            test_add_v4i32
 # ALL-LABEL: name:  test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDDrr %0, %1
 #
 # AVX1:                %2 = VPADDDrr %0, %1
 #

 ...
 ---
 name:            test_add_v2i64
 # ALL-LABEL: name:  test_add_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PADDQrr %0, %1
 #
 # AVX1:                %2 = VPADDQrr %0, %1
 #

llvm/test/CodeGen/X86/GlobalISel/select-add-v256.mir

 ...
 ---
 name:            test_add_v32i8
 # ALL-LABEL: name:  test_add_v32i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDBYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDBYrr %0, %1
 #

 ...
 ---
 name:            test_add_v16i16
 # ALL-LABEL: name:  test_add_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDWYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDWYrr %0, %1
 #

 ...
 ---
 name:            test_add_v8i32
 # ALL-LABEL: name:  test_add_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDDYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDDZ256rr %0, %1
 #

 ...
 ---
 name:            test_add_v4i64
 # ALL-LABEL: name:  test_add_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPADDQYrr %0, %1
 #
 # AVX512VL:            %2 = VPADDQZ256rr %0, %1
 #

llvm/test/CodeGen/X86/GlobalISel/select-add-v512.mir

 ...
 ---
 name:            test_add_v64i8
 # ALL-LABEL: name:  test_add_v64i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDBZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<64 x s8>) = COPY %zmm0
     %1(<64 x s8>) = COPY %zmm1
     %2(<64 x s8>) = G_ADD %0, %1
     %zmm0 = COPY %2(<64 x s8>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v32i16
 # ALL-LABEL: name:  test_add_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_ADD %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v16i32
 # ALL-LABEL: name:  test_add_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_ADD %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_add_v8i64
 # ALL-LABEL: name:  test_add_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPADDQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_ADD %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-add-x32.mir

 # RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X32
 --- |
   define i64 @test_add_i64(i64 %a, i64 %b) {
     %r = add i64 %a, %b
     ret i64 %r
   }
 
 ...
 ---
 name:            test_add_i64
 # X32-LABEL: name:  test_add_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # X32:      registers:
-# X32-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 4, class: gpr, preferred-register: '' }
-# X32-NEXT:   - { id: 5, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 6, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 7, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 8, class: gr32, preferred-register: '' }
-# X32-NEXT:   - { id: 9, class: gpr, preferred-register: '' }
+# X32-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 4, class: gpr, preferred-register: "" }
+# X32-NEXT:   - { id: 5, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 6, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 7, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 8, class: gr32, preferred-register: "" }
+# X32-NEXT:   - { id: 9, class: gpr, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }

llvm/test/CodeGen/X86/GlobalISel/select-add.mir

 ...
 
 ---
 name:            test_add_i64
 # ALL-LABEL: name:            test_add_i64
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %rdi
 # ALL-NEXT: %1 = COPY %rsi
 # ALL-NEXT: %2 = ADD64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_ADD %0, %1
     %rax = COPY %2(s64)
 
 ...
 
 ---
 name:            test_add_i32
 # ALL-LABEL: name:            test_add_i32
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %edi
 # ALL-NEXT: %1 = COPY %esi
 # ALL-NEXT: %2 = ADD32rr %0, %1
 body:             |

 ---
 name:            test_add_i16
 # ALL-LABEL: name:            test_add_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr16, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr16, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr16, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL: %0 = COPY %di
 # ALL: %1 = COPY %si
 # ALL: %2 = ADD16rr %0, %1, implicit-def %eflags
 body:             |

 ---
 name:            test_add_i8
 # ALL-LABEL: name:            test_add_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr8, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL: %0 = COPY %dil
 # ALL: %1 = COPY %sil
 # ALL: %2 = ADD8rr %0, %1, implicit-def %eflags
 body:             |

 name:            test_add_float
 # ALL-LABEL: name:            test_add_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = ADDSSrr %0, %1
 # AVX-NEXT:     %2 = VADDSSrr %0, %1

 name:            test_add_double
 # ALL-LABEL: name:            test_add_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = ADDSDrr %0, %1
 # AVX-NEXT:     %2 = VADDSDrr %0, %1

 name:            test_add_v4i32
 # ALL-LABEL: name:            test_add_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = PADDDrr %0, %1
 # AVX-NEXT:      %2 = VPADDDrr %0, %1

 name:            test_add_v4f32
 # ALL-LABEL: name:            test_add_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = ADDPSrr %0, %1
 # AVX-NEXT:      %2 = VADDPSrr %0, %1

llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

 ...
 ---
 name:            test_icmp_eq_i8
 # CHECK-LABEL: name:  test_icmp_eq_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %dil
 # CHECK-NEXT:     %1 = COPY %sil
 # CHECK-NEXT:     CMP8rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i16
 # CHECK-LABEL: name:  test_icmp_eq_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %di
 # CHECK-NEXT:     %1 = COPY %si
 # CHECK-NEXT:     CMP16rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i64
 # CHECK-LABEL: name:  test_icmp_eq_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %rsi
 # CHECK-NEXT:     CMP64rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_eq_i32
 # CHECK-LABEL: name:  test_icmp_eq_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ne_i32
 # CHECK-LABEL: name:  test_icmp_ne_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ugt_i32
 # CHECK-LABEL: name:  test_icmp_ugt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_uge_i32
 # CHECK-LABEL: name:  test_icmp_uge_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ult_i32
 # CHECK-LABEL: name:  test_icmp_ult_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_ule_i32
 # CHECK-LABEL: name:  test_icmp_ule_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sgt_i32
 # CHECK-LABEL: name:  test_icmp_sgt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sge_i32
 # CHECK-LABEL: name:  test_icmp_sge_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_slt_i32
 # CHECK-LABEL: name:  test_icmp_slt_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_icmp_sle_i32
 # CHECK-LABEL: name:  test_icmp_sle_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
-# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
+# CHECK-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 4, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %esi
 # CHECK-NEXT:     CMP32rr %0, %1, implicit-def %eflags

llvm/test/CodeGen/X86/GlobalISel/select-constant.mir

 ...
 ---
 name:            const_i8
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i8
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV8ri 2
 body:             |
   bb.1 (%ir-block.0):
     %0(s8) = G_CONSTANT i8 2
     %al = COPY %0(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            const_i16
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i16
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr16, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV16ri 3
 body:             |
   bb.1 (%ir-block.0):
     %0(s16) = G_CONSTANT i16 3
     %ax = COPY %0(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            const_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 4
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 4
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            const_i64
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri 68719476720
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 68719476720
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            const_i64_u32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64_u32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri32 1879048192
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 1879048192
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            const_i64_i32
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            const_i64_i32
 # CHECK: registers:
-# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV64ri32 -1
 body:             |
   bb.1 (%ir-block.0):
     %0(s64) = G_CONSTANT i64 -1
     %rax = COPY %0(s64)
     RET 0, implicit %rax
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

 ...
 ---
 name:            test_zext_i1
 # ALL-LABEL: name:  test_zext_i1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
-# ALL-NEXT:   - { id: 3, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: "" }
+# ALL-NEXT:   - { id: 3, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = COPY %0
 # ALL-NEXT:     %3 = SUBREG_TO_REG 0, %1, 1
 # ALL-NEXT:     %2 = AND64ri8 %3, 1, implicit-def %eflags

 ...
 ---
 name:            test_sext_i8
 # ALL-LABEL: name:  test_sext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVSX64rr8 %0
 # ALL-NEXT:     %rax = COPY %1
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s64) = G_SEXT %0(s8)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 name:            test_sext_i16
 # ALL-LABEL: name:  test_sext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVSX64rr16 %0
 # ALL-NEXT:     %rax = COPY %1
 # ALL-NEXT:     RET 0, implicit %rax
 body:             |

llvm/test/CodeGen/X86/GlobalISel/select-ext.mir

 ...
 ---
 name:            test_zext_i1
 # ALL-LABEL: name:  test_zext_i1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %2 = SUBREG_TO_REG 0, %0, 1
 # ALL-NEXT:     %1 = AND32ri8 %2, 1, implicit-def %eflags
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax

 ...
 ---
 name:            test_zext_i8
 # ALL-LABEL: name:  test_zext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVZX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s32) = G_ZEXT %0(s8)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_zext_i16
 # ALL-LABEL: name:  test_zext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVZX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s16) = COPY %edi
     %1(s32) = G_ZEXT %0(s16)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_sext_i8
 # ALL-LABEL: name:  test_sext_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %dil
 # ALL-NEXT:     %1 = MOVSX32rr8 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s8) = COPY %edi
     %1(s32) = G_SEXT %0(s8)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 name:            test_sext_i16
 # ALL-LABEL: name:  test_sext_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = MOVSX32rr16 %0
 # ALL-NEXT:     %eax = COPY %1
 # ALL-NEXT:     RET 0, implicit %eax
 body:             |

llvm/test/CodeGen/X86/GlobalISel/select-gep.mir

 # RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=CHECK
 
 --- |
   define i32* @test_gep_i32(i32* %arr) {
     %arrayidx = getelementptr i32, i32* %arr, i32 5
     ret i32* %arrayidx
   }
 ...
 ---
 name:            test_gep_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name:            test_gep_i32
 # CHECK: registers:
-# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: '' }
-# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: '' }
-# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: '' }
+# CHECK-NEXT: - { id: 0, class: gr64, preferred-register: "" }
+# CHECK-NEXT: - { id: 1, class: gr64_nosp, preferred-register: "" }
+# CHECK-NEXT: - { id: 2, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # CHECK:  body:
 # CHECK:       %1 = MOV64ri32 20
 # CHECK-NEXT:  %2 = LEA64r %0, 1, %1, 0, _
 body:             |

llvm/test/CodeGen/X86/GlobalISel/select-inc.mir

 # RUN: llc -mtriple=x86_64-linux-gnu                     -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,INC
 # RUN: llc -mtriple=x86_64-linux-gnu -mattr=+slow-incdec -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=ALL,ADD
 
 --- |
   define i8 @test_add_i8(i8 %arg1) {
     %ret = add i8 %arg1, 1
     ret i8 %ret
   }
 ...
 
 ---
 name:            test_add_i8
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: '' }
-# INC-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
-# ADD-NEXT:  - { id: 1, class: gr8, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr8, preferred-register: "" }
+# INC-NEXT:  - { id: 1, class: gpr, preferred-register: "" }
+# ADD-NEXT:  - { id: 1, class: gr8, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %al
 # INC-NEXT: %2 = INC8r %0
 # ADD-NEXT: %1 = MOV8ri 1
 # ADD-NEXT: %2 = ADD8rr %0, %1

llvm/test/CodeGen/X86/GlobalISel/select-leaf-constant.mir

 ...
 ---
 name:            const_i32_1
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1_optsize
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1_optsize
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32r1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1b
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1b
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32ri 1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...
 ---
 name:            const_i32_1_optsizeb
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK-LABEL: name: const_i32_1_optsizeb
 # CHECK:       registers:
-# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
+# CHECK-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
 # CHECK:  body:
 # CHECK:    %0 = MOV32r1
 body:             |
   bb.1 (%ir-block.0):
     %0(s32) = G_CONSTANT i32 1
     %eax = COPY %0(s32)
     RET 0, implicit %eax
 ...

llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir

 ...
 ---
 name:            test_load_i8
 # ALL-LABEL: name:  test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_load_i16
 # ALL-LABEL: name:  test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_load_i32
 # ALL-LABEL: name:  test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_store_i8
 # ALL-LABEL: name:  test_store_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr8, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_store_i16
 # ALL-LABEL: name:  test_store_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_store_i32
 # ALL-LABEL: name:  test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }

 ...
 ---
 name:            test_load_ptr
 # ALL-LABEL: name:  test_load_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 fixedStack:
   - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
 # ALL:          %1 = LEA32r %fixed-stack.0, 1, _, 0, _
 # ALL-NEXT:     %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)

 ...
 ---
 name:            test_store_ptr
 # ALL-LABEL: name:  test_store_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 3, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
   - { id: 3, class: gpr }
 fixedStack:
   - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
   - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }

llvm/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir

 ...
 ---
 # ALL-LABEL: name:            test_load_i8
 name:            test_load_i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr8, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr8, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
 # ALL:     %al = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i16
 name:            test_load_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr16, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr16, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
 # ALL:     %ax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i32
 name:            test_load_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr32, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %eax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %eax = COPY %1(s32)
     RET 0, implicit %eax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_i64
 name:            test_load_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %rax = COPY %1(s64)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_load_float
 name:            test_load_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr32, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr32, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_float_vecreg
 name:            test_load_float_vecreg
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: fr32, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: fr32x, preferred-register: '' }
+# ALL:          - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F:   - { id: 1, class: fr32, preferred-register: "" }
+# AVX512ALL:    - { id: 1, class: fr32x, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:       %0 = COPY %rdi
 # SSE:       %1 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # AVX:       %1 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # AVX512ALL: %1 = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
     %xmm0 = COPY %1(s32)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_double
 name:            test_load_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL:     %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_load_double_vecreg
 name:            test_load_double_vecreg
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: fr64, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: fr64x, preferred-register: '' }
+# ALL:          - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F:   - { id: 1, class: fr64, preferred-register: "" }
+# AVX512ALL:    - { id: 1, class: fr64x, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:       %0 = COPY %rdi
 # SSE:       %1 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # AVX:       %1 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # AVX512ALL: %1 = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
 # ALL: %xmm0 = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
     %xmm0 = COPY %1(s64)
     RET 0, implicit %xmm0
 
 ...
 ---
 # ALL-LABEL: name:            test_store_i32
 name:            test_store_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %edi
 # ALL:     %1 = COPY %rsi
 # ALL:     MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %rsi
 
     %0(s32) = COPY %edi
     %1(p0) = COPY %rsi
     G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_i64
 name:            test_store_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL:     %0 = COPY %rdi
 # ALL:     %1 = COPY %rsi
 # ALL:     MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(s64) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_float
 name:            test_store_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: fr32x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
-# ALL:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL:   - { id: 0, class: fr32x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
+# ALL:   - { id: 2, class: gr32, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
 # ALL:     %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_float_vec
 name:            test_store_float_vec
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr32, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: fr32x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 0, class: fr32, preferred-register: "" }
+# AVX512ALL:    - { id: 0, class: fr32x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX:       VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
 # ALL:       %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_double
 name:            test_store_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: fr64x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
-# ALL:   - { id: 2, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: fr64x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
+# ALL:   - { id: 2, class: gr64, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:     %0 = COPY %xmm0
 # ALL:     %1 = COPY %rdi
 # ALL:     %2 = COPY %0
 # ALL:     MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
 # ALL:     %rax = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_double_vec
 name:            test_store_double_vec
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: fr64, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: fr64x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 0, class: fr64, preferred-register: "" }
+# AVX512ALL:    - { id: 0, class: fr64x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX:       VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
 # ALL:       %rax = COPY %1

 ---
 # ALL-LABEL: name:            test_load_ptr
 name:            test_load_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1)
     %rax = COPY %1(p0)
     RET 0, implicit %rax
 
 ...
 ---
 # ALL-LABEL: name:            test_store_ptr
 name:            test_store_ptr
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1)
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %rsi
 
     %0(p0) = COPY %rdi
     %1(p0) = COPY %rsi
     G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1)
     RET 0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-memop-v128.mir

 ...
 ---
 # ALL-LABEL: name:            test_load_v4i32_noalign
 name:            test_load_v4i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:          - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
+# ALL:          - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: "" }
+# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:      %0 = COPY %rdi
 # SSE:      %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX:      %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX512F:  %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
 # ALL: %xmm0 = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_load_v4i32_align
 name:            test_load_v4i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# ALL:   - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: '' }
+# ALL:   - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F:   - { id: 1, class: vr128, preferred-register: "" }
+# AVX512ALL:    - { id: 1, class: vr128x, preferred-register: "" }
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # ALL:      %0 = COPY %rdi
 # SSE:      %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX:      %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX512F:  %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
 # ALL: %xmm0 = COPY %1

 ...
 ---
 # ALL-LABEL: name:            test_store_v4i32_align
 name:            test_store_v4i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: "" }
+# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX:       VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX512F:   VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
 # AVX512VL:  VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)

 ...
 ---
 # ALL-LABEL: name:            test_store_v4i32_noalign
 name:            test_store_v4i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
-# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: '' }
-# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: '' }
-# ALL:   - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F:   - { id: 0, class: vr128, preferred-register: "" }
+# AVX512ALL:    - { id: 0, class: vr128x, preferred-register: "" }
+# ALL:   - { id: 1, class: gr64, preferred-register: "" }
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # ALL:       %0 = COPY %xmm0
 # ALL:       %1 = COPY %rdi
 # SSE:       MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX:       VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX512F:   VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
 # AVX512VL:  VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)

llvm/test/CodeGen/X86/GlobalISel/select-memop-v256.mir

 ...
 ---
 name:            test_load_v8i32_noalign
 # ALL-LABEL: name:  test_load_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: "" }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: "" }
+# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # NO_AVX512F:           %0 = COPY %rdi
 # NO_AVX512F-NEXT:      %1 = VMOVUPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1, align 1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #

 ...
 ---
 name:            test_load_v8i32_align
 # ALL-LABEL: name:  test_load_v8i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 0, class: gr64, preferred-register: "" }
+# NO_AVX512F-NEXT:    - { id: 1, class: vr256, preferred-register: "" }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 0, class: gr64, preferred-register: "" }
+# AVX512ALL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # NO_AVX512F:           %0 = COPY %rdi
 # NO_AVX512F-NEXT:      %1 = VMOVAPSYrm %0, 1, _, 0, _ :: (load 32 from %ir.p1)
 # NO_AVX512F-NEXT:      %ymm0 = COPY %1
 # NO_AVX512F-NEXT:      RET 0, implicit %ymm0
 #

 ...
 ---
 name:            test_store_v8i32_noalign
 # ALL-LABEL: name:  test_store_v8i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: "" }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: "" }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # NO_AVX512F:           %0 = COPY %ymm0
 # NO_AVX512F-NEXT:      %1 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVUPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1, align 1)
 # NO_AVX512F-NEXT:      RET 0
 #

 ...
 ---
 name:            test_store_v8i32_align
 # ALL-LABEL: name:  test_store_v8i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NO_AVX512F:       registers:
-# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: '' }
-# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: '' }
+# NO_AVX512F-NEXT:    - { id: 0, class: vr256, preferred-register: "" }
+# NO_AVX512F-NEXT:    - { id: 1, class: gr64, preferred-register: "" }
 #
 # AVX512ALL:        registers:
-# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: '' }
+# AVX512ALL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512ALL-NEXT:     - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # NO_AVX512F:           %0 = COPY %ymm0
 # NO_AVX512F-NEXT:      %1 = COPY %rdi
 # NO_AVX512F-NEXT:      VMOVAPSYmr %1, 1, _, 0, _, %0 :: (store 32 into %ir.p1)
 # NO_AVX512F-NEXT:      RET 0
 #

llvm/test/CodeGen/X86/GlobalISel/select-memop-v512.mir

 ...
 ---
 name:            test_load_v16i32_noalign
 # AVX512F-LABEL: name:  test_load_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # AVX512F:          %0 = COPY %rdi
 # AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 1)
 # AVX512F-NEXT:     %zmm0 = COPY %1
 # AVX512F-NEXT:     RET 0, implicit %zmm0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 1)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_load_v16i32_align
 # AVX512F-LABEL: name:  test_load_v16i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# AVX512F-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: vecr }
 # AVX512F:          %0 = COPY %rdi
 # AVX512F-NEXT:     %1 = VMOVUPSZrm %0, 1, _, 0, _ :: (load 64 from %ir.p1, align 32)
 # AVX512F-NEXT:     %zmm0 = COPY %1
 # AVX512F-NEXT:     RET 0, implicit %zmm0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(p0) = COPY %rdi
     %1(<16 x s32>) = G_LOAD %0(p0) :: (load 64 from %ir.p1, align 32)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_store_v16i32_noalign
 # AVX512F-LABEL: name:  test_store_v16i32_noalign
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # AVX512F:          %0 = COPY %zmm0
 # AVX512F-NEXT:     %1 = COPY %rdi
 # AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 1)
 # AVX512F-NEXT:     RET 0
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi, %zmm0
 
     %0(<16 x s32>) = COPY %zmm0
     %1(p0) = COPY %rdi
     G_STORE %0(<16 x s32>), %1(p0) :: (store 64 into %ir.p1, align 1)
     RET 0
 
 ...
 ---
 name:            test_store_v16i32_align
 # AVX512F-LABEL: name:  test_store_v16i32_align
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX512F:      registers:
-# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
+# AVX512F-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# AVX512F-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: gpr }
 # AVX512F:          %0 = COPY %zmm0
 # AVX512F-NEXT:     %1 = COPY %rdi
 # AVX512F-NEXT:     VMOVUPSZmr %1, 1, _, 0, _, %0 :: (store 64 into %ir.p1, align 32)
 # AVX512F-NEXT:     RET 0
 body:             |

llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir

 ...
 ---
 name:            test_mul_i16
 # ALL-LABEL: name:  test_mul_i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr16, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %di
 # ALL-NEXT:     %1 = COPY %si
 # ALL-NEXT:     %2 = IMUL16rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_mul_i32
 # ALL-LABEL: name:  test_mul_i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %edi
 # ALL-NEXT:     %1 = COPY %esi
 # ALL-NEXT:     %2 = IMUL32rr %0, %1, implicit-def %eflags

 ...
 ---
 name:            test_mul_i64
 # ALL-LABEL: name:  test_mul_i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: gr64, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      body:             |
 # ALL:          %0 = COPY %rdi
 # ALL-NEXT:     %1 = COPY %rsi
 # ALL-NEXT:     %2 = IMUL64rr %0, %1, implicit-def %eflags

llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir

 ...
 ---
 name:            test_mul_v8i16
 # CHECK-LABEL: name:  test_mul_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = PMULLWrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v8i16_avx
 # CHECK-LABEL: name:  test_mul_v8i16_avx
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v8i16_avx512bwvl
 # CHECK-LABEL: name:  test_mul_v8i16_avx512bwvl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<8 x s16>) = COPY %xmm0
     %1(<8 x s16>) = COPY %xmm1
     %2(<8 x s16>) = G_MUL %0, %1
     %xmm0 = COPY %2(<8 x s16>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32
 # CHECK-LABEL: name:  test_mul_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = PMULLDrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32_avx
 # CHECK-LABEL: name:  test_mul_v4i32_avx
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v4i32_avx512vl
 # CHECK-LABEL: name:  test_mul_v4i32_avx512vl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<4 x s32>) = COPY %xmm0
     %1(<4 x s32>) = COPY %xmm1
     %2(<4 x s32>) = G_MUL %0, %1
     %xmm0 = COPY %2(<4 x s32>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v2i64
 # CHECK-LABEL: name:  test_mul_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZ128rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %xmm0, %xmm1
 
     %0(<2 x s64>) = COPY %xmm0
     %1(<2 x s64>) = COPY %xmm1
     %2(<2 x s64>) = G_MUL %0, %1
     %xmm0 = COPY %2(<2 x s64>)
     RET 0, implicit %xmm0
 
 ...
 ---
 name:            test_mul_v16i16
 # CHECK-LABEL: name:  test_mul_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWYrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<16 x s16>) = COPY %ymm0
     %1(<16 x s16>) = COPY %ymm1
     %2(<16 x s16>) = G_MUL %0, %1
     %ymm0 = COPY %2(<16 x s16>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v16i16_avx512bwvl
 # CHECK-LABEL: name:  test_mul_v16i16_avx512bwvl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<16 x s16>) = COPY %ymm0
     %1(<16 x s16>) = COPY %ymm1
     %2(<16 x s16>) = G_MUL %0, %1
     %ymm0 = COPY %2(<16 x s16>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v8i32
 # CHECK-LABEL: name:  test_mul_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr256, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr256, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr256, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDYrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<8 x s32>) = COPY %ymm0
     %1(<8 x s32>) = COPY %ymm1
     %2(<8 x s32>) = G_MUL %0, %1
     %ymm0 = COPY %2(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v8i32_avx512vl
 # CHECK-LABEL: name:  test_mul_v8i32_avx512vl
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<8 x s32>) = COPY %ymm0
     %1(<8 x s32>) = COPY %ymm1
     %2(<8 x s32>) = G_MUL %0, %1
     %ymm0 = COPY %2(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v4i64
 # CHECK-LABEL: name:  test_mul_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZ256rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %ymm0, %ymm1
 
     %0(<4 x s64>) = COPY %ymm0
     %1(<4 x s64>) = COPY %ymm1
     %2(<4 x s64>) = G_MUL %0, %1
     %ymm0 = COPY %2(<4 x s64>)
     RET 0, implicit %ymm0
 
 ...
 ---
 name:            test_mul_v32i16
 # CHECK-LABEL: name:  test_mul_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_MUL %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_mul_v16i32
 # CHECK-LABEL: name:  test_mul_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_MUL %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_mul_v8i64
 # CHECK-LABEL: name:  test_mul_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# CHECK-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # CHECK:          %2 = VPMULLQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_MUL %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-sub-v128.mir

 ...
 ---
 name:            test_sub_v16i8
 # ALL-LABEL: name:  test_sub_v16i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBBrr %0, %1
 #
 # AVX1:                %2 = VPSUBBrr %0, %1
 #

 ...
 ---
 name:            test_sub_v8i16
 # ALL-LABEL: name:  test_sub_v8i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBWrr %0, %1
 #
 # AVX1:                %2 = VPSUBWrr %0, %1
 #

 ...
 ---
 name:            test_sub_v4i32
 # ALL-LABEL: name:  test_sub_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBDrr %0, %1
 #
 # AVX1:                %2 = VPSUBDrr %0, %1
 #

 ...
 ---
 name:            test_sub_v2i64
 # ALL-LABEL: name:  test_sub_v2i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # NOVL:            registers:
-# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: '' }
-# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: '' }
+# NOVL-NEXT:         - { id: 0, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 1, class: vr128, preferred-register: "" }
+# NOVL-NEXT:         - { id: 2, class: vr128, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr128x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # SSE2:                %2 = PSUBQrr %0, %1
 #
 # AVX1:                %2 = VPSUBQrr %0, %1
 #

llvm/test/CodeGen/X86/GlobalISel/select-sub-v256.mir

 ...
 ---
 name:            test_sub_v32i8
 # ALL-LABEL: name:  test_sub_v32i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBBYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBBYrr %0, %1
 #

 ...
 ---
 name:            test_sub_v16i16
 # ALL-LABEL: name:  test_sub_v16i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBWYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBWYrr %0, %1
 #

 ...
 ---
 name:            test_sub_v8i32
 # ALL-LABEL: name:  test_sub_v8i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBDYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBDZ256rr %0, %1
 #

 ...
 ---
 name:            test_sub_v4i64
 # ALL-LABEL: name:  test_sub_v4i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # AVX2:            registers:
-# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: '' }
-# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: '' }
+# AVX2-NEXT:         - { id: 0, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 1, class: vr256, preferred-register: "" }
+# AVX2-NEXT:         - { id: 2, class: vr256, preferred-register: "" }
 #
 # AVX512VL:        registers:
-# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512VL-NEXT:     - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512VL-NEXT:     - { id: 2, class: vr256x, preferred-register: "" }
 #
 # AVX512BWVL:      registers:
-# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: '' }
-# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: '' }
+# AVX512BWVL-NEXT:   - { id: 0, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 1, class: vr256x, preferred-register: "" }
+# AVX512BWVL-NEXT:   - { id: 2, class: vr256x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # AVX2:                %2 = VPSUBQYrr %0, %1
 #
 # AVX512VL:            %2 = VPSUBQZ256rr %0, %1
 #

llvm/test/CodeGen/X86/GlobalISel/select-sub-v512.mir

 ...
 ---
 name:            test_sub_v64i8
 # ALL-LABEL: name:  test_sub_v64i8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBBZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<64 x s8>) = COPY %zmm0
     %1(<64 x s8>) = COPY %zmm1
     %2(<64 x s8>) = G_SUB %0, %1
     %zmm0 = COPY %2(<64 x s8>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v32i16
 # ALL-LABEL: name:  test_sub_v32i16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBWZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<32 x s16>) = COPY %zmm0
     %1(<32 x s16>) = COPY %zmm1
     %2(<32 x s16>) = G_SUB %0, %1
     %zmm0 = COPY %2(<32 x s16>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v16i32
 # ALL-LABEL: name:  test_sub_v16i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBDZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<16 x s32>) = COPY %zmm0
     %1(<16 x s32>) = COPY %zmm1
     %2(<16 x s32>) = G_SUB %0, %1
     %zmm0 = COPY %2(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_sub_v8i64
 # ALL-LABEL: name:  test_sub_v8i64
 alignment:       4
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: '' }
-# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: '' }
+# ALL-NEXT:   - { id: 0, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 1, class: vr512, preferred-register: "" }
+# ALL-NEXT:   - { id: 2, class: vr512, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %2 = VPSUBQZrr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %zmm0, %zmm1
 
     %0(<8 x s64>) = COPY %zmm0
     %1(<8 x s64>) = COPY %zmm1
     %2(<8 x s64>) = G_SUB %0, %1
     %zmm0 = COPY %2(<8 x s64>)
     RET 0, implicit %zmm0
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-sub.mir

--- |
   }
 
 ...
 ---
 name:            test_sub_i64
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr64, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr64, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr64, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %rdi
 # ALL-NEXT: %1 = COPY %rsi
 # ALL-NEXT: %2 = SUB64rr %0, %1
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi, %esi
 
     %0(s64) = COPY %rdi
     %1(s64) = COPY %rsi
     %2(s64) = G_SUB %0, %1
     %rax = COPY %2(s64)
 
 ...
 
 ---
 name:            test_sub_i32
 legalized:       true
 regBankSelected: true
 # ALL:      registers:
-# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: '' }
-# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: '' }
+# ALL-NEXT:  - { id: 0, class: gr32, preferred-register: "" }
+# ALL-NEXT:  - { id: 1, class: gr32, preferred-register: "" }
+# ALL-NEXT:  - { id: 2, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # ALL:      %0 = COPY %edi
 # ALL-NEXT: %1 = COPY %esi
 # ALL-NEXT: %2 = SUB32rr %0, %1
 body:             |

 ---
 name:            test_sub_float
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr32, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr32, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr32, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 0, class: fr32x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 1, class: fr32x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 2, class: fr32x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = SUBSSrr %0, %1
 # AVX-NEXT:     %2 = VSUBSSrr %0, %1

 ---
 name:            test_sub_double
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: '' }
-# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: '' }
-# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: '' }
+# NO_AVX512F-NEXT:  - { id: 0, class: fr64, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 1, class: fr64, preferred-register: "" }
+# NO_AVX512F-NEXT:  - { id: 2, class: fr64, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 0, class: fr64x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 1, class: fr64x, preferred-register: "" }
+# AVX512ALL-NEXT:  - { id: 2, class: fr64x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:          %0 = COPY %xmm0
 # ALL-NEXT:     %1 = COPY %xmm1
 # SSE-NEXT:     %2 = SUBSDrr %0, %1
 # AVX-NEXT:     %2 = VSUBSDrr %0, %1

 ---
 name:            test_sub_v4i32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = PSUBDrr %0, %1
 # AVX-NEXT:      %2 = VPSUBDrr %0, %1

 ---
 name:            test_sub_v4f32
 alignment:       4
 legalized:       true
 regBankSelected: true
 selected:        false
 tracksRegLiveness: true
 # ALL: registers:
-# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: '' }
-# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: '' }
-# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: '' }
+# NO_AVX512VL-NEXT:  - { id: 0, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 1, class: vr128, preferred-register: "" }
+# NO_AVX512VL-NEXT:  - { id: 2, class: vr128, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 0, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 1, class: vr128x, preferred-register: "" }
+# AVX512VL-NEXT:  - { id: 2, class: vr128x, preferred-register: "" }
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
   - { id: 2, class: vecr }
 # ALL:           %0 = COPY %xmm0
 # ALL-NEXT:      %1 = COPY %xmm1
 # SSE-NEXT:      %2 = SUBPSrr %0, %1
 # AVX-NEXT:      %2 = VSUBPSrr %0, %1

llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir

 ...
 ---
 name:            trunc_i32toi1
 # CHECK-LABEL: name:  trunc_i32toi1
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s1) = G_TRUNC %0(s32)
     %al = COPY %1(s1)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i32toi8
 # CHECK-LABEL: name:  trunc_i32toi8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s8) = G_TRUNC %0(s32)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i32toi16
 # CHECK-LABEL: name:  trunc_i32toi16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr32, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %edi
 # CHECK-NEXT:     %1 = COPY %0.sub_16bit
 # CHECK-NEXT:     %ax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %ax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s16) = G_TRUNC %0(s32)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            trunc_i64toi8
 # CHECK-LABEL: name:  trunc_i64toi8
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64_with_sub_8bit, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr64_with_sub_8bit, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr8, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_8bit
 # CHECK-NEXT:     %al = COPY %1
 # CHECK-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(s64) = COPY %rdi
     %1(s8) = G_TRUNC %0(s64)
     %al = COPY %1(s8)
     RET 0, implicit %al
 
 ...
 ---
 name:            trunc_i64toi16
 # CHECK-LABEL: name:  trunc_i64toi16
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr16, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_16bit
 # CHECK-NEXT:     %ax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %ax
 body:             |
   bb.1 (%ir-block.0):
     liveins: %rdi
 
     %0(s64) = COPY %rdi
     %1(s16) = G_TRUNC %0(s64)
     %ax = COPY %1(s16)
     RET 0, implicit %ax
 
 ...
 ---
 name:            trunc_i64toi32
 # CHECK-LABEL: name:  trunc_i64toi32
 alignment:       4
 legalized:       true
 regBankSelected: true
 # CHECK:      registers:
-# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: '' }
-# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: '' }
+# CHECK-NEXT:   - { id: 0, class: gr64, preferred-register: "" }
+# CHECK-NEXT:   - { id: 1, class: gr32, preferred-register: "" }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 # CHECK:          %0 = COPY %rdi
 # CHECK-NEXT:     %1 = COPY %0.sub_32bit
 # CHECK-NEXT:     %eax = COPY %1
 # CHECK-NEXT:     RET 0, implicit %eax
 body:             |

llvm/test/CodeGen/X86/stack-protector-remarks.ll

 
 ; RUN: llc %s -mtriple=x86_64-unknown-unknown -o /dev/null -pass-remarks-output=%t.yaml
 ; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML
 ; YAML:      --- !Passed
 ; YAML-NEXT: Pass:            stack-protector
 ; YAML-NEXT: Name:            StackProtectorRequested
 ; YAML-NEXT: Function:        attribute_ssp
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'Stack protection applied to function '
+; YAML-NEXT:   - String:          "Stack protection applied to function "
 ; YAML-NEXT:   - Function:        attribute_ssp
-; YAML-NEXT:   - String:          ' due to a function attribute or command-line switch'
+; YAML-NEXT:   - String:          " due to a function attribute or command-line switch"
 ; YAML-NEXT: ...
 
 define void @nossp() ssp {
   ret void
 }
 
 define void @attribute_ssp() sspreq {
   ret void

llvm/test/CodeGen/X86/virtual-registers-cleared-in-machine-functions-liveins.ll

 ; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after machine-scheduler %s | FileCheck %s --check-prefix=PRE-RA
 ; RUN: llc -mtriple=x86_64-unknown-unknown -o - -stop-after prologepilog %s | FileCheck %s --check-prefix=POST-RA
 
-; This test verifies that the virtual register references in machine function's
+; This test verifies that the virtual register references in machine function"s
 ; liveins are cleared after register allocation.
 
 define i32 @test(i32 %a, i32 %b) {
 body:
   %c = mul i32 %a, %b
   ret i32 %c
 }
 
 ; PRE-RA: liveins:
-; PRE-RA-NEXT: - { reg: '%edi', virtual-reg: '%0' }
-; PRE-RA-NEXT: - { reg: '%esi', virtual-reg: '%1' }
+; PRE-RA-NEXT: - { reg: "%edi", virtual-reg: "%0" }
+; PRE-RA-NEXT: - { reg: "%esi", virtual-reg: "%1" }
 
 ; POST-RA: liveins:
-; POST-RA-NEXT: - { reg: '%edi', virtual-reg: '' }
-; POST-RA-NEXT: - { reg: '%esi', virtual-reg: '' }
+; POST-RA-NEXT: - { reg: "%edi", virtual-reg: "" }
+; POST-RA-NEXT: - { reg: "%esi", virtual-reg: "" }

llvm/test/DebugInfo/PDB/Inputs/one-symbol.yaml

 ---
 DbiStream:
   Modules:
     - Module:          one-symbol.yaml
       Modi:
         Records:
           - Kind:            S_OBJNAME
             ObjNameSym:
               Signature:       0
-              ObjectName:      'c:\foo\one-symbol.yaml'
+              ObjectName:      "c:\\foo\\one-symbol.yaml"
 ...

llvm/test/DebugInfo/PDB/pdb-yaml-symbols.test

 YAML:   VerHeader:       V70
 YAML:   Age:             1
 YAML:   BuildNumber:     35840
 YAML:   PdbDllVersion:   31101
 YAML:   PdbDllRbld:      0
 YAML:   Flags:           1
 YAML:   MachineType:     x86
 YAML:   Modules:
-YAML:     - Module:          'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj'
-YAML:       ObjFile:         'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj'
+YAML:     - Module:          "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj"
+YAML:       ObjFile:         "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj"
 YAML:       Modi:
 YAML:         Signature:       4
 YAML:         Records:
 YAML:           - Kind:            S_OBJNAME
 YAML:             ObjNameSym:
 YAML:               Signature:       0
-YAML:               ObjectName:      'd:\src\llvm\test\DebugInfo\PDB\Inputs\empty.obj'
+YAML:               ObjectName:      "d:\\src\\llvm\\test\\DebugInfo\\PDB\\Inputs\\empty.obj"
 YAML:           - Kind:            S_COMPILE3
 YAML:             Compile3Sym:
 YAML:               Flags:           [ SecurityChecks ]
 YAML:               Machine:         Pentium3
 YAML:               FrontendMajor:   18
 YAML:               FrontendMinor:   0
 YAML:               FrontendBuild:   31101
 YAML:               FrontendQFE:     0
 YAML:               BackendMajor:    18
 YAML:               BackendMinor:    0
 YAML:               BackendBuild:    31101
 YAML:               BackendQFE:      0
-YAML:               Version:         'Microsoft (R) Optimizing Compiler'
+YAML:               Version:         "Microsoft (R) Optimizing Compiler"
 YAML:           - Kind:            S_GPROC32
 YAML:             ProcSym:
 YAML:               PtrParent:       0
 YAML:               PtrEnd:          196
 YAML:               PtrNext:         0
 YAML:               CodeSize:        10
 YAML:               DbgStart:        3
 YAML:               DbgEnd:          8

 YAML:               OffsetOfExceptionHandler: 0
 YAML:               SectionIdOfExceptionHandler: 0
 YAML:               Flags:           [ AsynchronousExceptionHandling, OptimizedForSpeed ]
 YAML:           - Kind:            S_END
 YAML:             ScopeEndSym:
 YAML:           - Kind:            S_BUILDINFO
 YAML:             BuildInfoSym:
 YAML:               BuildId:         4110
-YAML:     - Module:          '* Linker *'
-YAML:       ObjFile:         ''
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+YAML:       ObjFile:         ""
 YAML:       Modi:
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 YAML:         Records:
 YAML:           - Kind:            S_OBJNAME
 YAML:             ObjNameSym:
 YAML:               Signature:       0
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+YAML:                 - "C:\\Program Files (x86)\\Microsoft Visual Studio 12.0\\VC\\BIN\\link.exe"
 YAML:                 - pdb
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 No newline at end of file

llvm/test/DebugInfo/PDB/pdbdump-debug-subsections.test

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llvm/test/DebugInfo/PDB/pdbdump-source-names.test

 # Test that we can write source file names to PDBs and read them back.
 # Because the subsection the file names are stored in is 4-byte
 # aligned, there is a possibility of misaligning the file names. This
 # will cause them to be read back empty or truncated.  To guard
 # against this, we test with two different lengths of file name data
 # that differ by one byte, so that at least one of those will only
 # pass if alignment is implemented correctly.
 
 RUN: llvm-pdbutil yaml2pdb -pdb=%T/source-names-1.pdb %p/Inputs/source-names-1.yaml
 RUN: llvm-pdbutil pdb2yaml -module-files %T/source-names-1.pdb \
 RUN:     | FileCheck -check-prefix=CHECK1 %s
 RUN: llvm-pdbutil yaml2pdb -pdb=%T/source-names-2.pdb %p/Inputs/source-names-2.yaml
 RUN: llvm-pdbutil pdb2yaml -module-files %T/source-names-2.pdb \
 RUN:     | FileCheck -check-prefix=CHECK2 %s
 
 CHECK1: SourceFiles:
-CHECK1: 'C:\src\test.c'
+CHECK1: "C:\\src\\test.c"
 
 CHECK2: SourceFiles:
-CHECK2: 'C:\src\test.cc'
+CHECK2: "C:\\src\\test.cc"

llvm/test/DebugInfo/PDB/pdbdump-yaml-types.test

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-YAML:             Name:            ''
+YAML:             Name:            ""
 YAML:     - Kind:            LF_FIELDLIST
 YAML:       FieldList:       
 YAML:         - Kind:            LF_NESTTYPE
 YAML:           NestedType:      
 YAML:             Type:            4142
 YAML:             Name:            type_e
 YAML:         - Kind:            LF_METHOD
 YAML:           OverloadedMethod: 

 YAML:             Type:            4146
 YAML:             FieldOffset:     52
 YAML:             Name:            resource_name
 YAML:     - Kind:            LF_STRUCTURE
 YAML:       Class:           
 YAML:         MemberCount:     19
 YAML:         Options:         [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ]
 YAML:         FieldList:       4153
-YAML:         Name:            '__vc_attributes::moduleAttribute'
-YAML:         UniqueName:      '.?AUmoduleAttribute@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::moduleAttribute"
+YAML:         UniqueName:      ".?AUmoduleAttribute@__vc_attributes@@"
 YAML:         DerivationList:  0
 YAML:         VTableShape:     0
 YAML:         Size:            56
 YAML:     - Kind:            LF_FIELDLIST
 YAML:       FieldList:       
 YAML:         - Kind:            LF_ENUMERATE
 YAML:           Enumerator:      
 YAML:             Attrs:           3

 YAML:             Attrs:           3
 YAML:             Value:           4161535
 YAML:             Name:            eAnyIDLUsage
 YAML:     - Kind:            LF_ENUM
 YAML:       Enum:            
 YAML:         NumEnumerators:  30
 YAML:         Options:         [ None, Nested, HasUniqueName ]
 YAML:         FieldList:       4155
-YAML:         Name:            '__vc_attributes::helper_attributes::usageAttribute::usage_e'
-YAML:         UniqueName:      '.?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::usageAttribute::usage_e"
+YAML:         UniqueName:      ".?AW4usage_e@usageAttribute@helper_attributes@__vc_attributes@@"
 YAML:         UnderlyingType:  116
 YAML:     - Kind:            LF_STRUCTURE
 YAML:       Class:           
 YAML:         MemberCount:     0
 YAML:         Options:         [ None, ForwardReference, HasUniqueName ]
 YAML:         FieldList:       0
-YAML:         Name:            '__vc_attributes::helper_attributes::usageAttribute'
-YAML:         UniqueName:      '.?AUusageAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::usageAttribute"
+YAML:         UniqueName:      ".?AUusageAttribute@helper_attributes@__vc_attributes@@"
 YAML:         DerivationList:  0
 YAML:         VTableShape:     0
 YAML:         Size:            0
 YAML:     - Kind:            LF_POINTER
 YAML:       Pointer:         
 YAML:         ReferentType:    4157
 YAML:         Attrs:           33802
 YAML:     - Kind:            LF_ARGLIST

 YAML:             Type:            117
 YAML:             FieldOffset:     0
 YAML:             Name:            value
 YAML:     - Kind:            LF_STRUCTURE
 YAML:       Class:           
 YAML:         MemberCount:     3
 YAML:         Options:         [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ]
 YAML:         FieldList:       4161
-YAML:         Name:            '__vc_attributes::helper_attributes::usageAttribute'
-YAML:         UniqueName:      '.?AUusageAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::usageAttribute"
+YAML:         UniqueName:      ".?AUusageAttribute@helper_attributes@__vc_attributes@@"
 YAML:         DerivationList:  0
 YAML:         VTableShape:     0
 YAML:         Size:            4
 YAML:     - Kind:            LF_FIELDLIST
 YAML:       FieldList:       
 YAML:         - Kind:            LF_ENUMERATE
 YAML:           Enumerator:      
 YAML:             Attrs:           3

 YAML:             Attrs:           3
 YAML:             Value:           3
 YAML:             Name:            eDouble
 YAML:     - Kind:            LF_ENUM
 YAML:       Enum:            
 YAML:         NumEnumerators:  4
 YAML:         Options:         [ None, Nested, HasUniqueName ]
 YAML:         FieldList:       4163
-YAML:         Name:            '__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e'
-YAML:         UniqueName:      '.?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::v1_alttypeAttribute::type_e"
+YAML:         UniqueName:      ".?AW4type_e@v1_alttypeAttribute@helper_attributes@__vc_attributes@@"
 YAML:         UnderlyingType:  116
 YAML:     - Kind:            LF_STRUCTURE
 YAML:       Class:           
 YAML:         MemberCount:     0
 YAML:         Options:         [ None, ForwardReference, HasUniqueName ]
 YAML:         FieldList:       0
-YAML:         Name:            '__vc_attributes::helper_attributes::v1_alttypeAttribute'
-YAML:         UniqueName:      '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::v1_alttypeAttribute"
+YAML:         UniqueName:      ".?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@"
 YAML:         DerivationList:  0
 YAML:         VTableShape:     0
 YAML:         Size:            0
 YAML:     - Kind:            LF_POINTER
 YAML:       Pointer:         
 YAML:         ReferentType:    4165
 YAML:         Attrs:           33802
 YAML:     - Kind:            LF_ARGLIST

 YAML:             Type:            4164
 YAML:             FieldOffset:     0
 YAML:             Name:            type
 YAML:     - Kind:            LF_STRUCTURE
 YAML:       Class:           
 YAML:         MemberCount:     3
 YAML:         Options:         [ None, HasConstructorOrDestructor, ContainsNestedClass, HasUniqueName ]
 YAML:         FieldList:       4169
-YAML:         Name:            '__vc_attributes::helper_attributes::v1_alttypeAttribute'
-YAML:         UniqueName:      '.?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@'
+YAML:         Name:            "__vc_attributes::helper_attributes::v1_alttypeAttribute"
+YAML:         UniqueName:      ".?AUv1_alttypeAttribute@helper_attributes@__vc_attributes@@"
 YAML:         DerivationList:  0
 YAML:         VTableShape:     0
 YAML:         Size:            4
 YAML: ...

llvm/test/DebugInfo/PDB/pdbdump-yaml.test

 ; YAML-NEXT:   - Stream: [ 10 ]
 ; YAML-NEXT:   - Stream: [ 15 ]
 ; YAML-NEXT:   - Stream: [ 6 ]
 ; YAML-NEXT:   - Stream: [ 16 ]
 ; YAML-NEXT:   - Stream: [ 7 ]
 ; YAML-NEXT:   - Stream: [ 21 ]
 ; YAML-NEXT:   - Stream: [ 22 ]
 ; YAML-NEXT: StringTable:
-; YAML-NEXT:   - 'd:\src\llvm\test\debuginfo\pdb\inputs\predefined c++ attributes (compiler internal)'
-; YAML-NEXT:   - 'd:\src\llvm\test\debuginfo\pdb\inputs\empty.cpp'
-; YAML-NEXT:   - '$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = '
+; YAML-NEXT:   - "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\predefined c++ attributes (compiler internal)"
+; YAML-NEXT:   - "d:\\src\\llvm\\test\\debuginfo\\pdb\\inputs\\empty.cpp"
+; YAML-NEXT:   - "$T0 $ebp = $eip $T0 4 + ^ = $ebp $T0 ^ = $esp $T0 8 + = "
 ; YAML-NEXT: PdbStream:
 ; YAML-NEXT:   Age:             1
-; YAML-NEXT:   Guid:            '{0B355641-86A0-A249-896F-9988FAE52FF0}'
+; YAML-NEXT:   Guid:            "{0B355641-86A0-A249-896F-9988FAE52FF0}"
 ; YAML-NEXT:   Signature:       1424295906
 ; YAML-NEXT:   Features:        [ VC110 ]
 ; YAML-NEXT:   Version:         VC70
 ; YAML-NEXT: ...
 
 ; NO-HEADERS: ---
 ; NO-HEADERS-NOT: MSF:
 ; NO-HEADERS-NOT:   SuperBlock:
 ; NO-HEADERS: ...
 No newline at end of file

llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks-with-hotness.ll

 
 ; YAML: --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Hotness:         300
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          tinkywinky
-; YAML-NEXT:   - String:          ' inlined into '
+; YAML-NEXT:   - String:          " inlined into "
 ; YAML-NEXT:   - Caller:          main
 ; YAML-NEXT: ...
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-scei-ps4"
 
 declare i32 @patatino()
 

llvm/test/LTO/Resolution/X86/diagnostic-handler-remarks.ll

 ; RUN: llvm-as < %s >%t.bc
 
 ; RUN: rm -f %t.yaml
 ; RUN: llvm-lto2 run -pass-remarks-output=%t.yaml \
 ; RUN:           -r %t.bc,tinkywinky,p \
 ; RUN:           -r %t.bc,patatino,px \
 ; RUN:           -r %t.bc,main,px -o %t.o %t.bc
 ; RUN: cat %t.yaml | FileCheck %s -check-prefix=YAML
 
 ; YAML:      --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          tinkywinky
-; YAML-NEXT:   - String:          ' inlined into '
+; YAML-NEXT:   - String:          " inlined into "
 ; YAML-NEXT:   - Caller:          main
 ; YAML-NEXT: ...
 
 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-scei-ps4"
 
 declare i32 @patatino()
 

llvm/test/LTO/X86/diagnostic-handler-remarks-with-hotness.ll

 
 ; YAML:      --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Hotness:         300
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          foo
-; YAML-NEXT:   - String:          ' inlined into '
+; YAML-NEXT:   - String:          " inlined into "
 ; YAML-NEXT:   - Caller:          main
 ; YAML-NEXT: ...
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-darwin"
 
 declare i32 @bar()
 

llvm/test/LTO/X86/diagnostic-handler-remarks.ll

 ; RUN: llvm-as < %s >%t.bc
-; PR21108: Diagnostic handlers get pass remarks, even if they're not enabled.
+; PR21108: Diagnostic handlers get pass remarks, even if they"re not enabled.
 
 ; Confirm that there are -pass-remarks.
 ; RUN: llvm-lto -pass-remarks=inline \
 ; RUN:          -exported-symbol _func2 -pass-remarks-analysis=loop-vectorize \
 ; RUN:          -exported-symbol _main -o %t.o %t.bc 2>&1 | \
 ; RUN:     FileCheck %s -allow-empty -check-prefix=REMARKS
 ; RUN: llvm-nm %t.o | FileCheck %s -check-prefix NM
 

 ; NM: main
 
 ; YAML:      --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: Function:        main
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee:          foo
-; YAML-NEXT:   - String:          ' inlined into '
+; YAML-NEXT:   - String:          " inlined into "
 ; YAML-NEXT:   - Caller:          main
 ; YAML-NEXT: ...
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-darwin"
 
 declare i32 @bar()
 

llvm/test/Object/obj2yaml-coff-section-aux-symbol.test

 RUN: yaml2obj %p/Inputs/COFF/section-aux-symbol.yaml | obj2yaml | FileCheck %s --check-prefix COFF-I386
 
 COFF-I386:     sections:
 COFF-I386-NEXT:  - Name:            .CRT
 COFF-I386:     symbols:
-COFF-I386:       - Name:            '.CRT$XCAA'
+COFF-I386:       - Name:            ".CRT$XCAA"
 COFF-I386-NEXT:    Value:           4
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 1
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XIAA'
+COFF-I386:       - Name:            ".CRT$XIAA"
 COFF-I386-NEXT:    Value:           16
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 1
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XLD'
+COFF-I386:       - Name:            ".CRT$XLD"
 COFF-I386-NEXT:    Value:           36
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 1
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XLC'
+COFF-I386:       - Name:            ".CRT$XLC"
 COFF-I386-NEXT:    Value:           32
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 1
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XDZ'
+COFF-I386:       - Name:            ".CRT$XDZ"
 COFF-I386-NEXT:    Value:           48
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XDA'
+COFF-I386:       - Name:            ".CRT$XDA"
 COFF-I386-NEXT:    Value:           44
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XLZ'
+COFF-I386:       - Name:            ".CRT$XLZ"
 COFF-I386-NEXT:    Value:           40
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XLA'
+COFF-I386:       - Name:            ".CRT$XLA"
 COFF-I386-NEXT:    Value:           28
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XIC'
+COFF-I386:       - Name:            ".CRT$XIC"
 COFF-I386-NEXT:    Value:           20
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 1
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XCZ'
+COFF-I386:       - Name:            ".CRT$XCZ"
 COFF-I386-NEXT:    Value:           8
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XCA'
+COFF-I386:       - Name:            ".CRT$XCA"
 COFF-I386-NEXT:    Value:           0
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XIZ'
+COFF-I386:       - Name:            ".CRT$XIZ"
 COFF-I386-NEXT:    Value:           24
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0
-COFF-I386:       - Name:            '.CRT$XIA'
+COFF-I386:       - Name:            ".CRT$XIA"
 COFF-I386-NEXT:    Value:           12
 COFF-I386:         StorageClass:    IMAGE_SYM_CLASS_STATIC
 COFF-I386-NEXT:    SectionDefinition:
 COFF-I386-NEXT:      Length:          4
 COFF-I386-NEXT:      NumberOfRelocations: 0
 COFF-I386-NEXT:      NumberOfLinenumbers: 0

llvm/test/Object/obj2yaml-invalid-reloc.test

 CHECK-NEXT:     Content:         4833C0C390
 CHECK-NEXT:   - Name:            .rela.text
 CHECK-NEXT:     Type:            SHT_RELA
 CHECK-NEXT:     Link:            .symtab
 CHECK-NEXT:     AddressAlign:    0x0000000000000008
 CHECK-NEXT:     Info:            .text
 CHECK-NEXT:     Relocations:
 CHECK-NEXT:       - Offset:          0x0000000000000000
-CHECK-NEXT:         Symbol:          ''
+CHECK-NEXT:         Symbol:          ""
 CHECK-NEXT:         Type:            R_X86_64_NONE
 CHECK-NEXT: Symbols:
 CHECK-NEXT:   Local:
 CHECK-NEXT:     - Name:            rb_ary_new_capa
 CHECK-NEXT:       Type:            STT_FUNC
 CHECK-NEXT:       Section:         .text
 CHECK-NEXT:       Size:            0x0000000000000005
 CHECK-NEXT:   Global:
 CHECK-NEXT:     - Name:            __dtraceenabled_ruby___array-create
-CHECK-NEXT:     - Name:            '$dtrace1316529.rb_ary_new_capa'
+CHECK-NEXT:     - Name:            "$dtrace1316529.rb_ary_new_capa"
 CHECK-NEXT:       Type:            STT_FUNC
 CHECK-NEXT:       Section:         .text
 CHECK-NEXT:       Size:            0x0000000000000005
 CHECK-NEXT:       Visibility:      STV_HIDDEN

llvm/test/Object/obj2yaml.test

 COFF-X86-64-NEXT:         SymbolName: SomeOtherFunction
 COFF-X86-64-NEXT:         Type: IMAGE_REL_AMD64_REL32
 
 COFF-X86-64:        - Name: .data
 COFF-X86-64-NEXT:     Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ]
 COFF-X86-64-NEXT:     Alignment: 1
 COFF-X86-64-NEXT:     SectionData: 48656C6C6F20576F726C642100
 
-COFF-X86-64:        - Name: '.CRT$XCU'
+COFF-X86-64:        - Name: ".CRT$XCU"
 COFF-X86-64-NEXT:     Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ ]
 COFF-X86-64-NEXT:     Alignment: 8
-COFF-X86-64-NEXT:     SectionData:  '0000000000000000'
+COFF-X86-64-NEXT:     SectionData:  "0000000000000000"
 
 COFF-X86-64:     Relocations:
 COFF-X86-64-NEXT:       - VirtualAddress: 0
-COFF-X86-64-NEXT:         SymbolName: '??__Ex@@YAXXZ'
+COFF-X86-64-NEXT:         SymbolName: "??__Ex@@YAXXZ"
 COFF-X86-64-NEXT:         Type: IMAGE_REL_AMD64_ADDR64
 
 COFF-X86-64: symbols:
 COFF-X86-64-NEXT:   - Name: .text
 COFF-X86-64-NEXT:     Value: 0
 COFF-X86-64-NEXT:     SectionNumber: 1
 COFF-X86-64-NEXT:     SimpleType: IMAGE_SYM_TYPE_NULL
 COFF-X86-64-NEXT:     ComplexType: IMAGE_SYM_DTYPE_NULL

 
 COFF-X86-64:        - Name: SomeOtherFunction
 COFF-X86-64-NEXT:     Value: 0
 COFF-X86-64-NEXT:     SectionNumber: 0
 COFF-X86-64-NEXT:     SimpleType: IMAGE_SYM_TYPE_NULL
 COFF-X86-64-NEXT:     ComplexType: IMAGE_SYM_DTYPE_NULL
 COFF-X86-64-NEXT:     StorageClass: IMAGE_SYM_CLASS_EXTERNAL
 
-COFF-X86-64:        - Name: '??__Ex@@YAXXZ'
+COFF-X86-64:        - Name: "??__Ex@@YAXXZ"
 COFF-X86-64-NEXT:     Value: 0
 COFF-X86-64-NEXT:     SectionNumber: 3
 COFF-X86-64-NEXT:     SimpleType: IMAGE_SYM_TYPE_NULL
 COFF-X86-64-NEXT:     ComplexType: IMAGE_SYM_DTYPE_FUNCTION
 COFF-X86-64-NEXT:     StorageClass: IMAGE_SYM_CLASS_STATIC
 
 ELF-MIPSEL:      FileHeader:
 ELF-MIPSEL-NEXT:   Class:           ELFCLASS32

 ELF-MIPSEL-NEXT:     Relocations:
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000000
 ELF-MIPSEL-NEXT:         Symbol:          _gp_disp
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_HI16
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000004
 ELF-MIPSEL-NEXT:         Symbol:          _gp_disp
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_LO16
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000018
-ELF-MIPSEL-NEXT:         Symbol:          '$.str'
+ELF-MIPSEL-NEXT:         Symbol:          "$.str"
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_GOT16
 ELF-MIPSEL-NEXT:       - Offset:          0x000000000000001C
-ELF-MIPSEL-NEXT:         Symbol:          '$.str'
+ELF-MIPSEL-NEXT:         Symbol:          "$.str"
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_LO16
 ELF-MIPSEL-NEXT:       - Offset:          0x0000000000000020
 ELF-MIPSEL-NEXT:         Symbol:          puts
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_CALL16
 ELF-MIPSEL-NEXT:       - Offset:          0x000000000000002C
 ELF-MIPSEL-NEXT:         Symbol:          SomeOtherFunction
 ELF-MIPSEL-NEXT:         Type:            R_MIPS_CALL16
 ELF-MIPSEL-NEXT:   - Name:            .data
 ELF-MIPSEL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000004
-ELF-MIPSEL-NEXT:     Content:         ''
+ELF-MIPSEL-NEXT:     Content:         ""
 ELF-MIPSEL-NEXT:   - Name:            .bss
 ELF-MIPSEL-NEXT:     Type:            SHT_NOBITS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000004
 ELF-MIPSEL-NEXT:     Size:            0x0000000000000004
 ELF-MIPSEL-NEXT:   - Name:            .mdebug.abi32
 ELF-MIPSEL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000001
-ELF-MIPSEL-NEXT:     Content:         ''
+ELF-MIPSEL-NEXT:     Content:         ""
 ELF-MIPSEL-NEXT:   - Name:            .rodata.str1.1
 ELF-MIPSEL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_ALLOC, SHF_MERGE, SHF_STRINGS ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000001
 ELF-MIPSEL-NEXT:     Content:         48656C6C6F20576F726C640A00
 ELF-MIPSEL-NEXT:   - Name:            .reginfo
 ELF-MIPSEL-NEXT:     Type:            SHT_MIPS_REGINFO
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_ALLOC ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000001
-ELF-MIPSEL-NEXT:     Content:         '000000000000000000000000000000000000000000000000'
+ELF-MIPSEL-NEXT:     Content:         "000000000000000000000000000000000000000000000000"
 ELF-MIPSEL-NEXT:   - Name:            .MIPS.abiflags
 ELF-MIPSEL-NEXT:     Type:            SHT_MIPS_ABIFLAGS
 ELF-MIPSEL-NEXT:     Flags:           [ SHF_ALLOC ]
 ELF-MIPSEL-NEXT:     AddressAlign:    0x0000000000000008
 ELF-MIPSEL-NEXT:     ISA:             MIPS32
 ELF-MIPSEL-NEXT:     ISARevision:     0x01
 ELF-MIPSEL-NEXT:     FpABI:           FP_DOUBLE
 ELF-MIPSEL-NEXT:     GPRSize:         REG_32
 ELF-MIPSEL-NEXT:     CPR1Size:        REG_32
 ELF-MIPSEL-NEXT:     Flags1:          [ ODDSPREG ]
 ELF-MIPSEL-NEXT: Symbols:
 ELF-MIPSEL-NEXT:   Local:
 ELF-MIPSEL-NEXT:     - Name:            trivial.ll
 ELF-MIPSEL-NEXT:       Type:            STT_FILE
-ELF-MIPSEL-NEXT:     - Name:            '$.str'
+ELF-MIPSEL-NEXT:     - Name:            "$.str"
 ELF-MIPSEL-NEXT:       Type:            STT_OBJECT
 ELF-MIPSEL-NEXT:       Section:         .rodata.str1.1
 ELF-MIPSEL-NEXT:       Size:            0x000000000000000D
 ELF-MIPSEL-NEXT:     - Type:            STT_SECTION
 ELF-MIPSEL-NEXT:       Section:         .text
 ELF-MIPSEL-NEXT:     - Type:            STT_SECTION
 ELF-MIPSEL-NEXT:       Section:         .data
 ELF-MIPSEL-NEXT:     - Type:            STT_SECTION

 ELF-MIPS64EL-NEXT:   Type:            ET_REL
 ELF-MIPS64EL-NEXT:   Machine:         EM_MIPS
 ELF-MIPS64EL-NEXT:   Flags:           [ EF_MIPS_ARCH_3 ]
 ELF-MIPS64EL-NEXT: Sections:
 ELF-MIPS64EL-NEXT:   - Name:            .text
 ELF-MIPS64EL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000010
-ELF-MIPS64EL-NEXT:     Content:         ''
+ELF-MIPS64EL-NEXT:     Content:         ""
 ELF-MIPS64EL-NEXT:   - Name:            .data
 ELF-MIPS64EL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000010
-ELF-MIPS64EL-NEXT:     Content:         '00000000000000000000000000000000'
+ELF-MIPS64EL-NEXT:     Content:         "00000000000000000000000000000000"
 ELF-MIPS64EL-NEXT:   - Name:            .rela.data
 ELF-MIPS64EL-NEXT:     Type:            SHT_RELA
 ELF-MIPS64EL-NEXT:     Link:            .symtab
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000008
 ELF-MIPS64EL-NEXT:     Info:            .data
 ELF-MIPS64EL-NEXT:     Relocations:
 ELF-MIPS64EL-NEXT:       - Offset:          0
 ELF-MIPS64EL-NEXT:         Symbol:          zed
 ELF-MIPS64EL-NEXT:         Type:            R_MIPS_64
 ELF-MIPS64EL-NEXT:   - Name:            .bss
 ELF-MIPS64EL-NEXT:     Type:            SHT_NOBITS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000010
 ELF-MIPS64EL-NEXT:   - Name:            .MIPS.options
 ELF-MIPS64EL-NEXT:     Type:            SHT_MIPS_OPTIONS
 ELF-MIPS64EL-NEXT:     Flags:           [ SHF_ALLOC, SHF_MIPS_NOSTRIP ]
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000008
-ELF-MIPS64EL-NEXT:     Content:         '01280000000000000000000000000000000000000000000000000000000000000000000000000000'
+ELF-MIPS64EL-NEXT:     Content:         "01280000000000000000000000000000000000000000000000000000000000000000000000000000"
 ELF-MIPS64EL-NEXT:   - Name:            .pdr
 ELF-MIPS64EL-NEXT:     Type:            SHT_PROGBITS
 ELF-MIPS64EL-NEXT:     AddressAlign:    0x0000000000000004
-ELF-MIPS64EL-NEXT:     Content:         ''
+ELF-MIPS64EL-NEXT:     Content:         ""
 ELF-MIPS64EL-NEXT: Symbols:
 ELF-MIPS64EL-NEXT:   Local:
 ELF-MIPS64EL-NEXT:     - Type:            STT_SECTION
 ELF-MIPS64EL-NEXT:       Section:         .text
 ELF-MIPS64EL-NEXT:     - Type:            STT_SECTION
 ELF-MIPS64EL-NEXT:       Section:         .data
 ELF-MIPS64EL-NEXT:     - Type:            STT_SECTION
 ELF-MIPS64EL-NEXT:       Section:         .bss

 ELF-X86-64-NEXT:     Flags:           [ SHF_ALLOC, SHF_MERGE, SHF_STRINGS ]
 ELF-X86-64-NEXT:     Address:         0x0000000000000026
 ELF-X86-64-NEXT:     AddressAlign:    0x0000000000000001
 ELF-X86-64-NEXT:     Content:         48656C6C6F20576F726C642100
 ELF-X86-64-NEXT:   - Name:            .note.GNU-stack
 ELF-X86-64-NEXT:     Type:            SHT_PROGBITS
 ELF-X86-64-NEXT:     Address:         0x0000000000000033
 ELF-X86-64-NEXT:     AddressAlign:    0x0000000000000001
-ELF-X86-64-NEXT:     Content:         ''
+ELF-X86-64-NEXT:     Content:         ""
 ELF-X86-64-NEXT:   - Name:            .rela.text
 ELF-X86-64-NEXT:     Type:            SHT_RELA
 ELF-X86-64-NEXT:     Address:         0x0000000000000038
 ELF-X86-64-NEXT:     Link:            .symtab
 ELF-X86-64-NEXT:     AddressAlign:    0x0000000000000008
 ELF-X86-64-NEXT:     Info:            .text
 ELF-X86-64-NEXT:     Relocations:
 ELF-X86-64-NEXT:       - Offset:          0x000000000000000D
-ELF-X86-64-NEXT:         Symbol:          ''
+ELF-X86-64-NEXT:         Symbol:          ""
 ELF-X86-64-NEXT:         Type:            R_X86_64_32S
 ELF-X86-64-NEXT:       - Offset:          0x0000000000000012
 ELF-X86-64-NEXT:         Symbol:          puts
 ELF-X86-64-NEXT:         Type:            R_X86_64_PC32
 ELF-X86-64-NEXT:         Addend:          -4
 ELF-X86-64-NEXT:       - Offset:          0x0000000000000019
 ELF-X86-64-NEXT:         Symbol:          SomeOtherFunction
 ELF-X86-64-NEXT:         Type:            R_X86_64_PC32

 ELF-AVR-NEXT:     Flags:           [ SHF_ALLOC, SHF_EXECINSTR ]
 ELF-AVR-NEXT:     AddressAlign:    0x0000000000000002
 ELF-AVR-NEXT:     Content:         C20E0895
 ELF-AVR-NEXT:   - Name:            .data
 ELF-AVR-NEXT:     Type:            SHT_PROGBITS
 ELF-AVR-NEXT:     Flags:           [ SHF_WRITE, SHF_ALLOC ]
 ELF-AVR-NEXT:     Address:         0x0000000000800060
 ELF-AVR-NEXT:     AddressAlign:    0x0000000000000001
-ELF-AVR-NEXT:     Content:         ''
+ELF-AVR-NEXT:     Content:         ""
 ELF-AVR-NEXT: Symbols:         
 ELF-AVR-NEXT:   Local:           
 ELF-AVR-NEXT:     - Type:            STT_SECTION
 ELF-AVR-NEXT:       Section:         .text
 ELF-AVR-NEXT:     - Type:            STT_SECTION
 ELF-AVR-NEXT:       Section:         .data
 ELF-AVR-NEXT:       Value:           0x0000000000800060
 ELF-AVR-NEXT:     - Name:            a.o

 ELF-AVR-NEXT:       Section:         .data
 ELF-AVR-NEXT:       Value:           0x0000000000800060
 
 
 ELF-X86-64-UNWIND:      - Name:            .eh_frame
 ELF-X86-64-UNWIND-NEXT:   Type:            SHT_X86_64_UNWIND
 ELF-X86-64-UNWIND-NEXT:   Flags:           [ SHF_ALLOC ]
 ELF-X86-64-UNWIND-NEXT:   AddressAlign:    0x0000000000000001
-ELF-X86-64-UNWIND-NEXT:   Content:         ''
+ELF-X86-64-UNWIND-NEXT:   Content:         ""
 
 RUN: not obj2yaml %t.blah 2>&1 | FileCheck --check-prefix=ENOENT %s
 ENOENT: Error: '{{[Nn]}}o such file or directory'

llvm/test/ObjectYAML/MachO/DWARF-BigEndian.yaml

 # RUN: yaml2obj %s | obj2yaml | FileCheck %s
 
 --- !mach-o
 IsLittleEndian:  false
 FileHeader:      
   magic:           0xFEEDFACE
   cputype:         0x00000012
   cpusubtype:      0x00000000
   filetype:        0x00000001
   ncmds:           4
   sizeofcmds:      1264
   flags:           0x00002000
 LoadCommands:    
   - cmd:             LC_SEGMENT
     cmdsize:         1144
-    segname:         ''
+    segname:         ""
     vmaddr:          0
     vmsize:          1122
     fileoff:         1292
     filesize:        1122
     maxprot:         7
     initprot:        7
     nsects:          16
     flags:           0
- n_strx:          24
       n_desc:          0
       n_value:         0
     - n_strx:          1
       n_type:          0x01
       n_sect:          0
       n_desc:          0
       n_value:         0
   StringTable:     
-    - ''
+    - ""
     - _compilerrt_abort_impl
     - ___absvdi2
-    - ''
+    - ""
 DWARF:           
   debug_str:       
-    - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)'
+    - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)"
     - ../compiler-rt/lib/builtins/absvdi2.c
     - /Users/cbieneman/dev/open-source/llvm-build-rel
     - int
     - di_int
     - long long int
     - __absvdi2
     - a
     - N
- Code:            0x00000007
       Children:        DW_CHILDREN_no
       Attributes:      
         - Attribute:       DW_AT_type
           Form:            DW_FORM_ref4       
 ...
 
 #CHECK: DWARF:           
 #CHECK:   debug_str:       
-#CHECK:     - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)'
+#CHECK:     - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)"
 #CHECK:     - ../compiler-rt/lib/builtins/absvdi2.c
 #CHECK:     - /Users/cbieneman/dev/open-source/llvm-build-rel
 #CHECK:     - int
 #CHECK:     - di_int
 #CHECK:     - long long int
 #CHECK:     - __absvdi2
 #CHECK:     - a
 #CHECK:     - N

llvm/test/ObjectYAML/MachO/DWARF-LittleEndian.yaml

 # RUN: yaml2obj %s | obj2yaml | FileCheck %s
 
 --- !mach-o
 IsLittleEndian:  true
 FileHeader:      
   magic:           0xFEEDFACF
   cputype:         0x01000007
   cpusubtype:      0x00000003
   filetype:        0x00000001
   ncmds:           4
   sizeofcmds:      1392
   flags:           0x00002000
   reserved:        0x00000000
 LoadCommands:    
   - cmd:             LC_SEGMENT_64
     cmdsize:         1272
-    segname:         ''
+    segname:         ""
     vmaddr:          0
     vmsize:          1086
     fileoff:         1424
     filesize:        1086
     maxprot:         7
     initprot:        7
     nsects:          15
     flags:           0
- n_strx:          24
       n_desc:          0
       n_value:         0
     - n_strx:          1
       n_type:          0x01
       n_sect:          0
       n_desc:          0
       n_value:         0
   StringTable:     
-    - ''
+    - ""
     - _compilerrt_abort_impl
     - ___absvdi2
-    - ''
+    - ""
 DWARF:           
   debug_str:       
-    - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)'
+    - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)"
     - ../compiler-rt/lib/builtins/absvdi2.c
     - /Users/cbieneman/dev/open-source/llvm-build-rel
     - int
     - di_int
     - long long int
     - __absvdi2
     - a
     - N
- Code:            0x00000007
       Children:        DW_CHILDREN_no
       Attributes:      
         - Attribute:       DW_AT_type
           Form:            DW_FORM_ref4
 ...
 
 #CHECK: DWARF:           
 #CHECK:   debug_str:       
-#CHECK:     - 'clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)'
+#CHECK:     - "clang version 4.0.0 (trunk 290181) (llvm/trunk 290209)"
 #CHECK:     - ../compiler-rt/lib/builtins/absvdi2.c
 #CHECK:     - /Users/cbieneman/dev/open-source/llvm-build-rel
 #CHECK:     - int
 #CHECK:     - di_int
 #CHECK:     - long long int
 #CHECK:     - __absvdi2
 #CHECK:     - a
 #CHECK:     - N

llvm/test/ObjectYAML/MachO/DWARF-debug_str.yaml

- n_strx:          2
       n_desc:          16
       n_value:         4294967296
     - n_strx:          22
       n_type:          0x0F
       n_sect:          1
       n_desc:          0
       n_value:         4294971296
   StringTable:     
-    - ''
-    - ''
+    - ""
+    - ""
     - __mh_execute_header
     - _main
 DWARF:           
   debug_str:    
-    - ''
-    - 'clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)'
+    - ""
+    - "clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)"
     - hello_world.c
     - /Users/cbieneman/dev/open-source/llvm-build-rel
     - main
     - argc
     - argv
     - int
     - char
 ...
 
 #CHECK: DWARF:           
 #CHECK:   debug_str:    
-#CHECK:     - ''
-#CHECK:     - 'clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)'
+#CHECK:     - ""
+#CHECK:     - "clang version 4.0.0 (trunk 288677) (llvm/trunk 288676)"
 #CHECK:     - hello_world.c
 #CHECK:     - /Users/cbieneman/dev/open-source/llvm-build-rel
 #CHECK:     - main
 #CHECK:     - argc
 #CHECK:     - argv
 #CHECK:     - int
 #CHECK:     - char
 

llvm/test/ObjectYAML/MachO/dylib_dylinker_command.yaml

- cmd:             LC_LOAD_DYLINKER
     ZeroPadBytes:    7
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         48
     dylib:           
       name:            24
       timestamp:       2
       current_version: 7864576
       compatibility_version: 65536
-    PayloadString:   '/usr/lib/libc++.1.dylib'
+    PayloadString:   "/usr/lib/libc++.1.dylib"
     ZeroPadBytes:    1
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         56
     dylib:           
       name:            24
       timestamp:       2
       current_version: 80349697
       compatibility_version: 65536

 #CHECK:     ZeroPadBytes:    7
 #CHECK:   - cmd:             LC_LOAD_DYLIB
 #CHECK:     cmdsize:         48
 #CHECK:     dylib:           
 #CHECK:       name:            24
 #CHECK:       timestamp:       2
 #CHECK:       current_version: 7864576
 #CHECK:       compatibility_version: 65536
-#CHECK:     PayloadString:   '/usr/lib/libc++.1.dylib'
+#CHECK:     PayloadString:   "/usr/lib/libc++.1.dylib"
 #CHECK:     ZeroPadBytes:    1
 #CHECK:   - cmd:             LC_LOAD_DYLIB
 #CHECK:     cmdsize:         56
 #CHECK:     dylib:           
 #CHECK:       name:            24
 #CHECK:       timestamp:       2
 #CHECK:       current_version: 80349697
 #CHECK:       compatibility_version: 65536
 #CHECK:     PayloadString:   /usr/lib/libSystem.B.dylib
 #CHECK:     ZeroPadBytes:    6

llvm/test/ObjectYAML/MachO/export_trie.yaml

- cmd:             LC_MAIN
     stacksize:       0
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         48
     dylib:           
       name:            24
       timestamp:       2
       current_version: 7864576
       compatibility_version: 65536
-    PayloadString:   '/usr/lib/libc++.1.dylib'
+    PayloadString:   "/usr/lib/libc++.1.dylib"
     ZeroPadBytes:    1
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         56
     dylib:           
       name:            24
       timestamp:       2
       current_version: 80349697
       compatibility_version: 65536
     PayloadString:   /usr/lib/libSystem.B.dylib
     ZeroPadBytes:    6
   - cmd:             LC_FUNCTION_STARTS
     cmdsize:         16
     dataoff:         13064
     datasize:        16
   - cmd:             LC_DATA_IN_CODE
     cmdsize:         16
     dataoff:         13080
     datasize:        0
 LinkEditData:    
   ExportTrie:      
     TerminalSize:    0
     NodeOffset:      0
-    Name:            ''
+    Name:            ""
     Flags:           0x0000000000000000
     Address:         0x0000000000000000
     Other:           0x0000000000000000
-    ImportName:      ''
+    ImportName:      ""
     Children:        
       - TerminalSize:    0
         NodeOffset:      5
         Name:            _
         Flags:           0x0000000000000000
         Address:         0x0000000000000000
         Other:           0x0000000000000000
-        ImportName:      ''
+        ImportName:      ""
         Children:        
           - TerminalSize:    2
             NodeOffset:      33
             Name:            _mh_execute_header
             Flags:           0x0000000000000000
             Address:         0x0000000000000000
             Other:           0x0000000000000000
-            ImportName:      ''
+            ImportName:      ""
           - TerminalSize:    3
             NodeOffset:      37
             Name:            main
             Flags:           0x0000000000000000
             Address:         0x0000000000001160
             Other:           0x0000000000000000
-            ImportName:      ''
+            ImportName:      ""
 ...
 
 #CHECK: ExportTrie:      
 #CHECK:     TerminalSize:    0
 #CHECK:     NodeOffset:      0
-#CHECK:     Name:            ''
+#CHECK:     Name:            ""
 #CHECK:     Children:        
 #CHECK:       - TerminalSize:    0
 #CHECK:         NodeOffset:      5
 #CHECK:         Name:            _
 #CHECK:         Children:        
 #CHECK:           - TerminalSize:    2
 #CHECK:             NodeOffset:      33
 #CHECK:             Name:            _mh_execute_header
 #CHECK:             Address:         0x0000000000000000
 #CHECK:           - TerminalSize:    3
 #CHECK:             NodeOffset:      37
 #CHECK:             Name:            main
 #CHECK:             Address:         0x0000000000001160

llvm/test/ObjectYAML/MachO/null_string_entries.yaml

- cmd:             LC_MAIN
     stacksize:       0
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         48
     dylib:           
       name:            24
       timestamp:       2
       current_version: 7864576
       compatibility_version: 65536
-    PayloadString:   '/usr/lib/libc++.1.dylib'
+    PayloadString:   "/usr/lib/libc++.1.dylib"
     ZeroPadBytes:    1
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         52
     dylib:           
       name:            24
       timestamp:       2
       current_version: 80349697
       compatibility_version: 65536
     PayloadString:   /usr/lib/libSystem.B.dylib
     ZeroPadBytes:    2
   - cmd:             LC_FUNCTION_STARTS
     cmdsize:         16
     dataoff:         13272
     datasize:        16
   - cmd:             LC_DATA_IN_CODE
     cmdsize:         16
     dataoff:         13288
     datasize:        0
 LinkEditData:
   StringTable:     
-    - ''
-    - ''
-    - ''
-    - ''
+    - ""
+    - ""
+    - ""
+    - ""
     - __mh_execute_header
     - __Unwind_Resume
     - __ZNKSt3__16locale9use_facetERNS0_2idE
     - __ZNKSt3__18ios_base6getlocEv
     - __ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEmc
     - __ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev
     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE3putEc
     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE5flushEv
     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE6sentryC1ERS3_
     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE6sentryD1Ev
     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEElsEm
     - __ZNSt3__14coutE
     - __ZNSt3__15ctypeIcE2idE
     - __ZNSt3__16localeD1Ev
     - __ZNSt3__18ios_base33__set_badbit_and_consider_rethrowEv
     - __ZNSt3__18ios_base5clearEj
     - __ZSt9terminatev
     - ___cxa_begin_catch
     - ___cxa_end_catch
     - ___gxx_personality_v0
     - _memset
     - _strlen
     - _strnlen
     - dyld_stub_binder
-    - 'radr://5614542'
-    - ''
-    - ''
-    - ''
+    - "radr://5614542"
+    - ""
+    - ""
+    - ""
 ...
 
 #CHECK: StringTable:     
-#CHECK:     - ''
-#CHECK:     - ''
-#CHECK:     - ''
-#CHECK:     - ''
+#CHECK:     - ""
+#CHECK:     - ""
+#CHECK:     - ""
+#CHECK:     - ""
 #CHECK:     - __mh_execute_header
 #CHECK:     - __Unwind_Resume
 #CHECK:     - __ZNKSt3__16locale9use_facetERNS0_2idE
 #CHECK:     - __ZNKSt3__18ios_base6getlocEv
 #CHECK:     - __ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEE6__initEmc
 #CHECK:     - __ZNSt3__112basic_stringIcNS_11char_traitsIcEENS_9allocatorIcEEED1Ev
 #CHECK:     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE3putEc
 #CHECK:     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE5flushEv
 #CHECK:     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE6sentryC1ERS3_
 #CHECK:     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEE6sentryD1Ev
 #CHECK:     - __ZNSt3__113basic_ostreamIcNS_11char_traitsIcEEElsEm
 #CHECK:     - __ZNSt3__14coutE
 #CHECK:     - __ZNSt3__15ctypeIcE2idE
 #CHECK:     - __ZNSt3__16localeD1Ev
 #CHECK:     - __ZNSt3__18ios_base33__set_badbit_and_consider_rethrowEv
 #CHECK:     - __ZNSt3__18ios_base5clearEj
 #CHECK:     - __ZSt9terminatev
 #CHECK:     - ___cxa_begin_catch
 #CHECK:     - ___cxa_end_catch
 #CHECK:     - ___gxx_personality_v0
 #CHECK:     - _memset
 #CHECK:     - _strlen
 #CHECK:     - _strnlen
 #CHECK:     - dyld_stub_binder
-#CHECK:     - 'radr://5614542'
-#CHECK:     - ''
-#CHECK:     - ''
-#CHECK:     - ''
+#CHECK:     - "radr://5614542"
+#CHECK:     - ""
+#CHECK:     - ""
+#CHECK:     - ""

llvm/test/ObjectYAML/MachO/out_of_order_linkedit.yaml

- cmd:             LC_MAIN
     stacksize:       0
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         48
     dylib:           
       name:            24
       timestamp:       2
       current_version: 7864576
       compatibility_version: 65536
-    PayloadString:   '/usr/lib/libc++.1.dylib'
+    PayloadString:   "/usr/lib/libc++.1.dylib"
     ZeroPadBytes:    1
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         56
     dylib:           
       name:            24
       timestamp:       2
       current_version: 80349697
       compatibility_version: 65536
- Opcode:          REBASE_OPCODE_DO_REBASE_ULEB_TIMES
       Imm:             0
       ExtraData:       
         - 0x000000000000000F
     - Opcode:          REBASE_OPCODE_DONE
       Imm:             0
   BindOpcodes:     
     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
       Imm:             1
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
       Imm:             0
       Symbol:          __ZNSt3__14coutE
     - Opcode:          BIND_OPCODE_SET_TYPE_IMM
       Imm:             1
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
       Imm:             2
       ULEBExtraData:   
         - 0x0000000000000000
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_DO_BIND
       Imm:             0
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
       Imm:             0
       Symbol:          __ZNSt3__15ctypeIcE2idE
     - Opcode:          BIND_OPCODE_DO_BIND
       Imm:             0
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
       Imm:             0
       Symbol:          ___gxx_personality_v0
     - Opcode:          BIND_OPCODE_DO_BIND
       Imm:             0
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
       Imm:             2
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
       Imm:             0
       Symbol:          dyld_stub_binder
     - Opcode:          BIND_OPCODE_DO_BIND
       Imm:             0
-      Symbol:          ''
+      Symbol:          ""
     - Opcode:          BIND_OPCODE_DONE
       Imm:             0
-      Symbol:          ''
+      Symbol:          ""
 ...
 
 #CHECK:   - cmd:             LC_DYLD_INFO_ONLY
 #CHECK:     cmdsize:         48
 #CHECK:     rebase_off:      12384
 #CHECK:     rebase_size:     8
 #CHECK:     bind_off:        12288
 #CHECK:     bind_size:       96

 #CHECK:       Imm:             0
 #CHECK:       ExtraData:       
 #CHECK:         - 0x000000000000000F
 #CHECK:     - Opcode:          REBASE_OPCODE_DONE
 #CHECK:       Imm:             0
 #CHECK:   BindOpcodes:     
 #CHECK:     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
 #CHECK:       Imm:             1
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 #CHECK:       Imm:             0
 #CHECK:       Symbol:          __ZNSt3__14coutE
 #CHECK:     - Opcode:          BIND_OPCODE_SET_TYPE_IMM
 #CHECK:       Imm:             1
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_SEGMENT_AND_OFFSET_ULEB
 #CHECK:       Imm:             2
 #CHECK:       ULEBExtraData:   
 #CHECK:         - 0x0000000000000000
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 #CHECK:       Imm:             0
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 #CHECK:       Imm:             0
 #CHECK:       Symbol:          __ZNSt3__15ctypeIcE2idE
 #CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 #CHECK:       Imm:             0
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 #CHECK:       Imm:             0
 #CHECK:       Symbol:          ___gxx_personality_v0
 #CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 #CHECK:       Imm:             0
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_DYLIB_ORDINAL_IMM
 #CHECK:       Imm:             2
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_SET_SYMBOL_TRAILING_FLAGS_IMM
 #CHECK:       Imm:             0
 #CHECK:       Symbol:          dyld_stub_binder
 #CHECK:     - Opcode:          BIND_OPCODE_DO_BIND
 #CHECK:       Imm:             0
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""
 #CHECK:     - Opcode:          BIND_OPCODE_DONE
 #CHECK:       Imm:             0
-#CHECK:       Symbol:          ''
+#CHECK:       Symbol:          ""

llvm/test/ObjectYAML/MachO/symtab.yaml

- cmd:             LC_MAIN
     stacksize:       0
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         48
     dylib:           
       name:            24
       timestamp:       2
       current_version: 7864576
       compatibility_version: 65536
-    PayloadString:   '/usr/lib/libc++.1.dylib'
+    PayloadString:   "/usr/lib/libc++.1.dylib"
     ZeroPadBytes:    1
   - cmd:             LC_LOAD_DYLIB
     cmdsize:         56
     dylib:           
       name:            24
       timestamp:       2
       current_version: 80349697
       compatibility_version: 65536
- n_strx:          1065
       n_desc:          512
       n_value:         0
     - n_strx:          1073
       n_type:          0x01
       n_sect:          0
       n_desc:          512
       n_value:         0
   StringTable:     
-    - ' '
+    - " "
     - __ZNSt3__1lsINS_11char_traitsIcEEEERNS_13basic_ostreamIcT_EES6_PKc
     - __ZNSt3__124__put_character_sequenceIcNS_11char_traitsIcEEEERNS_13basic_ostreamIT_T0_EES7_PKS4_m
     - __ZNSt3__111char_traitsIcE6lengthEPKc
     - __ZNSt3__116__pad_and_outputIcNS_11char_traitsIcEEEENS_19ostreambuf_iteratorIT_T0_EES6_PKS4_S8_S8_RNS_8ios_baseES4_
     - ___clang_call_terminate
     - __ZNSt3__111char_traitsIcE11eq_int_typeEii
     - __ZNSt3__111char_traitsIcE3eofEv
     - GCC_except_table2

 #CHECK:       n_desc:          512
 #CHECK:       n_value:         0
 #CHECK:     - n_strx:          1073
 #CHECK:       n_type:          0x01
 #CHECK:       n_sect:          0
 #CHECK:       n_desc:          512
 #CHECK:       n_value:         0
 #CHECK:   StringTable:     
-#CHECK:     - ' '
+#CHECK:     - " "
 #CHECK:     - __ZNSt3__1lsINS_11char_traitsIcEEEERNS_13basic_ostreamIcT_EES6_PKc
 #CHECK:     - __ZNSt3__124__put_character_sequenceIcNS_11char_traitsIcEEEERNS_13basic_ostreamIT_T0_EES7_PKS4_m
 #CHECK:     - __ZNSt3__111char_traitsIcE6lengthEPKc
 #CHECK:     - __ZNSt3__116__pad_and_outputIcNS_11char_traitsIcEEEENS_19ostreambuf_iteratorIT_T0_EES6_PKS4_S8_S8_RNS_8ios_baseES4_
 #CHECK:     - ___clang_call_terminate
 #CHECK:     - __ZNSt3__111char_traitsIcE11eq_int_typeEii
 #CHECK:     - __ZNSt3__111char_traitsIcE3eofEv
 #CHECK:     - GCC_except_table2

llvm/test/ObjectYAML/wasm/data_section.yaml

 # RUN: yaml2obj %s | obj2yaml | FileCheck %s
 --- !WASM
 FileHeader:
   Version:         0x00000001
 Sections:
   - Type:            MEMORY
     Memories:
       - Initial:         0x00000003
   - Type:            DATA
     Segments:
       - Index:           0
         Offset:
           Opcode:          I32_CONST
           Value:           4
-        Content:         '10001000'
+        Content:         "10001000"
     Relocations:
       - Type:            R_WEBASSEMBLY_GLOBAL_ADDR_I32
         Index:           0
         Offset:          0x00000006
         Addend:          8
       - Type:            R_WEBASSEMBLY_GLOBAL_ADDR_I32
         Index:           0
         Offset:          0x00000006

 # CHECK-NEXT:        Index:           0
 # CHECK-NEXT:        Offset:          0x00000006
 # CHECK-NEXT:        Addend:          -6
 # CHECK-NEXT:     Segments:
 # CHECK-NEXT:       - Index:           0
 # CHECK-NEXT:         Offset:
 # CHECK-NEXT:           Opcode:          I32_CONST
 # CHECK-NEXT:           Value:           4
-# CHECK-NEXT:         Content:         '10001000'
+# CHECK-NEXT:         Content:         "10001000"
 # CHECK-NEXT: ...

llvm/test/ThinLTO/X86/diagnostic-handler-remarks-with-hotness.ll

 ; RUN: cat %t.yaml.thin.0.yaml | FileCheck %s -check-prefix=YAML1
 ; YAML1:      --- !Passed
 ; YAML1-NEXT: Pass:            inline
 ; YAML1-NEXT: Name:            Inlined
 ; YAML1-NEXT: Function:        main
 ; YAML1-NEXT: Hotness:         50
 ; YAML1-NEXT: Args:
 ; YAML1-NEXT:   - Callee:          foo
-; YAML1-NEXT:   - String:          ' inlined into '
+; YAML1-NEXT:   - String:          " inlined into "
 ; YAML1-NEXT:   - Caller:          main
 ; YAML1-NEXT: ...
 
 
 ; Verify that bar is imported and inlined into foo
 ; RUN: cat %t.yaml.thin.1.yaml | FileCheck %s -check-prefix=YAML2
 ; YAML2:      --- !Passed
 ; YAML2-NEXT: Pass:            inline
 ; YAML2-NEXT: Name:            Inlined
 ; YAML2-NEXT: Function:        foo
 ; YAML2-NEXT: Args:
 ; YAML2-NEXT:   - Callee:          bar
-; YAML2-NEXT:   - String:          ' inlined into '
+; YAML2-NEXT:   - String:          " inlined into "
 ; YAML2-NEXT:   - Caller:          foo
 ; YAML2-NEXT: ...
 
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 define i32 @bar() {

llvm/test/ThinLTO/X86/diagnostic-handler-remarks.ll

 ; Verify that bar is imported and inlined into foo
 ; RUN: cat %t.yaml.thin.0.yaml | FileCheck %s -check-prefix=YAML1
 ; YAML1:      --- !Passed
 ; YAML1-NEXT: Pass:            inline
 ; YAML1-NEXT: Name:            Inlined
 ; YAML1-NEXT: Function:        main
 ; YAML1-NEXT: Args:
 ; YAML1-NEXT:   - Callee:          foo
-; YAML1-NEXT:   - String:          ' inlined into '
+; YAML1-NEXT:   - String:          " inlined into "
 ; YAML1-NEXT:   - Caller:          main
 ; YAML1-NEXT: ...
 
 
 ; Verify that bar is imported and inlined into foo
 ; RUN: cat %t.yaml.thin.1.yaml | FileCheck %s -check-prefix=YAML2
 ; YAML2: --- !Passed
 ; YAML2-NEXT: Pass:            inline
 ; YAML2-NEXT: Name:            Inlined
 ; YAML2-NEXT: Function:        foo
 ; YAML2-NEXT: Args:
 ; YAML2-NEXT:   - Callee:          bar
-; YAML2-NEXT:   - String:          ' inlined into '
+; YAML2-NEXT:   - String:          " inlined into "
 ; YAML2-NEXT:   - Caller:          foo
 ; YAML2-NEXT: ...
 
 
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 define i32 @bar() {
   ret i32 42
 }
 declare i32 @foo()
 define i32 @main() {
   %i = call i32 @foo()
   ret i32 %i
 }
 

llvm/test/Transforms/GVN/opt-remarks.ll

 ; RUN: opt < %s -gvn -o /dev/null  -pass-remarks-output=%t -S -pass-remarks=gvn \
 ; RUN:     2>&1 | FileCheck %s
 ; RUN: cat %t | FileCheck -check-prefix=YAML %s
 
 ; CHECK:      remark: <unknown>:0:0: load of type i32 eliminated{{$}}
 ; CHECK-NEXT: remark: <unknown>:0:0: load of type i32 eliminated{{$}}
 ; CHECK-NEXT: remark: <unknown>:0:0: load of type i32 eliminated{{$}}
 ; CHECK-NOT:  remark:
 
 ; YAML:      --- !Passed
 ; YAML-NEXT: Pass:            gvn
 ; YAML-NEXT: Name:            LoadElim
 ; YAML-NEXT: Function:        arg
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'load of type '
+; YAML-NEXT:   - String:          "load of type "
 ; YAML-NEXT:   - Type:            i32
-; YAML-NEXT:   - String:          ' eliminated'
-; YAML-NEXT:   - String:          ' in favor of '
+; YAML-NEXT:   - String:          " eliminated"
+; YAML-NEXT:   - String:          " in favor of "
 ; YAML-NEXT:   - InfavorOfValue:  i
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Passed
 ; YAML-NEXT: Pass:            gvn
 ; YAML-NEXT: Name:            LoadElim
 ; YAML-NEXT: Function:        const
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'load of type '
+; YAML-NEXT:   - String:          "load of type "
 ; YAML-NEXT:   - Type:            i32
-; YAML-NEXT:   - String:          ' eliminated'
-; YAML-NEXT:   - String:          ' in favor of '
-; YAML-NEXT:   - InfavorOfValue:  '4'
+; YAML-NEXT:   - String:          " eliminated"
+; YAML-NEXT:   - String:          " in favor of "
+; YAML-NEXT:   - InfavorOfValue:  "4"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Passed
 ; YAML-NEXT: Pass:            gvn
 ; YAML-NEXT: Name:            LoadElim
 ; YAML-NEXT: Function:        inst
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'load of type '
+; YAML-NEXT:   - String:          "load of type "
 ; YAML-NEXT:   - Type:            i32
-; YAML-NEXT:   - String:          ' eliminated'
-; YAML-NEXT:   - String:          ' in favor of '
+; YAML-NEXT:   - String:          " eliminated"
+; YAML-NEXT:   - String:          " in favor of "
 ; YAML-NEXT:   - InfavorOfValue:  load
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Missed
 ; YAML-NEXT: Pass:            gvn
 ; YAML-NEXT: Name:            LoadClobbered
 ; YAML-NEXT: DebugLoc:        { File: /tmp/s.c, Line: 3, Column: 3 }
 ; YAML-NEXT: Function:        may_alias
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'load of type '
+; YAML-NEXT:   - String:          "load of type "
 ; YAML-NEXT:   - Type:            i32
-; YAML-NEXT:   - String:          ' not eliminated'
-; YAML-NEXT:   - String:          ' in favor of '
+; YAML-NEXT:   - String:          " not eliminated"
+; YAML-NEXT:   - String:          " in favor of "
 ; YAML-NEXT:   - OtherAccess:     load
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 1, Column: 13 }
-; YAML-NEXT:   - String:          ' because it is clobbered by '
+; YAML-NEXT:   - String:          " because it is clobbered by "
 ; YAML-NEXT:   - ClobberedBy:     store
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 2, Column: 10 }
 ; YAML-NEXT: ...
 
 define i32 @arg(i32* %p, i32 %i) {
 entry:
   store i32 %i, i32* %p
   %load = load i32, i32* %p

llvm/test/Transforms/Inline/optimization-remarks-passed-yaml.ll

 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            CanBeInlined
 ; YAML-NEXT: DebugLoc:        { File: /tmp/s.c, Line: 4, Column: 10 }
 ; YAML-NEXT: Function:        bar
 ; YAML-NEXT: Hotness:         30
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee: foo
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 1, Column: 0 }
-; YAML-NEXT:   - String: ' can be inlined into '
+; YAML-NEXT:   - String: " can be inlined into "
 ; YAML-NEXT:   - Caller: bar
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 3, Column: 0 }
-; YAML-NEXT:   - String: ' with cost='
-; YAML-NEXT:   - Cost: '{{[0-9\-]+}}'
-; YAML-NEXT:   - String: ' (threshold='
-; YAML-NEXT:   - Threshold: '{{[0-9]+}}'
-; YAML-NEXT:   - String: ')'
+; YAML-NEXT:   - String: " with cost="
+; YAML-NEXT:   - Cost: "{{[0-9\-]+}}"
+; YAML-NEXT:   - String: " (threshold="
+; YAML-NEXT:   - Threshold: "{{[0-9]+}}"
+; YAML-NEXT:   - String: ")"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Passed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            Inlined
 ; YAML-NEXT: DebugLoc:        { File: /tmp/s.c, Line: 4, Column: 10 }
 ; YAML-NEXT: Function:        bar
 ; YAML-NEXT: Hotness:         30
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee: foo
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 1, Column: 0 }
-; YAML-NEXT:   - String: ' inlined into '
+; YAML-NEXT:   - String: " inlined into "
 ; YAML-NEXT:   - Caller: bar
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 3, Column: 0 }
 ; YAML-NEXT: ...
 
-; ModuleID = '/tmp/s.c'
+; ModuleID = "/tmp/s.c"
 source_filename = "/tmp/s.c"
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 ; Function Attrs: nounwind ssp uwtable
 define i32 @foo() #0 !dbg !7 {
 entry:
   ret i32 1, !dbg !9

llvm/test/Transforms/Inline/optimization-remarks-yaml.ll

 ; YAML:      --- !Missed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            NoDefinition
 ; YAML-NEXT: DebugLoc:        { File: /tmp/s.c, Line: 5, Column: 10 }
 ; YAML-NEXT: Function:        baz
 ; YAML-NEXT: Hotness:         30
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee: foo
-; YAML-NEXT:   - String: ' will not be inlined into '
+; YAML-NEXT:   - String: " will not be inlined into "
 ; YAML-NEXT:   - Caller: baz
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 4, Column: 0 }
-; YAML-NEXT:   - String: ' because its definition is unavailable'
+; YAML-NEXT:   - String: " because its definition is unavailable"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Missed
 ; YAML-NEXT: Pass:            inline
 ; YAML-NEXT: Name:            NoDefinition
 ; YAML-NEXT: DebugLoc:        { File: /tmp/s.c, Line: 5, Column: 18 }
 ; YAML-NEXT: Function:        baz
 ; YAML-NEXT: Hotness:         30
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - Callee: bar
-; YAML-NEXT:   - String: ' will not be inlined into '
+; YAML-NEXT:   - String: " will not be inlined into "
 ; YAML-NEXT:   - Caller: baz
 ; YAML-NEXT:     DebugLoc:        { File: /tmp/s.c, Line: 4, Column: 0 }
-; YAML-NEXT:   - String: ' because its definition is unavailable'
+; YAML-NEXT:   - String: " because its definition is unavailable"
 ; YAML-NEXT: ...
 
-; ModuleID = '/tmp/s.c'
+; ModuleID = "/tmp/s.c"
 source_filename = "/tmp/s.c"
 target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
 target triple = "x86_64-apple-macosx10.11.0"
 
 ; Function Attrs: nounwind ssp uwtable
 define i32 @"\01baz"() !dbg !7 !prof !14 {
 entry:
   %call = call i32 (...) @foo(), !dbg !9

llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-missed.ll

-; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed='loop-vectorize' -pass-remarks-analysis='loop-vectorize' 2>&1 | FileCheck %s
+; RUN: opt < %s -loop-vectorize -S -pass-remarks-missed="loop-vectorize" -pass-remarks-analysis="loop-vectorize" 2>&1 | FileCheck %s
 ; RUN: opt < %s -loop-vectorize -o /dev/null -pass-remarks-output=%t.yaml
 ; RUN: cat %t.yaml | FileCheck -check-prefix=YAML %s
 
 ; C/C++ code for tests
 ; void test(int *A, int Length) {
 ; #pragma clang loop vectorize(enable) interleave(enable)
 ;   for (int i = 0; i < Length; i++) {
 ;     A[i] = i;

 ; CHECK: remark: source.cpp:27:3: loop not vectorized
 
 ; YAML:       --- !Analysis
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            CantComputeNumberOfIterations
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 4, Column: 5 }
 ; YAML-NEXT: Function:        _Z4testPii
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          could not determine number of loop iterations
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Missed
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            MissedDetails
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 4, Column: 5 }
 ; YAML-NEXT: Function:        _Z4testPii
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - String:          loop not vectorized
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Analysis
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            AllDisabled
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 13, Column: 5 }
 ; YAML-NEXT: Function:        _Z13test_disabledPii
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1'
+; YAML-NEXT:   - String:          "loop not vectorized: vectorization and interleaving are explicitly disabled, or vectorize width and interleave count are both set to 1"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Analysis
-; YAML-NEXT: Pass:            ''
+; YAML-NEXT: Pass:            ""
 ; YAML-NEXT: Name:            CantIdentifyArrayBounds
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 19, Column: 5 }
 ; YAML-NEXT: Function:        _Z17test_array_boundsPiS_i
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          cannot identify array bounds
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Missed
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            MissedDetails
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 19, Column: 5 }
 ; YAML-NEXT: Function:        _Z17test_array_boundsPiS_i
 ; YAML-NEXT: Args:
 ; YAML-NEXT:   - String:          loop not vectorized
-; YAML-NEXT:   - String:          ' (Force='
-; YAML-NEXT:   - Force:           'true'
-; YAML-NEXT:   - String:          ')'
+; YAML-NEXT:   - String:          " (Force="
+; YAML-NEXT:   - Force:           "true"
+; YAML-NEXT:   - String:          ")"
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Failure
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            FailedRequestedVectorization
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 19, Column: 5 }
 ; YAML-NEXT: Function:        _Z17test_array_boundsPiS_i
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          failed explicitly specified loop vectorization
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Analysis
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            NoCFGForSelect
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 29, Column: 7 }
 ; YAML-NEXT: Function:        test_multiple_failures
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          control flow cannot be substituted for a select
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Analysis
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            NonReductionValueUsedOutsideLoop
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 27, Column: 3 }
 ; YAML-NEXT: Function:        test_multiple_failures
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          value that could not be identified as reduction is used outside the loop
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Analysis
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            CantComputeNumberOfIterations
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 27, Column: 3 }
 ; YAML-NEXT: Function:        test_multiple_failures
 ; YAML-NEXT: Args:
-; YAML-NEXT:   - String:          'loop not vectorized: '
+; YAML-NEXT:   - String:          "loop not vectorized: "
 ; YAML-NEXT:   - String:          could not determine number of loop iterations
 ; YAML-NEXT: ...
 ; YAML-NEXT: --- !Missed
 ; YAML-NEXT: Pass:            loop-vectorize
 ; YAML-NEXT: Name:            MissedDetails
 ; YAML-NEXT: DebugLoc:        { File: source.cpp, Line: 27, Column: 3 }
 ; YAML-NEXT: Function:        test_multiple_failures
 ; YAML-NEXT: Args:

llvm/test/Transforms/WholeProgramDevirt/export-single-impl.ll

 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:   typeid4:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            SingleImpl
-; SUMMARY-NEXT:         SingleImplName:  'vf4$merged'
+; SUMMARY-NEXT:         SingleImplName:  "vf4$merged"
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT: WithGlobalValueDeadStripping: false
 ; SUMMARY-NEXT: ...
 
 ; CHECK: @vt1 = constant void (i8*)* @vf1
 @vt1 = constant void (i8*)* @vf1, !type !0
 
 ; CHECK: @vt2 = constant void (i8*)* @vf2

llvm/test/Transforms/WholeProgramDevirt/export-uniform-ret-val.ll

 ; RUN: opt -wholeprogramdevirt -wholeprogramdevirt-summary-action=export -wholeprogramdevirt-read-summary=%S/Inputs/export.yaml -wholeprogramdevirt-write-summary=%t -S -o - %s | FileCheck %s
 ; RUN: FileCheck --check-prefix=SUMMARY %s < %t
 
 ; SUMMARY-NOT: TypeTests:
 
 ; SUMMARY:      TypeIdMap:
 ; SUMMARY-NEXT:   typeid4:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           24,12:
 ; SUMMARY-NEXT:             Kind:            UniformRetVal
 ; SUMMARY-NEXT:             Info:            36
 
 ; CHECK: @vt4a = constant i32 (i8*, i32, i32)* @vf4a
 @vt4a = constant i32 (i8*, i32, i32)* @vf4a, !type !0
 

llvm/test/Transforms/WholeProgramDevirt/export-unique-ret-val.ll

 ; RUN: opt -wholeprogramdevirt -wholeprogramdevirt-summary-action=export -wholeprogramdevirt-read-summary=%S/Inputs/export.yaml -wholeprogramdevirt-write-summary=%t -S -o - %s | FileCheck %s
 ; RUN: FileCheck --check-prefix=SUMMARY %s < %t
 
 ; SUMMARY-NOT:  TypeTests:
 
 ; SUMMARY:      TypeIdMap:
 ; SUMMARY-NEXT:   typeid3:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           12,24:
 ; SUMMARY-NEXT:             Kind:            UniqueRetVal
 ; SUMMARY-NEXT:             Info:            0
 ; SUMMARY-NEXT:   typeid4:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           24,12:
 ; SUMMARY-NEXT:             Kind:            UniqueRetVal
 ; SUMMARY-NEXT:             Info:            1
 
 ; CHECK: @vt3a = constant i1 (i8*, i32, i32)* @vf3a
 @vt3a = constant i1 (i8*, i32, i32)* @vf3a, !type !0
 

llvm/test/Transforms/WholeProgramDevirt/export-vcp.ll

 ; RUN: opt -wholeprogramdevirt -wholeprogramdevirt-summary-action=export -wholeprogramdevirt-read-summary=%S/Inputs/export.yaml -wholeprogramdevirt-write-summary=%t -S -o - %s | FileCheck %s
 ; RUN: FileCheck --check-prefix=SUMMARY %s < %t
 
 target datalayout = "e-p:64:64"
 target triple = "x86_64-unknown-linux-gnu"
 
 ; SUMMARY:      TypeIdMap:
 ; SUMMARY-NEXT:   typeid3:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           12,24:
 ; SUMMARY-NEXT:             Kind:            VirtualConstProp
 ; SUMMARY-NEXT:             Info:            0
 ; SUMMARY-NEXT:   typeid4:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           24,12:
 ; SUMMARY-NEXT:             Kind:            VirtualConstProp
 ; SUMMARY-NEXT:             Info:            0
 
 ; CHECK: [[CVT3A:.*]] = private constant { [8 x i8], i1 (i8*, i32, i32)*, [0 x i8] } { [8 x i8] zeroinitializer, i1 (i8*, i32, i32)* @vf0i1, [0 x i8] zeroinitializer }, !type !0
 @vt3a = constant i1 (i8*, i32, i32)* @vf0i1, !type !0
 

llvm/test/Transforms/WholeProgramDevirt/import-indir.ll

 ; SUMMARY-NEXT: TypeIdMap:
 ; SUMMARY-NEXT:   typeid1:
 ; SUMMARY-NEXT:     TTRes:
 ; SUMMARY-NEXT:       Kind:            Unsat
 ; SUMMARY-NEXT:       SizeM1BitWidth:  0
 ; SUMMARY-NEXT:     WPDRes:
 ; SUMMARY-NEXT:       0:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:       4:
 ; SUMMARY-NEXT:         Kind:            Indir
-; SUMMARY-NEXT:         SingleImplName:  ''
+; SUMMARY-NEXT:         SingleImplName:  ""
 ; SUMMARY-NEXT:         ResByArg:
 ; SUMMARY-NEXT:           :
 ; SUMMARY-NEXT:             Kind:            UniformRetVal
 ; SUMMARY-NEXT:             Info:            12
 ; SUMMARY-NEXT:           12:
 ; SUMMARY-NEXT:             Kind:            UniformRetVal
 ; SUMMARY-NEXT:             Info:            24
 ; SUMMARY-NEXT:           12,24:

llvm/test/tools/dsymutil/arch-option.test

 Processing of the -arch option happens at debug map parsing time, thus just
 looking at the dumped debug maps is enough to validate their effects.
 
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch all | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK
-RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch='*' | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK
+RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch="*" | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm64 | FileCheck %s -check-prefix=ARM64 -check-prefix=CHECK
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm | FileCheck %s -check-prefix=ARMV7S -check-prefix=ARMV7 -check-prefix=CHECK
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch armv7 | FileCheck %s -check-prefix=ARMV7 -check-prefix=CHECK
 RUN: llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm64 -arch armv7s | FileCheck %s -check-prefix=ARM64 -check-prefix=ARMV7S -check-prefix=CHECK
 RUN: not llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch arm42 2>&1 | FileCheck %s -check-prefix=BADARCH
 RUN: not llvm-dsymutil -oso-prepend-path %p -dump-debug-map %p/Inputs/fat-test.arm.dylib -arch i386 2>&1 | FileCheck %s -check-prefix=EMPTY
 
 
 ARMV7: ---
 ARMV7-NOT: ...
-ARMV7: triple:          'armv7-apple-darwin'
+ARMV7: triple:          "armv7-apple-darwin"
 ARMV7-NOT: ...
 ARMV7: sym: _armv7_var
 ARMV7-NOT: ---
 
 ARMV7S: ---
 ARMV7S-NOT: ...
-ARMV7S: triple:          'armv7s-apple-darwin'
+ARMV7S: triple:          "armv7s-apple-darwin"
 ARMV7S-NOT: ...
 ARMV7S: sym: _armv7s_var
 ARMV7S-NOT: ---
 
 ARM64: ---
 ARM64-NOT: ...
-ARM64: triple:          'arm64-apple-darwin'
+ARM64: triple:          "arm64-apple-darwin"
 ARM64-NOT: ...
 ARM64: sym: _arm64_var
 ARM64-NOT: ---
 
 CHECK: ...
 
 BADARCH: error: Unsupported cpu architecture: 'arm42'
 EMPTY: error: no architecture to link

llvm/test/tools/dsymutil/debug-map-parsing.test

 RUN: llvm-dsymutil -dump-debug-map -oso-prepend-path=%p %p/Inputs/basic.macho.x86_64 | FileCheck %s
 RUN: llvm-dsymutil -dump-debug-map -oso-prepend-path=%p %p/Inputs/basic-lto.macho.x86_64 | FileCheck %s --check-prefix=CHECK-LTO
 RUN: llvm-dsymutil -verbose -dump-debug-map -oso-prepend-path=%p %p/Inputs/basic-archive.macho.x86_64 | FileCheck %s --check-prefix=CHECK-ARCHIVE
 RUN: llvm-dsymutil -dump-debug-map %p/Inputs/basic.macho.x86_64 2>&1 | FileCheck %s --check-prefix=NOT-FOUND
 RUN: not llvm-dsymutil -dump-debug-map %p/Inputs/inexistant 2>&1 | FileCheck %s --check-prefix=NO-EXECUTABLE
 
 
 Check that We can parse the debug map of the basic executable.
 
 CHECK-NOT: error
 CHECK: ---
-CHECK: triple: 'x86_64-apple-darwin'
+CHECK: triple: "x86_64-apple-darwin"
 CHECK: binary-path:{{.*}}/Inputs/basic.macho.x86_64
 CHECK: filename:{{.*}}/Inputs/basic1.macho.x86_64.o
 CHECK-DAG: sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024
 CHECK: filename{{.*}}/Inputs/basic2.macho.x86_64.o
 CHECK-DAG:  sym: _baz, objAddr: 0x0000000000000310, binAddr: 0x0000000100001000, size: 0x00000000
 CHECK-DAG:  sym: _foo, objAddr: 0x0000000000000020, binAddr: 0x0000000100000ED0, size: 0x00000050
 CHECK-DAG:  sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F20, size: 0x00000017
 CHECK-DAG:  sym: _private_int, objAddr: 0x0000000000000560, binAddr: 0x0000000100001008, size: 0x00000000
 CHECK: filename{{.*}}/Inputs/basic3.macho.x86_64.o
 CHECK-DAG:  sym: _bar, objAddr: 0x0000000000000020, binAddr: 0x0000000100000F40, size: 0x00000050
 CHECK-DAG:  sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F90, size: 0x00000019
 CHECK-DAG:  sym: _val, binAddr: 0x0000000100001004, size: 0x00000000
 CHECK: ...
 
 
 Check that we can parse the debug-map of the basic-lto executable
 
 CHECK-LTO-NOT: error
 CHECK-LTO: ---
-CHECK-LTO: triple: 'x86_64-apple-darwin'
+CHECK-LTO: triple: "x86_64-apple-darwin"
 CHECK-LTO: binary-path:{{.*}}/Inputs/basic-lto.macho.x86_64
 CHECK-LTO: /Inputs/basic-lto.macho.x86_64.o
 CHECK-LTO-DAG:  sym: _bar, objAddr: 0x0000000000000050, binAddr: 0x0000000100000F90, size: 0x00000024
 CHECK-LTO-DAG:  sym: _baz, objAddr: 0x0000000000000658, binAddr: 0x0000000100001000, size: 0x00000000
 CHECK-LTO-DAG:  sym: _foo, objAddr: 0x0000000000000010, binAddr: 0x0000000100000F50, size: 0x00000040
 CHECK-LTO-DAG:  sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000F40, size: 0x00000010
 CHECK-LTO-DAG:  sym: _private_int, objAddr: 0x00000000000008E8, binAddr: 0x0000000100001008, size: 0x00000000
 CHECK-LTO-DAG:  sym: _val, objAddr: 0x00000000000008EC, binAddr: 0x0000000100001004, size: 0x00000000
 CHECK-LTO: ...
 
 Check thet we correctly handle debug maps with archive members (including only
 opening the archive once if mulitple of its members are used).
 
 CHECK-ARCHIVE:      trying to open {{.*}}basic-archive.macho.x86_64'
 CHECK-ARCHIVE-NEXT:   loaded file.
 CHECK-ARCHIVE-NEXT: trying to open {{.*}}/Inputs/basic1.macho.x86_64.o'
 CHECK-ARCHIVE-NEXT:   loaded file.
 CHECK-ARCHIVE-NEXT: trying to open {{.*}}/libbasic.a(basic2.macho.x86_64.o)'
 CHECK-ARCHIVE-NEXT:   opened new archive {{.*}}/libbasic.a'
 CHECK-ARCHIVE-NEXT:   found member in current archive.
 CHECK-ARCHIVE-NEXT: trying to open {{.*}}/libbasic.a(basic3.macho.x86_64.o)'
 CHECK-ARCHIVE-NEXT:   found member in current archive.
 CHECK-ARCHIVE: ---
-CHECK-ARCHIVE: triple: 'x86_64-apple-darwin'
+CHECK-ARCHIVE: triple: "x86_64-apple-darwin"
 CHECK-ARCHIVE: binary-path:{{.*}}/Inputs/basic-archive.macho.x86_64
 CHECK-ARCHIVE: /Inputs/basic1.macho.x86_64.o
 CHECK-ARCHIVE-DAG:  sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024
 CHECK-ARCHIVE: /Inputs/./libbasic.a(basic2.macho.x86_64.o)
 CHECK-ARCHIVE-DAG:  sym: _baz, objAddr: 0x0000000000000310, binAddr: 0x0000000100001000, size: 0x00000000
 CHECK-ARCHIVE-DAG:  sym: _foo, objAddr: 0x0000000000000020, binAddr: 0x0000000100000ED0, size: 0x00000050
 CHECK-ARCHIVE-DAG:  sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F20, size: 0x00000017
 CHECK-ARCHIVE-DAG:  sym: _private_int, objAddr: 0x0000000000000560, binAddr: 0x0000000100001004, size: 0x00000000
 CHECK-ARCHIVE: /Inputs/./libbasic.a(basic3.macho.x86_64.o)
 CHECK-ARCHIVE-DAG:  sym: _bar, objAddr: 0x0000000000000020, binAddr: 0x0000000100000F40, size: 0x00000050
 CHECK-ARCHIVE-DAG:  sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F90, size: 0x00000019
 CHECK-ARCHIVE-DAG:  sym: _val, binAddr: 0x0000000100001008, size: 0x00000000
 CHECK-ARCHIVE: ...
 
 Check that we warn about missing object files (this presumes that the files aren't
 present in the machine's /Inputs/ folder, which should be a pretty safe bet).
 
 NOT-FOUND: cannot open{{.*}}"/Inputs/basic1.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: cannot open{{.*}}"/Inputs/basic2.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: cannot open{{.*}}"/Inputs/basic3.macho.x86_64.o": {{[Nn]o}} such file
 NOT-FOUND: ---
-NOT-FOUND-NEXT: triple: 'x86_64-apple-darwin'
+NOT-FOUND-NEXT: triple: "x86_64-apple-darwin"
 NOT-FOUND-NEXT: binary-path:{{.*}}/Inputs/basic.macho.x86_64
 NOT-FOUND-NEXT: ...
 
 Check that we correctly error out on invalid executatble.
 
 NO-EXECUTABLE: cannot parse{{.*}}/inexistant": {{[Nn]o}} such file
 NO-EXECUTABLE-NOT: ---

llvm/test/tools/dsymutil/fat-binary-output.test

 RUN: llvm-dsymutil -f -verbose -no-output %p/Inputs/fat-test.dylib -oso-prepend-path %p | FileCheck %s
 
-This test doesn't produce any filesytstem output, we just look at the verbose
+This test doesn"t produce any filesytstem output, we just look at the verbose
 log output.
 
 For each arch in the binary, check that we emit the right triple with the right
 file and the right symbol inside it (each slice has a different symbol, so that
 means that the logic is looking at the right file slice too).
 
 After the link of each architecture, check that lipo is correctly invoked to
 generate the fat output binary.
 
-CHECK: triple:          'x86_64-apple-darwin'
-CHECK:   - filename:        {{'?}}[[INPUTS_PATH:.*]]fat-test.o
+CHECK: triple:          "x86_64-apple-darwin"
+CHECK:   - filename:        {{"?}}[[INPUTS_PATH:.*]]fat-test.o
 CHECK:   DW_AT_name{{.*}} "x86_64_var"
 
-CHECK: triple:          'i386-apple-darwin'
-CHECK:   - filename:        {{'?}}[[INPUTS_PATH]]fat-test.o
+CHECK: triple:          "i386-apple-darwin"
+CHECK:   - filename:        {{"?}}[[INPUTS_PATH]]fat-test.o
 CHECK:   DW_AT_name{{.*}} "i386_var"
 
-CHECK: triple:          'x86_64h-apple-darwin'
-CHECK:   - filename:        {{'?}}[[INPUTS_PATH]]fat-test.o
+CHECK: triple:          "x86_64h-apple-darwin"
+CHECK:   - filename:        {{"?}}[[INPUTS_PATH]]fat-test.o
 CHECK:   DW_AT_name{{.*}} "x86_64h_var"
 
 CHECK: Running lipo
 CHECK-NEXT: lipo -create
 CHECK-SAME  [[TMP_PATH:.*?]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf [[TMP_PATH]]fat-test.dylib.tmp{{......}}.dwarf
 CHECK-SAME: -segalign x86_64 20 -segalign i386 20 -segalign x86_64h 20
 CHECK-SAME: -output [[INPUTS_PATH]]fat-test.dylib.dwarf
 

llvm/test/tools/dsymutil/yaml-object-address-rewrite.test

 # RUN: llvm-dsymutil -dump-debug-map -oso-prepend-path=%p -y %s | FileCheck %s
 #
 # The YAML debug map bellow is the one from basic-archive.macho.x86_64 with
 # the object addresses set to zero. Check that the YAML import is able to
 # rewrite these addresses to the right values.
 #
 # CHECK: ---
-# CHECK-NEXT: triple:{{.*}}'x86_64-apple-darwin'
-# CHECK-NEXT: binary-path:{{.*}}''
+# CHECK-NEXT: triple:{{.*}}"x86_64-apple-darwin"
+# CHECK-NEXT: binary-path:{{.*}}""
 # CHECK-NEXT: objects:
 # CHECK-NEXT: filename:{{.*}}/Inputs/basic1.macho.x86_64.o
 # CHECK-NEXT: timestamp: 0
 # CHECK-NEXT: symbols:
 # CHECK-NEXT: sym: _main, objAddr: 0x0000000000000000, binAddr: 0x0000000100000EA0, size: 0x00000024
-# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic2.macho.x86_64.o)'
+# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic2.macho.x86_64.o)"
 # CHECK-NEXT: timestamp: 0
 # CHECK-NEXT: symbols:
 # CHECK-DAG:   sym: _foo, objAddr: 0x0000000000000020, binAddr: 0x0000000100000ED0, size: 0x00000050
 # CHECK-DAG:   sym: _private_int, objAddr: 0x0000000000000560, binAddr: 0x0000000100001004, size: 0x00000000
 # CHECK-DAG:   sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F20, size: 0x00000017
 # CHECK-DAG:   sym: _baz, objAddr: 0x0000000000000310, binAddr: 0x0000000100001000, size: 0x00000000
 # CHECK-NOT: { sym:
-# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic3.macho.x86_64.o)'
+# CHECK-NEXT: filename:{{.*}}/Inputs/./libbasic.a(basic3.macho.x86_64.o)"
 # CHECK-NEXT: timestamp: 0
 # CHECK-NEXT: symbols:
 # CHECK-DAG:   sym: _val, binAddr: 0x0000000100001008, size: 0x00000000
 # CHECK-DAG:   sym: _bar, objAddr: 0x0000000000000020, binAddr: 0x0000000100000F40, size: 0x00000050
 # CHECK-DAG:   sym: _inc, objAddr: 0x0000000000000070, binAddr: 0x0000000100000F90, size: 0x00000019
 # CHECK-NOT: { sym:
 # CHECK-NEXT: ...
 ---
-triple:          'x86_64-apple-darwin'
+triple:          "x86_64-apple-darwin"
 objects:
   - filename: /Inputs/basic1.macho.x86_64.o
     symbols:
       - { sym: _main, objAddr: 0x0, binAddr: 0x0000000100000EA0, size: 0x00000024 }
   - filename: /Inputs/./libbasic.a(basic2.macho.x86_64.o)
     symbols:
       - { sym: _foo, objAddr: 0x0, binAddr: 0x0000000100000ED0, size: 0x00000050 }
       - { sym: _private_int, objAddr: 0x0, binAddr: 0x0000000100001004, size: 0x00000000 }
       - { sym: _inc, objAddr: 0x0, binAddr: 0x0000000100000F20, size: 0x00000017 }
       - { sym: _baz, objAddr: 0x0, binAddr: 0x0000000100001000, size: 0x00000000 }
   - filename: /Inputs/./libbasic.a(basic3.macho.x86_64.o)
     symbols:
       - { sym: _val, binAddr: 0x0000000100001008, size: 0x00000000 }
       - { sym: _bar, objAddr: 0x0, binAddr: 0x0000000100000F40, size: 0x00000050 }
       - { sym: _inc, objAddr: 0x0, binAddr: 0x0000000100000F90, size: 0x00000019 }
 ...

llvm/test/tools/llvm-xray/X86/convert-fdr-to-yaml.txt

 ; RUN: llvm-xray convert %S/Inputs/fdr-log-version-1.xray -f=yaml -o - | FileCheck %s
 
 ; CHECK:      ---
 ; CHECK-NEXT: header:
 ; CHECK-NEXT:   version:         1
 ; CHECK-NEXT:   type:            1
 ; CHECK-NEXT:   constant-tsc:    true
 ; CHECK-NEXT:   nonstop-tsc:     true
 ; CHECK-NEXT:   cycle-frequency: 5678
 ; CHECK-NEXT: records:
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407340 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407346 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407347 }
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407387 }
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407437 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407467 }
-; CHECK-NEXT:   - { type: 0, func-id: 4, function: '4', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407492 }
-; CHECK-NEXT:   - { type: 0, func-id: 5, function: '5', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407517 }
-; CHECK-NEXT:   - { type: 0, func-id: 5, function: '5', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407542 }
-; CHECK-NEXT:   - { type: 0, func-id: 268435455, function: '268435455', cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407552 }
-; CHECK-NEXT:   - { type: 0, func-id: 268435455, function: '268435455', cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407562 }
-; CHECK-NEXT:   - { type: 0, func-id: 6, function: '6', cpu: 6, thread: 5, kind: function-enter, tsc: 7238225556407682 }
-; CHECK-NEXT:   - { type: 0, func-id: 6, function: '6', cpu: 6, thread: 5, kind: function-exit, tsc: 7238225556407755 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407340 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407346 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407347 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407387 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407437 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407467 }
+; CHECK-NEXT:   - { type: 0, func-id: 4, function: "4", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407492 }
+; CHECK-NEXT:   - { type: 0, func-id: 5, function: "5", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407517 }
+; CHECK-NEXT:   - { type: 0, func-id: 5, function: "5", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407542 }
+; CHECK-NEXT:   - { type: 0, func-id: 268435455, function: "268435455", cpu: 5, thread: 5, kind: function-enter, tsc: 7238225556407552 }
+; CHECK-NEXT:   - { type: 0, func-id: 268435455, function: "268435455", cpu: 5, thread: 5, kind: function-exit, tsc: 7238225556407562 }
+; CHECK-NEXT:   - { type: 0, func-id: 6, function: "6", cpu: 6, thread: 5, kind: function-enter, tsc: 7238225556407682 }
+; CHECK-NEXT:   - { type: 0, func-id: 6, function: "6", cpu: 6, thread: 5, kind: function-exit, tsc: 7238225556407755 }
 ; CHECK-NEXT: ...

llvm/test/tools/llvm-xray/X86/convert-roundtrip.yaml

 #CHECK:       ---
 #CHECK-NEXT:  header:
 #CHECK-NEXT:    version: 1
 #CHECK-NEXT:    type: 0
 #CHECK-NEXT:    constant-tsc: true
 #CHECK-NEXT:    nonstop-tsc: true
 #CHECK-NEXT:    cycle-frequency: 2601000000
 #CHECK-NEXT:  records:
-#CHECK-NEXT:    - { type: 0, func-id: 1, function: '1', cpu: 1, thread: 111, kind: function-enter, tsc: 10001 }
-#CHECK-NEXT:    - { type: 0, func-id: 1, function: '1', cpu: 1, thread: 111, kind: function-exit, tsc: 10100 }
+#CHECK-NEXT:    - { type: 0, func-id: 1, function: "1", cpu: 1, thread: 111, kind: function-enter, tsc: 10001 }
+#CHECK-NEXT:    - { type: 0, func-id: 1, function: "1", cpu: 1, thread: 111, kind: function-exit, tsc: 10100 }
 #CHECK-NEXT:  ...

llvm/test/tools/llvm-xray/X86/convert-to-yaml.txt

 ; RUN: llvm-xray convert %S/Inputs/naive-log-simple.xray -f=yaml -o - | FileCheck %s
 
 ; CHECK:      ---
 ; CHECK-NEXT: header:
 ; CHECK-NEXT:   version:         1
 ; CHECK-NEXT:   type:            0
 ; CHECK-NEXT:   constant-tsc:    true
 ; CHECK-NEXT:   nonstop-tsc:     true
 ; CHECK-NEXT:   cycle-frequency: 2601000000
 ; CHECK-NEXT: records:
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
 ; CHECK-NEXT: ...

llvm/test/tools/llvm-xray/X86/convert-with-standalone-instrmap.txt

 ; RUN: llvm-xray convert -m %S/Inputs/elf64-objcopied-instrmap.bin -y %S/Inputs/naive-log-simple.xray -f=yaml -o - 2>&1 | FileCheck %s
 
 ; CHECK:      ---
 ; CHECK-NEXT: header:
 ; CHECK-NEXT:   version:         1
 ; CHECK-NEXT:   type:            0
 ; CHECK-NEXT:   constant-tsc:    true
 ; CHECK-NEXT:   nonstop-tsc:     true
 ; CHECK-NEXT:   cycle-frequency: 2601000000
 ; CHECK-NEXT: records:
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '@(41caa0)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '@(41ca70)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '@(41ca70)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '@(41ca40)', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '@(41ca40)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '@(41caa0)', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "@(41caa0)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "@(41ca70)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "@(41ca70)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "@(41ca40)", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "@(41ca40)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "@(41caa0)", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
 ; CHECK-NEXT: ...

llvm/test/tools/llvm-xray/X86/convert-with-yaml-instrmap.txt

 ; RUN: llvm-xray convert -m %S/Inputs/simple-xray-instrmap.yaml %S/Inputs/naive-log-simple.xray -f=yaml -o - | FileCheck %s
 
 ; CHECK:      ---
 ; CHECK-NEXT: header:
 ; CHECK-NEXT:   version:         1
 ; CHECK-NEXT:   type:            0
 ; CHECK-NEXT:   constant-tsc:    true
 ; CHECK-NEXT:   nonstop-tsc:     true
 ; CHECK-NEXT:   cycle-frequency: 2601000000
 ; CHECK-NEXT: records:
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
-; CHECK-NEXT:   - { type: 0, func-id: 2, function: '2', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
-; CHECK-NEXT:   - { type: 0, func-id: 1, function: '1', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
-; CHECK-NEXT:   - { type: 0, func-id: 3, function: '3', cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841453914 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454542 }
+; CHECK-NEXT:   - { type: 0, func-id: 2, function: "2", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454670 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-enter, tsc: 3315356841454762 }
+; CHECK-NEXT:   - { type: 0, func-id: 1, function: "1", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841454802 }
+; CHECK-NEXT:   - { type: 0, func-id: 3, function: "3", cpu: 37, thread: 84697, kind: function-exit, tsc: 3315356841494828 }
 ; CHECK-NEXT: ...

llvm/unittests/ObjectYAML/YAMLTest.cpp

 } // end namespace llvm
 
 TEST(ObjectYAML, BinaryRef) {
   BinaryHolder BH;
   SmallVector<char, 32> Buf;
   llvm::raw_svector_ostream OS(Buf);
   yaml::Output YOut(OS);
   YOut << BH;
-  EXPECT_NE(OS.str().find("''"), StringRef::npos);
+  EXPECT_NE(OS.str().find("\"\""), StringRef::npos);
 }

llvm/unittests/Support/YAMLIOTest.cpp

struct StringTypes {
   llvm::StringRef str4;
   llvm::StringRef str5;
   llvm::StringRef str6;
   llvm::StringRef str7;
   llvm::StringRef str8;
   llvm::StringRef str9;
   llvm::StringRef str10;
   llvm::StringRef str11;
+  llvm::StringRef str12;
+  llvm::StringRef str13;
   std::string stdstr1;
   std::string stdstr2;
   std::string stdstr3;
   std::string stdstr4;
   std::string stdstr5;
   std::string stdstr6;
   std::string stdstr7;
   std::string stdstr8;
   std::string stdstr9;
   std::string stdstr10;
   std::string stdstr11;
+  std::string stdstr12;
+  std::string stdstr13;
 };
 
 namespace llvm {
 namespace yaml {
   template <>
   struct MappingTraits<StringTypes> {
     static void mapping(IO &io, StringTypes& st) {
       io.mapRequired("str1",      st.str1);
       io.mapRequired("str2",      st.str2);
       io.mapRequired("str3",      st.str3);
       io.mapRequired("str4",      st.str4);
       io.mapRequired("str5",      st.str5);
       io.mapRequired("str6",      st.str6);
       io.mapRequired("str7",      st.str7);
       io.mapRequired("str8",      st.str8);
       io.mapRequired("str9",      st.str9);
       io.mapRequired("str10",     st.str10);
       io.mapRequired("str11",     st.str11);
+      io.mapRequired("str12",     st.str12);
+      io.mapRequired("str13",     st.str13);
       io.mapRequired("stdstr1",   st.stdstr1);
       io.mapRequired("stdstr2",   st.stdstr2);
       io.mapRequired("stdstr3",   st.stdstr3);
       io.mapRequired("stdstr4",   st.stdstr4);
       io.mapRequired("stdstr5",   st.stdstr5);
       io.mapRequired("stdstr6",   st.stdstr6);
       io.mapRequired("stdstr7",   st.stdstr7);
       io.mapRequired("stdstr8",   st.stdstr8);
       io.mapRequired("stdstr9",   st.stdstr9);
       io.mapRequired("stdstr10",  st.stdstr10);
       io.mapRequired("stdstr11",  st.stdstr11);
+      io.mapRequired("stdstr12",  st.stdstr12);
+      io.mapRequired("stdstr13",  st.stdstr13);
     }
   };
 }
 }
 
 TEST(YAMLIO, TestReadWriteStringTypes) {
+  static const char quoted[34] =
+      "\001\002\003\004\005\006\007\010\011\012\013\014\015\016\017"
+      "\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036"
+      "\037\000\177";
+  static const char unquoted[] =
+      "abcdefghijklmnopqrstuvwxyzABCDEFGHIJKLMNOPQRSTUVWXYZ"
+      "0123456789_-/^.,";
   std::string intermediate;
   {
     StringTypes map;
     map.str1 = "'aaa";
     map.str2 = "\"bbb";
     map.str3 = "`ccc";
     map.str4 = "@ddd";
     map.str5 = "";
     map.str6 = "0000000004000000";
     map.str7 = "true";
     map.str8 = "FALSE";
     map.str9 = "~";
     map.str10 = "0.2e20";
     map.str11 = "0x30";
+    map.str12 = unquoted;
+    map.str13 = llvm::StringRef(quoted, 33);
     map.stdstr1 = "'eee";
     map.stdstr2 = "\"fff";
     map.stdstr3 = "`ggg";
     map.stdstr4 = "@hhh";
     map.stdstr5 = "";
     map.stdstr6 = "0000000004000000";
     map.stdstr7 = "true";
     map.stdstr8 = "FALSE";
     map.stdstr9 = "~";
     map.stdstr10 = "0.2e20";
     map.stdstr11 = "0x30";
+    map.stdstr12 = unquoted;
+    map.stdstr13 = std::string(quoted, 33);
 
     llvm::raw_string_ostream ostr(intermediate);
     Output yout(ostr);
     yout << map;
   }
 
   llvm::StringRef flowOut(intermediate);
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'''aaa"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'\"bbb'"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'`ccc'"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'@ddd'"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("''\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0000000004000000'\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'true'\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'FALSE'\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'~'\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0.2e20'\n"));
-  EXPECT_NE(llvm::StringRef::npos, flowOut.find("'0x30'\n"));
-  EXPECT_NE(std::string::npos, flowOut.find("'''eee"));
-  EXPECT_NE(std::string::npos, flowOut.find("'\"fff'"));
-  EXPECT_NE(std::string::npos, flowOut.find("'`ggg'"));
-  EXPECT_NE(std::string::npos, flowOut.find("'@hhh'"));
-  EXPECT_NE(std::string::npos, flowOut.find("''\n"));
-  EXPECT_NE(std::string::npos, flowOut.find("'0000000004000000'\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"'aaa\""));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"\\\"bbb\""));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"`ccc\""));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"@ddd\""));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0000000004000000\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"true\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"FALSE\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"~\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0.2e20\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find("\"0x30\"\n"));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find(unquoted));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find(
+      "\"\\x01\\x02\\x03\\x04\\x05\\x06\\x07\\x08\\x09\\x0A\\x0B\\x0C\\x0D\\x0E"
+      "\\x0F\\x10\\x11\\x12\\x13\\x14\\x15\\x16\\x17\\x18\\x19\\x1A\\x1B\\x1C"
+      "\\x1D\\x1E\\x1F\\x00\\x7F\""));
+  EXPECT_NE(std::string::npos, flowOut.find("\"'eee\""));
+  EXPECT_NE(std::string::npos, flowOut.find("\"\\\"fff\""));
+  EXPECT_NE(std::string::npos, flowOut.find("\"`ggg\""));
+  EXPECT_NE(std::string::npos, flowOut.find("\"@hhh\""));
+  EXPECT_NE(std::string::npos, flowOut.find("\"\"\n"));
+  EXPECT_NE(std::string::npos, flowOut.find("\"0000000004000000\"\n"));
+  EXPECT_NE(std::string::npos, flowOut.find(unquoted));
+  EXPECT_NE(llvm::StringRef::npos, flowOut.find(
+      "\"\\x01\\x02\\x03\\x04\\x05\\x06\\x07\\x08\\x09\\x0A\\x0B\\x0C\\x0D\\x0E"
+      "\\x0F\\x10\\x11\\x12\\x13\\x14\\x15\\x16\\x17\\x18\\x19\\x1A\\x1B\\x1C"
+      "\\x1D\\x1E\\x1F\\x00\\x7F\""));
 
   {
     Input yin(intermediate);
     StringTypes map;
     yin >> map;
 
     EXPECT_FALSE(yin.error());
     EXPECT_TRUE(map.str1.equals("'aaa"));
     EXPECT_TRUE(map.str2.equals("\"bbb"));
     EXPECT_TRUE(map.str3.equals("`ccc"));
     EXPECT_TRUE(map.str4.equals("@ddd"));
     EXPECT_TRUE(map.str5.equals(""));
     EXPECT_TRUE(map.str6.equals("0000000004000000"));
+    EXPECT_TRUE(map.str12.equals(unquoted));
+    EXPECT_TRUE(map.str13.equals(llvm::StringRef(quoted, 33)));
     EXPECT_TRUE(map.stdstr1 == "'eee");
     EXPECT_TRUE(map.stdstr2 == "\"fff");
     EXPECT_TRUE(map.stdstr3 == "`ggg");
     EXPECT_TRUE(map.stdstr4 == "@hhh");
     EXPECT_TRUE(map.stdstr5 == "");
     EXPECT_TRUE(map.stdstr6 == "0000000004000000");
+    EXPECT_TRUE(map.stdstr12 == unquoted);
+    EXPECT_TRUE(map.stdstr13 == std::string(quoted, 33));
   }
 }
 
 //===----------------------------------------------------------------------===//
 //  Test ScalarEnumerationTraits
 //===----------------------------------------------------------------------===//
 
 enum Colors {