This patch completely replaces the scheduling information for the SandyBridge and the Haswell architecture targets by completely modifying the files: X86SchedSandyBridge.td and X86SchedHaswell.td located under the X86 Target.
The Haswell and SandyBridge architects have provided us with the correct information about each instruction and I use it to replace existing incorrect instructions scheduling and to add missing instructions in the two files.
Please note that the patch extensively affects the X86 MC instr scheduling.
The updated and extended information about each instruction in HSW and SNB includes the following data:
- static latency of instruction
- number of uOps from which the instruction consists of
- all ports used by the instruction
For example, the following code dictates that instructions, ADC64mr, ADC8mr, SBB64mr, SBB8mr have a static latency of 9 cycles. Each of these instructions is decoded into 6 micro operations whic use ports 4, ports 2 or 3 and port 0 and ports 0 or 1 or 5:
def SBWriteResGroup94 : SchedWriteRes<[SBPort4,SBPort23,SBPort0,SBPort015]> {
let Latency = 9; let NumMicroOps = 6; let ResourceCycles = [1,2,2,1];
}
def: InstRW<[SBWriteResGroup94], (instregex "ADC64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "ADC8mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB64mr")>;
def: InstRW<[SBWriteResGroup94], (instregex "SBB8mr")>;
An alternative would be to call out those instructions using 'UnSupported'. This will let you set CompleteModel = 1.
Please see - https://github.com/llvm-mirror/llvm/blob/master/lib/Target/AArch64/AArch64SchedFalkor.td#L65