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avt77 (Andrew V. Tischenko)
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Apr 11 2016, 3:46 AM (166 w, 10 h)

Recent Activity

Aug 30 2018

avt77 added a comment to D51492: [X86][BtVer2] Fix WriteFShuffle256 schedule write info..

I don't see any changes for VEXTRACTF128 in tests. Do you really need this JWriteVecExtractF128? If YES you should add the corresponding test.

Aug 30 2018, 9:54 AM

Aug 29 2018

avt77 committed rL341024: [X86] Improved sched model for X86 CMPXCHG* instructions..
[X86] Improved sched model for X86 CMPXCHG* instructions.
Aug 29 2018, 11:27 PM
avt77 closed D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 29 2018, 11:27 PM

Aug 28 2018

avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

The issue with SB uops was fixed.

Aug 28 2018, 10:34 PM
avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 28 2018, 10:18 AM

Aug 27 2018

avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

Now we have WriteCMPXCHGRMW accordingly to craig.topper requirement.

Aug 27 2018, 1:39 PM

Aug 22 2018

avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 22 2018, 5:12 AM
avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 22 2018, 2:28 AM

Aug 21 2018

avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 21 2018, 7:09 AM

Aug 17 2018

avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

:start: means the timer was started

In some cases, the ChildTime is already non-zero at the "start" point; what does that mean?

Aug 17 2018, 4:15 AM
avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

I fixed the issue with WriteCMPXCHGLd - tnx to craig.topper.

Aug 17 2018, 3:46 AM

Aug 16 2018

avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

I mean, which of the callers of startFrontendTimer() is calling it with a pointer to std::declval()?

Aug 16 2018, 4:50 AM
avt77 updated the diff for D47196: [Time-report ](2): Recursive timers in Clang.

The ability to produce debug output for 'ftiming' was added. As result now it's possible to check places where timers start/stop and for what functions it's being done (see changes in Utils.h).

Aug 16 2018, 4:27 AM

Aug 14 2018

avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

I fixed sched parameters accordingly to craig.topper suggestions.

Aug 14 2018, 4:51 AM

Aug 13 2018

avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

The code was re-based. We have 2 changed tests for SandyBridge (Generic). I did not find the proper numbers in Intel SDMs or on Agner site that's why I don't know what's beter the new results or the old ones. The old sched model does not use SBPort4 for memory ops and that looks strange for me. Could anyone help me with these tests?

Aug 13 2018, 4:29 AM

Aug 9 2018

avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

Currently we have 93 warnings for X86 CPU models:

Aug 9 2018, 4:48 AM
avt77 committed rL339321: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions..
[X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.
Aug 9 2018, 2:24 AM
avt77 closed D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.
Aug 9 2018, 2:24 AM
avt77 added a comment to D45619: [Time-report] (1) Use special new Clang flag 'FrontendTimesIsEnabled' instead of 'llvm::TimePassesIsEnabled' inside -ftime-report feature.

I'm unclear why the we would want to assign clang's FrontendTimesIsEnabled from inside CodeGenAction. If I'm understanding the intentions here, the goal was to add more timing infrastructure to clang. But if the enabling is tied to CodeGenAction, then doesn't that mean any new clang timers wouldn't work under -fsyntax-only?

Aug 9 2018, 1:28 AM

Aug 8 2018

avt77 updated the diff for D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

The patch was rebased after D49912.

Aug 8 2018, 2:52 AM

Aug 7 2018

avt77 committed rL339145: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.
[X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions
Aug 7 2018, 7:37 AM
avt77 closed D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.
Aug 7 2018, 7:37 AM
avt77 updated the diff for D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.

All last requirements were fixed.

Aug 7 2018, 3:32 AM

Aug 3 2018

avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

I think you're almost there but D49912 must be completed and committed first

Aug 3 2018, 7:37 AM
avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

"0.0040" is four milliseconds? You're probably crediting time incorrectly, somehow. Can you tell which FrontendTimeRAII the time is coming from?

Aug 3 2018, 7:33 AM
avt77 updated the diff for D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

The comment was added:

Aug 3 2018, 4:37 AM

Aug 2 2018

avt77 updated the diff for D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

XADD*rr instrs were added: I did not add rm version because we should decide how to do it beter:

Aug 2 2018, 8:13 AM
avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

Tag XADD instructions with WriteXCHG as well?

Aug 2 2018, 4:23 AM
avt77 updated the diff for D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.

The new tests were updated, xadd* tests were added.

Aug 2 2018, 4:04 AM
avt77 added inline comments to D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.
Aug 2 2018, 2:18 AM
avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 2 2018, 12:54 AM

Aug 1 2018

avt77 updated the diff for D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.

The WriteCMPXCHGLd was implemented.

Aug 1 2018, 9:20 AM
avt77 updated the diff for D47196: [Time-report ](2): Recursive timers in Clang.

efriedma, I removed redundant RAII objects but I still have the following:

Aug 1 2018, 8:11 AM
avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

Tag XADD instructions with WriteXCHG as well?

Aug 1 2018, 5:03 AM
avt77 committed rL338507: [X86] Improved sched models for X86 BT*rr instructions..
[X86] Improved sched models for X86 BT*rr instructions.
Aug 1 2018, 3:25 AM
avt77 closed D49243: [X86] Improved sched models for X86 BT*rr instructions.
Aug 1 2018, 3:25 AM
avt77 added inline comments to D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Aug 1 2018, 2:05 AM

Jul 31 2018

avt77 created D50070: [X86] Improved sched models for X86 CMPXCHG* instructions.
Jul 31 2018, 7:58 AM
avt77 committed rL338365: [X86] Improved sched models for X86 BT*rr instructions..
[X86] Improved sched models for X86 BT*rr instructions.
Jul 31 2018, 5:34 AM
avt77 updated the diff for D47196: [Time-report ](2): Recursive timers in Clang.

Accordingly to efriedma suggestion I removed start/stopFrontendTimer where it's possible and inserted FrontendTimeRAII in several new places. As result the patch becomes bigger and bigger. And as another result I got output like here (on compiler bootstrap):
....
0.5920 (165) _ZSt7declvalv (*)
0.5960 (155) _ZSt7declvalv (*)
0.5960 (162) _ZSt7declvalv (*)
0.6000 (167) _ZSt7declvalv (*)
0.6040 (155) _ZSt7declvalv (*)
0.6040 (160) _ZSt7declvalv (*)
0.6040 (169) _ZSt7declvalv (*)
....
(the above is grep output from build log file)

Jul 31 2018, 5:25 AM
avt77 committed rL338359: [X86] Improved sched models for X86 SHLD/SHRD* instructions..
[X86] Improved sched models for X86 SHLD/SHRD* instructions.
Jul 31 2018, 3:15 AM

Jul 30 2018

avt77 added inline comments to D49611: [X86] Improved sched models for X86 SHLD/SHRD* instructions.
Jul 30 2018, 6:09 AM
avt77 added inline comments to D47196: [Time-report ](2): Recursive timers in Clang.
Jul 30 2018, 12:47 AM

Jul 28 2018

avt77 added inline comments to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.
Jul 28 2018, 5:08 AM
avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

The SLM & btver2 - are those placeholders, or those are real values from agner?

Jul 28 2018, 4:47 AM

Jul 27 2018

avt77 updated the diff for D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.

I updated the tests accordingly to Roman's request.

Jul 27 2018, 8:30 AM
avt77 added inline comments to D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.
Jul 27 2018, 6:27 AM
avt77 created D49912: [X86] MCA tests for XCHG*, XADD* and CMPXCHG* instructions.
Jul 27 2018, 5:53 AM
avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

But of course you're right: we need such mca tests. I'll try to prepare such tests for XCHG* and CMPXCHG* instrs (I've just started to work with CMPXCHG*).

Jul 27 2018, 2:39 AM
avt77 added a comment to D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.

But we have a lot of XCHG tests in other places. For example:

Jul 27 2018, 1:01 AM

Jul 26 2018

avt77 created D49861: [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.
Jul 26 2018, 8:41 AM
avt77 updated the diff for D49611: [X86] Improved sched models for X86 SHLD/SHRD* instructions.

WriteShiftDouble was removed, other comments were fixed.

Jul 26 2018, 5:38 AM
avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

efriedma, do you have any other comments/requirements?

Jul 26 2018, 3:00 AM

Jul 24 2018

avt77 updated the diff for D49611: [X86] Improved sched models for X86 SHLD/SHRD* instructions.

I fixed all requirements from Simon - even the SLM test was fixed.

Jul 24 2018, 7:18 AM
avt77 abandoned D47766: Removing unsupported resources from sched model.

The main idea of this patch is implemented in D47763.

Jul 24 2018, 12:41 AM
avt77 added a comment to D47637: Check Sched Class tables at generation time.

Anything to do to get this going? Or did this got replaced by some other differential? D48222?

Jul 24 2018, 12:39 AM

Jul 23 2018

avt77 updated the diff for D49243: [X86] Improved sched models for X86 BT*rr instructions.

We decided that this patch won't include memory versions of instrs that's why I simply fixed tiny requirements like "place of WriteBitTest" and "removing of the TableGen CodeGenSchedule diffs".

Jul 23 2018, 4:07 AM

Jul 20 2018

avt77 created D49611: [X86] Improved sched models for X86 SHLD/SHRD* instructions.
Jul 20 2018, 11:39 AM
avt77 committed rL337537: Improved sched model for X86 BSWAP* instrs..
Improved sched model for X86 BSWAP* instrs.
Jul 20 2018, 2:44 AM
avt77 closed D49477: [X86] Improved sched models for X86 BSWAP* instructions..
Jul 20 2018, 2:44 AM

Jul 19 2018

avt77 updated the diff for D49477: [X86] Improved sched models for X86 BSWAP* instructions..

I removed the changes from D48222.

Jul 19 2018, 5:31 AM
avt77 added a comment to D49477: [X86] Improved sched models for X86 BSWAP* instructions..

Drop the tablegen CodeGenSchedule changes

Jul 19 2018, 5:24 AM
avt77 updated the diff for D49477: [X86] Improved sched models for X86 BSWAP* instructions..

Comments from Simon and Roman were resolved.

Jul 19 2018, 3:41 AM

Jul 18 2018

avt77 updated the diff for D47196: [Time-report ](2): Recursive timers in Clang.

I added required comments and did the required changes.

Jul 18 2018, 7:09 AM
avt77 created D49477: [X86] Improved sched models for X86 BSWAP* instructions..
Jul 18 2018, 5:34 AM

Jul 17 2018

avt77 updated the diff for D48222: Check Sched Class tables at generation time - 2.

I replaced 'auto' with real types accordingly to Simon's request.

Jul 17 2018, 10:04 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

What happened to the BSWAP patch? Compared to BT (D49243) it should have been pretty trivial to implement.

In fact we have there very similar issues but even with rr versions: we should separate implementations for different sizes 16/32/64. I'm going to complete it tomorrow. But again - most probably it will be w/o memory operands support like in D49243.

Jul 17 2018, 8:26 AM
avt77 updated the diff for D49243: [X86] Improved sched models for X86 BT*rr instructions.

Now we use WriteRes instead of *WriteResPair.
Folded versions of the intrs will be implemented in the next patches.

Jul 17 2018, 6:21 AM
avt77 added a comment to D49243: [X86] Improved sched models for X86 BT*rr instructions.

http://www.agner.org/optimize/instruction_tables.pdf, page 202, "Intel Haswell", "List of instruction timings and μop breakdown" appears to list all the BT* as having latency of 1.

I mixed columns for latency and throughput: latency is missed.

Jul 17 2018, 2:46 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

(Would be great if the checkbox 'done' in notes would be getting checked, too)

Jul 17 2018, 2:28 AM
avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

Adding startFrontendTimer/stopFrontendTimer helps a little, but it's still difficult to match a given startFrontendTimer to the corresponding stopFrontendTimer because they're in completely different functions in some cases. Do they really need to be scattered like that? If they do, please add comments so someone reading the code can match them up.

Jul 17 2018, 1:16 AM

Jul 16 2018

avt77 added a comment to D49243: [X86] Improved sched models for X86 BT*rr instructions.

Hi All,
I need your help!

Jul 16 2018, 7:40 AM
avt77 updated the diff for D48222: Check Sched Class tables at generation time - 2.

It seems I fixed all issues raised by lebedev.ri. The open question is: should I remove the second check inside checkSchedClasses? I'm sure there is a way to get default values for such SchedWrites like WriteALU, WriteFAdd, etc. but I don't know at the moment how to do it. Please, help.

Jul 16 2018, 7:31 AM
avt77 added inline comments to D48222: Check Sched Class tables at generation time - 2.
Jul 16 2018, 7:23 AM
avt77 added inline comments to D48222: Check Sched Class tables at generation time - 2.
Jul 16 2018, 1:53 AM
avt77 added inline comments to D49243: [X86] Improved sched models for X86 BT*rr instructions.
Jul 16 2018, 12:41 AM

Jul 13 2018

avt77 updated the diff for D49243: [X86] Improved sched models for X86 BT*rr instructions.

I renamed WriteBTr with WriteBitTest.
I could not add memory version of the instructions because there were some issues. For example, if we have

Jul 13 2018, 7:45 AM
avt77 added a comment to D49243: [X86] Improved sched models for X86 BT*rr instructions.

I'm assuming that you have run ninja check-llvm-tools-llvm-mca-x86 and it was ok. (the test coverage seems to be ok as-is.)

Jul 13 2018, 2:06 AM

Jul 12 2018

avt77 created D49243: [X86] Improved sched models for X86 BT*rr instructions.
Jul 12 2018, 8:30 AM
avt77 updated the diff for D48222: Check Sched Class tables at generation time - 2.

Now the patch keeps only infrastructure changes to produce new TableGen warns about sched models.

Jul 12 2018, 3:08 AM

Jul 11 2018

avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

Please can you pul out the BSWAP change into its own patch for review?

Jul 11 2018, 7:50 AM

Jul 10 2018

avt77 updated the diff for D47196: [Time-report ](2): Recursive timers in Clang.

I fixed all issues raised by efriedma: GlobalDecl(FD), function body, class names, etc. Many tnx for your help.

Jul 10 2018, 7:26 AM
avt77 added a comment to D47196: [Time-report ](2): Recursive timers in Clang.

Can you give an example of what the output looks like?

Jul 10 2018, 7:21 AM

Jul 9 2018

avt77 updated the diff for D48222: Check Sched Class tables at generation time - 2.

I fixed warns for BSWAP instrs (see changes in X86*.td files). If this approach is OK I'll fix other instrs.

Jul 9 2018, 5:28 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

At the moment we have the following warns for X86:

Jul 9 2018, 3:56 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

In fact we have the warnings for 2 Targets only:

Jul 9 2018, 1:33 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

@avt77 Next step is probably to start briefly collating the instructions causing the warnings and investigate how best to fix them (list them here, raise bugs etc.). The aim would be to see if we can remove ALL these warnings before we consider committing this patch - its probably time to add the maintainers for each target that has warnings so they can be investigated?

Jul 9 2018, 12:14 AM

Jul 3 2018

avt77 updated the diff for D48222: Check Sched Class tables at generation time - 2.

Now it's almost completed but should deal with deafult Latency value: hope to implement it soon. (The current version does not produce yet warning about identical uOps & Latency during compiler build: maybe it's OK?)

Jul 3 2018, 7:25 AM
avt77 added a comment to D48222: Check Sched Class tables at generation time - 2.

Hi! I was out for 2 weeks that's why I did not do anything here. Is it still interesting for you? I'm going to publish an update asap.
But the question is: how to get latnency/uop from CodeGenSchedClass ?

Jul 3 2018, 4:12 AM

Jun 15 2018

avt77 created D48222: Check Sched Class tables at generation time - 2.
Jun 15 2018, 9:07 AM

Jun 7 2018

avt77 added a comment to D47766: Removing unsupported resources from sched model.

9>>! In D47766#1124708, @RKSimon wrote:

I really don't like the idea of a separate file - I think the models need to stay self contained. @courbet 's approach in D47763 seems a lot tidier

Jun 7 2018, 6:55 AM
avt77 added a comment to D47763: [X86] Explicitly mark unsupported zmm classes in scheduling models..

Introduce X86WriteRes(|Pair)Unsupported.

Jun 7 2018, 6:36 AM
avt77 added a comment to D47637: Check Sched Class tables at generation time.

If I use one check only (" // Check if an instruction is always overriden (candidate for a new class?)") I see warnings for p9model only.
At the moment, I'm learning debug output related to generation of all these tables and hope to come up with some realistic logging soon.

Jun 7 2018, 6:13 AM
avt77 added a comment to D47637: Check Sched Class tables at generation time.

Simon, I have some troubles with slack connection that's why I read your message only now :-( I'll back with answer asap.

Jun 7 2018, 6:05 AM
avt77 added a comment to D47766: Removing unsupported resources from sched model.

Then I'm not sure if we win a lot from this as it makes things less explicit, though I agree that it slightly reduces code duplication.

Jun 7 2018, 1:01 AM

Jun 6 2018

avt77 added a comment to D47766: Removing unsupported resources from sched model.

Of course not. First of all, I suggest to put AVX2 and AVX512 instructions in separate files and to use them in models which don't support AVX2 and/or AVX512. Etc.

Jun 6 2018, 8:50 AM
avt77 updated the diff for D47766: Removing unsupported resources from sched model.

Obviously, the idea was to use one include file for all targets. But it did not work in the first version of the patch. Now I did a "dirty hack" in TableGen to be able to do it. It works for 2 CPUs and obviously it should work for others. The usage is very simply: the common include file should keep the common unsupported instructions while the specific onces should be inserted into the specific .td files.

Jun 6 2018, 8:13 AM

Jun 5 2018

avt77 added a comment to D47637: Check Sched Class tables at generation time.

And the last question. Again, in P9Model we have

Jun 5 2018, 8:02 AM
avt77 added a comment to D47637: Check Sched Class tables at generation time.

Next, we have for P9Model only:

Jun 5 2018, 7:58 AM
avt77 added a comment to D47637: Check Sched Class tables at generation time.

Something is wrong with current diagnostic. Fro example, we have

Jun 5 2018, 7:39 AM