- User Since
- Apr 11 2016, 3:46 AM (75 w, 6 d)
Thu, Sep 21
Wed, Sep 20
Tue, Sep 19
I fixed issues raised by Craig and Simon.
It seems nobody wants to change the default value of the switch.
I re-implemented the fix accordingly to Craig suggest.
Wed, Aug 30
Tue, Aug 29
Mon, Aug 28
Aug 25 2017
32-bit tests added and the condition fixed properly.
Aug 23 2017
Craig's issues fixed.
Aug 22 2017
https://reviews.llvm.org/D36793 should cover these issues
All changes from this review (excluding error diagnostic) were included in D36793.
I did fixes raised by Craig.
Aug 18 2017
IntelExpr::isValid looks rather strange because it validates possible multiplication only. But if we have Scale == 1 and don't have either BaseReg or Disp?
+ I'm currently having a patch on review (D36793) which contains most of the intended goals of this one (everything but the new error, afaik), can you verify it answers your needs?
Coby, Reid, is eveything OK? Could you get LGTM?
Aug 16 2017
I fixed the last minute issue raised in the first version.
I found one issue in the current version of the patch that's why I'm asking to postpone its review until the next version: hope to publish it in some hours or tomorrow.
Aplied Reid's requirements.
Aug 15 2017
It's fixed in D35621
I created a ne review to show changes in Clang: D36735
I restored the patch with LLVM part only.
The Clang changes added.
Last minor fixes done.
Aug 14 2017
I removed all changes (apart from the added diagnostics). Now it should fit to Coby requirements. Right?
Aug 11 2017
I applied all changes suggested by Coby.
Aug 10 2017
Aug 8 2017
The last requirements from Simon were fixed.
Aug 4 2017
Hope, my comments now are OK.
There were 2 commits covering this patch
I'm not sure we need rebase this patch because 2 pre-patches do almost everything I'd like to see here. There is only one last thing: a possibilty to return latency as value of throughput if we don't have any sched model or don't have ResourceCycles in the existing model. But now I think that programmer can do this functionality by himself (if s/he needs it). Am I right? I'm going to abandon this review. OK?
Aug 3 2017
Do you have any questions about this patch?
Aug 1 2017
Jul 31 2017
The note mentioned by Simon fixed.
Jul 28 2017
It was committed
Jul 27 2017
Could we split it on 2 sub-parts:
Jul 26 2017
The questionn with getCycles() fixed.
I got rid of "double Unknown = std::numeric_limits<double>::infinity();" - many tnx to Simon for this idea.
I re-based the the code after the patch about replacing of assertions with corresponding diagnostic error messages. As result changes in tests show that X86 Asm supports symbolic Scale/Disp properly now (including its negative value).
Jul 25 2017
Jul 21 2017
This patch replaces assertions with normal diagnostic when it's possible. Now we see normal error messages instead of compiler crashes. It should close PR33861, PR33862 and PR33661. In addition the patch prepares tests for D35621.
Jul 20 2017
I updated 2 tests in trunk to demonstarte the difference in code generation after this patch aplying. Now we can clearly see the issues and how they could be resolved with help of this patch.
Jul 19 2017
Jul 14 2017
I fixed Simon's comments.
Jul 13 2017
I merged this patch with trunk. Now it's a part 2 othe initial patch.
Jul 11 2017
Jul 10 2017
Jul 7 2017
I removed NFCs from this patch.
Simon, thank you for all these catches: I fixed them.
Jul 6 2017
We have now only 256-bit ops: it makes the patch smaller.
Jun 13 2017
The comments fixed.
New reviewers added.
Jun 9 2017
Jun 8 2017
All notes from Simon were resolved. In addition I fixed numbers for some XMM versions of VMOVxxxx instructions.
Some renames and other minor updates.
Jun 7 2017
I removed all changes related to throughput calculations. And I made all updates suggested by Simon.
I re-implemented all things mentioned by Simon and Gadi.
Jun 6 2017
Why don't you use regular expressions instead of simple list of instructions?
Jun 1 2017
I removed default values defined for SB model (required by javed.absar).
I fixed all Simon's notes.
May 30 2017
I redesigned the implementation accordingly to Simon requirements. Now it's done in general way and every X86 should support horizontal operations modeling. I did not check the numbers for SB and SLM: I simply kept the current ones. And I separated Ymm version from Xmm version to be able to model the corresponding throughput difference for Jaguar.
May 29 2017
The revision was committed.