- User Since
- Nov 23 2016, 4:39 AM (356 w, 6 d)
Feb 20 2018
Feb 19 2018
Updated diff to include the complete 32bit and 64bit tests
reclaimed the review in order to add the 32-bit encoding tests.
Feb 8 2018
Feb 5 2018
Following comments by Craig and Simon, is it possible to add the MC tests for CET 32bit?
You can use the 32bit tests in https://reviews.llvm.org/D41329
Sorry. Updated diff as the added MRM tests in POPCNT-*.s were not reflected in the previous diff file.
Added more MRM tests in POPCNT-32.s and POPCNT-64.s following Simon's comment.
The 32bit encoding is identical to the 64bit CET encoding (similar to the RTM ISA).
Feb 4 2018
The MC tests for the CET ISA Set are fully covered in test/MC/X86/cet-encoding.s added in https://reviews.llvm.org/D40223
I, therefore, abandon this review.
Jan 16 2018
Jan 15 2018
Dec 28 2017
Dec 27 2017
Sorry for delayed response. Just returned from vacation.
Added the prefetchwt1 testing.
Dec 21 2017
Unfortunately the following instruction mnemonics are not supported by llvm-mc:
rdfsbasew, rdgsbasew, wrfsbasw, wrgsbasew
Added tests for rdfsbaseq,,rdgsbaseq, wrfsbaseq, wrgsbaseq
Added rdseedw,rdseedq, rdrandw, rdrandq instructions.
updated XOP-64 tests following comments by Craig
Dec 20 2017
Added missing tests for the prefetcht0/1/2 and prefetchnta instructions
good call. I will add Oren to the review.
Added mem ops tests for POPCNT 32 and 64 bit
Yes, Added Andrei who is going to take over this task and add the new instructions.
good catch. I will add the mem ops for popcnt.
fixed comments found by Simon
Dec 19 2017
fixed a typo in SHA-64.s tests
Dec 17 2017
I can try to add them in. However, we should consider opening a proper bugzilla to convert ALL the MC tests to use asb proposal, since the llvm-objdump is not always compatible with llvm-mc on x86.
Dec 16 2017
Dec 15 2017
Dec 14 2017
Yes Gather instructions are part of AVX2GATHER.
I will add the VEX.X testing to all AVX tests.
X87 diff replaced by AVX1 diff
Updated diff following comments by Craig and Simon.
AVX512F 128N are vector instructions which have a GPR or a memory with the size of a scalar as an operand (insert/extract/mov).
Dec 13 2017
The AVX512F 128N is a small extension to the AVX512F 128 base which includes the following ifroms:
VEXTRACTPS, VINSERTPS, VMOVD, VMOVHLPS, VMOVHPD, VMOVHPS, VMOVLHPS, VMOVLPD, VMOVLPS, VMOVQ
Added zero masked and non-masked instructions following Craig's comment
Craig, following your comment I added the zero masked and non masked instructions. However, the diff file is too large to get uploaded by the phabricator.
Consequently, I will have to split the review into multiple reviews.
Dec 12 2017
Unfortunately, there are many cases of incompatibility tween what llvm-objdump generates and the disassembler output - causing the above tests to fail.
I will continue to investigate this as it is a good idea to test the llvm-objdump as well.
However, it may take a while and I may need to open different review for this
Interesting. I will try it out.
I can get/check the encoded bytes this way but what about checking the assembly instruction representation? e.g. checking the assembly instruction : "imull $0, %r13d, %r13d"?
Dec 10 2017
Updated diff based on comments by Simon and Craig:
- Added the I286 and all Pentium tests
- Removed a CET instruction from PPRO tests.
Yes, The bswap belongs to I486REAL but I will add it to the I486 tests.
bound belongs to I186. I will check why it is missing from it.
Dec 8 2017
Dec 7 2017
- Following Craig's comment extended all I*86 tests.
- Added the tests for PENTIUMMMX and PPRO.