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aymanmus (Ayman Musa)
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Aug 8 2016, 8:14 AM (220 w, 4 d)

Recent Activity

Apr 19 2020

aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Apr 19 2020, 4:15 AM · Restricted Project
aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Sorry, I did not explain my previous comment as well as possible. Let's take this minimal example:

define i1 @f(i8 %a) {
  %conv = sext i8 %a to i32
  %cmp = icmp slt i32 %conv, 109
  ret i1 %cmp
}
Apr 19 2020, 1:34 AM · Restricted Project

Apr 14 2020

aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Apr 14 2020, 1:33 AM · Restricted Project

Apr 8 2020

aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

As per @spatel 's request,
Added a comment explaining the motive behind implementing the transformation in aggressive instcombine instead of normal instcombine.

Apr 8 2020, 5:23 AM · Restricted Project

Apr 7 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

@spatel: Basically the test cases with the real motivation are the first 4.

Do you mean the first 4 with diffs, or the first 4 that are being added as new tests?

The first 4 with diff.

Where most of the other cases are there to check various "edge" cases of the added code behavior.
I think, that even if some of the tests are not in a canonical form (and can be optimized by instcombine), we still have an added value having them here in order to check the behavior of this specific pass with similar cases.
Don't you agree?

Yes, I agree that we want to have tests for edge cases to make sure that the logic is correct here. But we also should have tests that show why this patch is necessary - functions that could not be solved in regular instcombine easily.

I agree with you 100%. That's why we have several test cases.

Apr 7 2020, 8:39 AM · Restricted Project

Apr 6 2020

aymanmus added a comment to D73228: [AsmPrinter][ELF] Define local aliases (.Lfoo$local) for GlobalObjects.

This change has broke the update_llc_test_checks.py tool's functionality for any test that includes a local function.
The tool now removes all "; CHECK" lines from such tests and emits nothing instead.
You can check this by adding "dso_local" attribute to any of the X86 existing tests (for example /llvm/CodeGen/X86/add-i64.ll) and run "update_llc_test_checks.py on it.

Apr 6 2020, 8:38 AM · Restricted Project
aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

@spatel: Basically the test cases with the real motivation are the first 4.
Where most of the other cases are there to check various "edge" cases of the added code behavior.
I think, that even if some of the tests are not in a canonical form (and can be optimized by instcombine), we still have an added value having them here in order to check the behavior of this specific pass with similar cases.
Don't you agree?

Apr 6 2020, 6:27 AM · Restricted Project

Mar 31 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Just checked the patch @spatel mentioned.
Doesn't really help with the cases provided here.

Mar 31 2020, 1:04 AM · Restricted Project

Mar 29 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

PING.

Mar 29 2020, 1:02 AM · Restricted Project

Mar 10 2020

aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Mar 10 2020, 8:06 AM · Restricted Project
aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Mar 10 2020, 8:06 AM · Restricted Project

Mar 8 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Ping #2.

Mar 8 2020, 12:33 AM · Restricted Project

Feb 27 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Ping.

Feb 27 2020, 12:37 AM · Restricted Project

Feb 20 2020

aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 20 2020, 6:04 AM · Restricted Project
aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 20 2020, 6:04 AM · Restricted Project
aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 20 2020, 6:04 AM · Restricted Project

Feb 16 2020

aymanmus added inline comments to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 16 2020, 5:36 AM · Restricted Project
aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Fix the constant aux functions to correctly handle vector constants.

Feb 16 2020, 5:36 AM · Restricted Project

Feb 13 2020

aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

@aymanmus I have something along these lines in mind...

%conv = sext i8 %a to i32
%conv2 = sext i8 %b to i32
%conv3 = sext i8 %c to i32
%cmp = icmp slt i32 %conv3, TOO_BIG_CONST
%cond = select i1 %cmp, i32 %conv2, i32 %conv
%conv4 = trunc i32 %cond to i16
ret i16 %conv4

That is, where the icmp has a form that passes the isConstOrExt(C->getOperand(0)) && isConstOrExt(C->getOperand(1)) check, but later gets rejected due to constant bitwidth.

Not sure if that example does it, but I think there must be some case like this, unless I'm misunderstanding the patch.

Feb 13 2020, 7:21 AM · Restricted Project
aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Addressed @nikic & @lebedev.ri comments.

Feb 13 2020, 7:21 AM · Restricted Project
aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

I think this is missing a test-case where the select could be truncated if you ignored the icmp, but not if you require the icmp to also be truncated. That should show up as a regression in the test diffs.

Feb 13 2020, 1:26 AM · Restricted Project
aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 13 2020, 12:41 AM · Restricted Project
aymanmus updated the diff for D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

Deal with APInt instead of 64-bit value in constants.

Feb 13 2020, 12:41 AM · Restricted Project
aymanmus added a comment to D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..

This seems not generic enough to me, can't we not require the icmp operands to be constants/[sz]ext's,
but instead try to see if it can be evaluated in smaller bitwidth (what the rest of the code here does)?

As long as the icmp can be shrunked to at least as small bitwidth as we need there to get rid of cast,
i think we can always pick the actual bitwidth we'll use, which might be wider than minimal?

After thinking about this, i'd be okay with not doing that straight away.
It should be doable, but would require substantial redesign to nicely model more than one dag and their connection/dependency.

Feb 13 2020, 12:23 AM · Restricted Project

Feb 12 2020

aymanmus created D74484: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's condition operand..
Feb 12 2020, 6:04 AM · Restricted Project
aymanmus committed rGcd515a6538f4: [AggressiveInstCombine] Add test with baseline CHECKs for aggressive inst… (authored by aymanmus).
[AggressiveInstCombine] Add test with baseline CHECKs for aggressive inst…
Feb 12 2020, 5:19 AM
aymanmus committed rG35f02aa0213c: Revert "[AggressiveInstCombine] Add support for ICmp instr that feeds a select… (authored by aymanmus).
Revert "[AggressiveInstCombine] Add support for ICmp instr that feeds a select…
Feb 12 2020, 5:09 AM
aymanmus added a reverting change for rGcf155150f992: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's…: rG35f02aa0213c: Revert "[AggressiveInstCombine] Add support for ICmp instr that feeds a select….
Feb 12 2020, 5:09 AM
aymanmus committed rGcf155150f992: [AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's… (authored by aymanmus).
[AggressiveInstCombine] Add support for ICmp instr that feeds a select intsr's…
Feb 12 2020, 5:09 AM
aymanmus committed rG3bda9059b88b: [AggressiveInstCombine] Add support for select instruction. (authored by aymanmus).
[AggressiveInstCombine] Add support for select instruction.
Feb 12 2020, 4:05 AM
aymanmus closed D72837: [AggressiveInstCombine] Add support for select instruction..
Feb 12 2020, 4:05 AM · Restricted Project
aymanmus committed rG49a4d85f6d24: [NFC][AggressiveInstCombine] Remove redundant std::max. (authored by aymanmus).
[NFC][AggressiveInstCombine] Remove redundant std::max.
Feb 12 2020, 3:56 AM
aymanmus closed D74476: [NFC][AggressiveInstCombine] Remove redundant std::max..
Feb 12 2020, 3:55 AM · Restricted Project
aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Extract the std::max omission to a separate patch as requested (patch D74476)

Feb 12 2020, 3:55 AM · Restricted Project
aymanmus created D74476: [NFC][AggressiveInstCombine] Remove redundant std::max..
Feb 12 2020, 3:46 AM · Restricted Project

Feb 11 2020

aymanmus added inline comments to D72837: [AggressiveInstCombine] Add support for select instruction..
Feb 11 2020, 5:07 AM · Restricted Project
aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Adding full context to patch.

Feb 11 2020, 4:40 AM · Restricted Project
aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Removed all cmp instruction handling to get a pure SELECT patch support.

Feb 11 2020, 1:35 AM · Restricted Project

Feb 9 2020

aymanmus committed rG10c7b7708b32: [AggressiveInstCombine] Add test with baseline CHECKs for aggressive inst… (authored by aymanmus).
[AggressiveInstCombine] Add test with baseline CHECKs for aggressive inst…
Feb 9 2020, 2:09 AM

Jan 26 2020

aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Following @nikic's comment:
I agree, the patch is missing some select exclusive tests.
Adding such test cases.
IMHO, there is no added value to splitting to 2 patches, the select changed are too obvious, and the compare is strongly related to the select changes.

Jan 26 2020, 5:52 AM · Restricted Project
aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Fix @spatel's test case. Thanks for the review.
Involve constants in cmp operations in the MinBitWidth calculations.

Jan 26 2020, 12:48 AM · Restricted Project

Jan 20 2020

aymanmus updated the diff for D72837: [AggressiveInstCombine] Add support for select instruction..

Somehow the test wasn't included with the differential text file.
Adding now.

Jan 20 2020, 4:26 AM · Restricted Project

Jan 16 2020

aymanmus created D72837: [AggressiveInstCombine] Add support for select instruction..
Jan 16 2020, 4:55 AM · Restricted Project

Jul 14 2019

aymanmus added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Thanks Anton.
Can you please keep us updated with any progress in this regard?

Jul 14 2019, 12:55 AM · Restricted Project

Jul 9 2019

aymanmus added a comment to D63934: [MIR] Improve PRE condition of MachineCSE optimization.

Just to make sure I understand the change correctly:
This can still hoist instructions outside of their BB and execute them speculatively even if you can't prove that all possible paths execute the instruction, am I right?

Jul 9 2019, 12:40 AM · Restricted Project

Jun 26 2019

aymanmus added a comment to rL362901: [MIR] Add simple PRE pass to MachineCSE.

Hi Anton,

Jun 26 2019, 2:11 AM
aymanmus updated subscribers of rL362901: [MIR] Add simple PRE pass to MachineCSE.
Jun 26 2019, 2:11 AM

Dec 12 2017

aymanmus committed rL320481: [X86] Recognize constant arrays with special values and replace loads from it….
[X86] Recognize constant arrays with special values and replace loads from it…
Dec 12 2017, 6:14 AM
aymanmus closed D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..
Dec 12 2017, 6:14 AM

Nov 13 2017

aymanmus added inline comments to D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..
Nov 13 2017, 3:50 AM

Nov 2 2017

aymanmus committed rL317206: [X86] Fix bug in legalize vector types - Split large loads.
[X86] Fix bug in legalize vector types - Split large loads
Nov 2 2017, 6:07 AM
aymanmus closed D38495: [X86] Fix bug in legalize vector types - Split large loads by committing rL317206: [X86] Fix bug in legalize vector types - Split large loads.
Nov 2 2017, 6:07 AM
aymanmus added inline comments to D38495: [X86] Fix bug in legalize vector types - Split large loads.
Nov 2 2017, 6:04 AM

Oct 31 2017

aymanmus committed rL316989: Adding a shufflevector and select LLVM IR instructions fuzz tool.
Adding a shufflevector and select LLVM IR instructions fuzz tool
Oct 31 2017, 4:40 AM
aymanmus closed D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool by committing rL316989: Adding a shufflevector and select LLVM IR instructions fuzz tool.
Oct 31 2017, 4:40 AM
aymanmus updated the diff for D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.

Targeted Gadi's comments.

Oct 31 2017, 2:39 AM

Oct 29 2017

aymanmus added inline comments to D38495: [X86] Fix bug in legalize vector types - Split large loads.
Oct 29 2017, 6:09 AM
aymanmus updated the diff for D38495: [X86] Fix bug in legalize vector types - Split large loads.

Manually reducing "bugpointed" test.

Oct 29 2017, 1:22 AM

Oct 23 2017

aymanmus updated the diff for D38495: [X86] Fix bug in legalize vector types - Split large loads.

Adding triple & a test case for PR23657

Oct 23 2017, 6:51 AM
aymanmus updated the diff for D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..
Oct 23 2017, 3:30 AM
aymanmus committed rL316320: [X86] Add test for opportunity to use bzhi X86 instruction instead of load+and….
[X86] Add test for opportunity to use bzhi X86 instruction instead of load+and…
Oct 23 2017, 3:26 AM
aymanmus added a comment to D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.

Ping #3!

Oct 23 2017, 1:30 AM
aymanmus added a comment to D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..

Ping #3!

Oct 23 2017, 1:30 AM
aymanmus abandoned D32680: [X86] Apply the new instruction's register classes constraints on the operands of the replaced instruction when memory folding.

Abandoning - lack of response.

Oct 23 2017, 1:25 AM

Oct 22 2017

aymanmus accepted D38738: X86CallFrameOptimization: Recognize 'store 0/-1 using and/or' idioms.

Minor comments but LGTM overall.

Oct 22 2017, 2:14 AM

Oct 10 2017

aymanmus added inline comments to D38689: [X86] Fix a bug with i386 subtarget in LowerCONCAT_VECTORSvXi1 func.
Oct 10 2017, 12:30 AM

Oct 8 2017

aymanmus added a comment to D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..

Kind ping #2

Oct 8 2017, 4:41 AM
aymanmus added a comment to D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.

Kind ping #2

Oct 8 2017, 4:41 AM
aymanmus committed rL315174: [X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the….
[X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the…
Oct 8 2017, 2:48 AM
aymanmus closed D38500: [X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the table by committing rL315174: [X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the….
Oct 8 2017, 2:48 AM
aymanmus committed rL315173: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend….
[X86][TableGen] Recommitting the X86 memory folding tables TableGen backend…
Oct 8 2017, 2:22 AM
aymanmus closed D38028: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default. by committing rL315173: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend….
Oct 8 2017, 2:22 AM
aymanmus added a comment to D38495: [X86] Fix bug in legalize vector types - Split large loads.

The bug was filed for Clang's 3.8 version, it passed with clang-4.0 and clang-ToT (top of trunc).
Seems like the issue was fixed while ago.

Oct 8 2017, 2:14 AM
aymanmus committed rL315171: [X86] Add new attribute to X86 instructions to enable marking them as "not….
[X86] Add new attribute to X86 instructions to enable marking them as "not…
Oct 8 2017, 1:34 AM
aymanmus closed D38027: [X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable" by committing rL315171: [X86] Add new attribute to X86 instructions to enable marking them as "not….
Oct 8 2017, 1:34 AM

Oct 4 2017

aymanmus added a comment to D38027: [X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable".

The goal is to make tablegen generate the "correct" tables (according to what we define is correct).
So it's up to us to decide what will go in and out of the tables.

Oct 4 2017, 12:29 AM

Oct 3 2017

aymanmus added a comment to D38028: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default..

@craig.topper that's right, at the end of this process both the generated and manual tables will hold the same entries. But the backend would be disabled and we would include a copy of the last generated inc file from it.
The main challenge here is how to integrate the TableGen's backend and taking advantage of its capabilities while supervising and validating each change made to them.

Oct 3 2017, 11:48 PM
aymanmus created D38500: [X86] Add missing entries in 'MemoryFoldTable2Addr' to get complete form of the table.
Oct 3 2017, 6:13 AM
aymanmus added a comment to D38028: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default..

No it won't completely replace it. It would be used as a reference to the manual tables.
It's explained in the description section of this patch.
The decision was made after a discussion in the community's mailing list (http://lists.llvm.org/pipermail/llvm-dev/2017-July/115734.html)

Oct 3 2017, 3:57 AM
aymanmus created D38495: [X86] Fix bug in legalize vector types - Split large loads.
Oct 3 2017, 12:50 AM

Oct 2 2017

aymanmus added a comment to D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..

Ping.

Oct 2 2017, 5:06 AM
aymanmus added a comment to D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.

Ping.

Oct 2 2017, 5:05 AM

Oct 1 2017

aymanmus accepted D38120: [X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem.

LGTM

Oct 1 2017, 1:43 AM
aymanmus abandoned D38025: [X86] Change the Format attribute for TEST*rr instruction from the default MRMDestReg to MRMSrcReg.

Fixed in D38120

Oct 1 2017, 1:43 AM
aymanmus added inline comments to D38027: [X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable".
Oct 1 2017, 1:25 AM
aymanmus added a comment to D38028: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default..

Since the backend would be disabled at the end of the process, I think that it's better to keep it that way from the beginning.
The generated tables do not mean anything now and IMHO should not be visible to anyone who has no interest in contributing to this specific effort.
So I guess the best way to keep the temporary tables "hidden" is by enabling the "run-by-demand" mechanism now.

Oct 1 2017, 12:44 AM

Sep 19 2017

aymanmus created D38031: Adding a shufflevector and select LLVM IR instructions fuzz tool.
Sep 19 2017, 2:52 AM
aymanmus created D38028: [X86][TableGen] Recommitting the X86 memory folding tables TableGen backend while disabling it by default..
Sep 19 2017, 1:39 AM
aymanmus created D38027: [X86] Add new attribute to X86 instructions to enable marking them as "not memory foldable".
Sep 19 2017, 1:28 AM
aymanmus created D38025: [X86] Change the Format attribute for TEST*rr instruction from the default MRMDestReg to MRMSrcReg.
Sep 19 2017, 12:43 AM

Sep 18 2017

aymanmus updated the diff for D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..
Sep 18 2017, 5:31 AM

Sep 17 2017

aymanmus updated the diff for D34141: [X86] Recognize constant arrays with special values and replace loads from it with subtract and shift instructions, which then will be replaced by X86 BZHI machine instruction..

Total redesign to the previous solution.
moved the transformation to a more "natural" area.

Sep 17 2017, 8:17 AM

Sep 14 2017

aymanmus committed rL313256: [X86] When applying the shuffle-to-zero-extend transformation on floating point….
[X86] When applying the shuffle-to-zero-extend transformation on floating point…
Sep 14 2017, 5:08 AM
aymanmus closed D37803: [X86] When applying the shuffle-to-zero-extend transformation on floating point, bitcast to integer first. by committing rL313256: [X86] When applying the shuffle-to-zero-extend transformation on floating point….
Sep 14 2017, 5:08 AM
aymanmus updated the diff for D37803: [X86] When applying the shuffle-to-zero-extend transformation on floating point, bitcast to integer first..
Sep 14 2017, 1:13 AM

Sep 13 2017

aymanmus created D37803: [X86] When applying the shuffle-to-zero-extend transformation on floating point, bitcast to integer first..
Sep 13 2017, 6:12 AM

Sep 12 2017

aymanmus accepted D37592: [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel.

Thanks for the answer.
LGTM

Sep 12 2017, 9:00 AM
aymanmus added inline comments to D37592: [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel.
Sep 12 2017, 2:19 AM

Sep 11 2017

aymanmus added inline comments to D37592: [X86] Move matching of (and (srl/sra, C), (1<<C) - 1) to BEXTR/BEXTRI instruction to custom isel.
Sep 11 2017, 12:04 AM

Sep 6 2017

aymanmus accepted D37455: [X86] Introduce a new td file to hold patterns some of the non instruction patterns from SSE and AVX512.

LGTM

Sep 6 2017, 12:50 AM