[SelectionDAG] Improve support for promotion of <1 x fX> floating point argument types (PR31088)

[RKSimon]

Summary

PR31088 demonstrated that we were assuming that only integers require promotion from <1 x iX> types, when in fact float types may require it as well - in this case half floats.

This patch adds support for extension/truncation for both integer and float types.

[efriedma]

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

368

Is it actually possible for this to truncate/round?

564

Unless I'm misreading this, we just set Val to an EXTRACT_VECTOR_ELT of type PartVT on the previous line; does this conversion do anything?

test/CodeGen/X86/pr31088.ll

14

This __gnu_f2h_ieee + __gnu_h2f_ieee sequence looks strange...

21

Only tangentially related to your patch, but I'm not sure I understand the lowering here; addss is not a half-precision operation (and therefore won't produce correctly rounded results).

[RKSimon]

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

564

Good point - will remove this and add an assert to check that the Parts[0] has a PartVT value type.

test/CodeGen/X86/pr31088.ll

14

From what I can tell, half args always come in as single precision floats and we don't guarantee that the floats are only set to half precision, so we have to truncate them - and then as we're performing arithmetic they must be extended back again to singles for the fadd.

Interestingly we don't bother truncating+extending the single results - we leave it with excess precision on return.

[RKSimon]

Updated based on @efriedma comments

[RKSimon]

rebased against trunk

[RKSimon]

ping?

[efriedma]

(I don't understand how this is supposed to work, so I don't feel comfortable approving it.)

[spatel]

The title/summary shows the wrong PR#; it should be PR31088:
https://bugs.llvm.org/show_bug.cgi?id=31088

The patch itself seems mechanical in that it's repeating the integer fixups, but I wonder if we can get someone with half-FP experience to take a look too in case this isn't behaving how we expect on all targets? The suspicious x86 codegen is a separate issue as noted earlier, but that's better than crashing? :)

test/CodeGen/X86/pr31088.ll

3–4

Does having both SSE and AVX RUNs add value? Seems like the output is identical apart from 'v' prefixes, so I'd kill one of them just as a matter of saving test time.

[RKSimon]

test/CodeGen/X86/pr31088.ll

3–4

OK - I'll keep SSE. I'll add i686 targets instead as they will be coming from the stack instead of registers so will show another behaviour

[tra]

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

530–533

Nit. I'd use VT.isFloatingPoint() and use FP_EXTEND only on types we positively know to be FP and leave behavior for all other types as it is right now. Otherwise you're making implicit assumption that all types are either integer or FP which, generally speaking, is not true. There's void, for instance.

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

364–369

Same as above.

test/CodeGen/X86/pr31088.ll

3–4

It may be interesting to run the tests for NVPTX target as it supports both native FP16 and promote-to-fp32-calcualate->demote back to fp16 codegen modes.

[RKSimon]

Use VT.isFloatingPoint() to select float extension/truncation (and still use integer path by default).

Add NVPTX test as suggested.

[tra]

LGTM. The patch produces sensible code for NVPTX target with and without fp16 support in hardware.

include/llvm/CodeGen/SelectionDAG.h

#endif
   }
 
   /// \brief Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to
   /// the shuffle node in input but with swapped operands.
   ///
   /// Example: shuffle A, B, <0,5,2,7> -> shuffle B, A, <4,1,6,3>
   SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV);
 
+  /// Convert Op, which must be of float type, to the
+  /// float type VT, by either extending or rounding (by truncation).
+  SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT);
+
   /// Convert Op, which must be of integer type, to the
   /// integer type VT, by either any-extending or truncating it.
   SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
 
   /// Convert Op, which must be of integer type, to the
   /// integer type VT, by either sign-extending or truncating it.
   SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT);
 

lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

SDValue DAGTypeLegalizer::ScalarizeVecOp_CONCAT_VECTORS(SDNode *N) {
   for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i)
     Ops[i] = GetScalarizedVector(N->getOperand(i));
   return DAG.getBuildVector(N->getValueType(0), SDLoc(N), Ops);
 }
 
 /// If the input is a vector that needs to be scalarized, it must be <1 x ty>,
 /// so just return the element, ignoring the index.
 SDValue DAGTypeLegalizer::ScalarizeVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
+  EVT VT = N->getValueType(0);
   SDValue Res = GetScalarizedVector(N->getOperand(0));
-  if (Res.getValueType() != N->getValueType(0))
-    Res = DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0),
-                      Res);
+  if (Res.getValueType() != VT)
+    Res = VT.isInteger() ? DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), VT, Res)
+                         : DAG.getNode(ISD::FP_EXTEND, SDLoc(N), VT, Res);
   return Res;
 }
 
 
 /// If the input condition is a vector that needs to be scalarized, it must be
 /// <1 x i1>, so just convert to a normal ISD::SELECT
 /// (still with vector output type since that was acceptable if we got here).
 SDValue DAGTypeLegalizer::ScalarizeVecOp_VSELECT(SDNode *N) {

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
             static_cast<SDNode*>(nullptr));
 
   EntryNode.UseList = nullptr;
   InsertNode(&EntryNode);
   Root = getEntryNode();
   DbgInfo->clear();
 }
 
+SDValue SelectionDAG::getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT) {
+  return VT.bitsGT(Op.getValueType())
+             ? getNode(ISD::FP_EXTEND, DL, VT, Op)
+             : getNode(ISD::FP_ROUND, DL, VT, Op, getIntPtrConstant(0, DL));
+}
+
 SDValue SelectionDAG::getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
   return VT.bitsGT(Op.getValueType()) ?
     getNode(ISD::ANY_EXTEND, DL, VT, Op) :
     getNode(ISD::TRUNCATE, DL, VT, Op);
 }
 
 SDValue SelectionDAG::getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT) {
   return VT.bitsGT(Op.getValueType()) ?

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (PartEVT.getSizeInBits() == ValueVT.getSizeInBits() &&
     return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
 
   // Handle cases such as i8 -> <1 x i1>
   if (ValueVT.getVectorNumElements() != 1) {
     diagnosePossiblyInvalidConstraint(*DAG.getContext(), V,
                                       "non-trivial scalar-to-vector conversion");
     return DAG.getUNDEF(ValueVT);
   }
 
-  if (ValueVT.getVectorNumElements() == 1 &&
-      ValueVT.getVectorElementType() != PartEVT)
-    Val = DAG.getAnyExtOrTrunc(Val, DL, ValueVT.getScalarType());
+  EVT ValueSVT = ValueVT.getVectorElementType();
+  if (ValueVT.getVectorNumElements() == 1 && ValueSVT != PartEVT) {
+    Val = ValueVT.isInteger() ? DAG.getAnyExtOrTrunc(Val, DL, ValueSVT)
+                              : DAG.getFPExtendOrRound(Val, DL, ValueSVT);
+  }
 
   return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val);
 }
 
 static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl,
                                  SDValue Val, SDValue *Parts, unsigned NumParts,
                                  MVT PartVT, const Value *V);
 
if (NumParts == 1) {
     } else{
       // Vector -> scalar conversion.
       assert(ValueVT.getVectorNumElements() == 1 &&
              "Only trivial vector-to-scalar conversions should get here!");
       Val = DAG.getNode(
           ISD::EXTRACT_VECTOR_ELT, DL, PartVT, Val,
           DAG.getConstant(0, DL, TLI.getVectorIdxTy(DAG.getDataLayout())));
 
-      Val = DAG.getAnyExtOrTrunc(Val, DL, PartVT);
+      Val = PartVT.isInteger() ? DAG.getAnyExtOrTrunc(Val, DL, PartVT)
+                               : DAG.getFPExtendOrRound(Val, DL, PartVT);
     }
 
     Parts[0] = Val;
     return;
   }
 
   // Handle a multi-element vector.
   EVT IntermediateVT;

test/CodeGen/X86/pr31088.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=SSE
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+f16c | FileCheck %s --check-prefix=F16C
+
+define <1 x half> @ir_fadd_v1f16(<1 x half> %arg0, <1 x half> %arg1) nounwind {
+; SSE-LABEL: ir_fadd_v1f16:
+; SSE:       # BB#0:
+; SSE-NEXT:    pushq %rax
+; SSE-NEXT:    movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movaps %xmm1, %xmm0
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    movss %xmm0, (%rsp) # 4-byte Spill
+; SSE-NEXT:    movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; SSE-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    addss (%rsp), %xmm0 # 4-byte Folded Reload
+; SSE-NEXT:    popq %rax
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: ir_fadd_v1f16:
+; AVX:       # BB#0:
+; AVX-NEXT:    pushq %rax
+; AVX-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovaps %xmm1, %xmm0
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vmovss %xmm0, (%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; AVX-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vaddss (%rsp), %xmm0, %xmm0 # 4-byte Folded Reload
+; AVX-NEXT:    popq %rax
+; AVX-NEXT:    retq
+;
+; F16C-LABEL: ir_fadd_v1f16:
+; F16C:       # BB#0:
+; F16C-NEXT:    vcvtps2ph $4, %xmm1, %xmm1
+; F16C-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; F16C-NEXT:    retq
+  %retval = fadd <1 x half> %arg0, %arg1
+  ret <1 x half> %retval
+}
+
+define <2 x half> @ir_fadd_v2f16(<2 x half> %arg0, <2 x half> %arg1) nounwind {
+; SSE-LABEL: ir_fadd_v2f16:
+; SSE:       # BB#0:
+; SSE-NEXT:    subq $24, %rsp
+; SSE-NEXT:    movss %xmm2, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movss %xmm1, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movaps %xmm3, %xmm0
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; SSE-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; SSE-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    movss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; SSE-NEXT:    movss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; SSE-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; SSE-NEXT:    callq __gnu_f2h_ieee
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    addss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Folded Reload
+; SSE-NEXT:    movss {{[0-9]+}}(%rsp), %xmm1 # 4-byte Reload
+; SSE-NEXT:    # xmm1 = mem[0],zero,zero,zero
+; SSE-NEXT:    addss {{[0-9]+}}(%rsp), %xmm1 # 4-byte Folded Reload
+; SSE-NEXT:    addq $24, %rsp
+; SSE-NEXT:    retq
+;
+; AVX-LABEL: ir_fadd_v2f16:
+; AVX:       # BB#0:
+; AVX-NEXT:    subq $24, %rsp
+; AVX-NEXT:    vmovss %xmm2, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss %xmm1, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovaps %xmm3, %xmm0
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; AVX-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; AVX-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vmovss %xmm0, {{[0-9]+}}(%rsp) # 4-byte Spill
+; AVX-NEXT:    vmovss {{[0-9]+}}(%rsp), %xmm0 # 4-byte Reload
+; AVX-NEXT:    # xmm0 = mem[0],zero,zero,zero
+; AVX-NEXT:    callq __gnu_f2h_ieee
+; AVX-NEXT:    movzwl %ax, %edi
+; AVX-NEXT:    callq __gnu_h2f_ieee
+; AVX-NEXT:    vaddss {{[0-9]+}}(%rsp), %xmm0, %xmm0 # 4-byte Folded Reload
+; AVX-NEXT:    vmovss {{[0-9]+}}(%rsp), %xmm1 # 4-byte Reload
+; AVX-NEXT:    # xmm1 = mem[0],zero,zero,zero
+; AVX-NEXT:    vaddss {{[0-9]+}}(%rsp), %xmm1, %xmm1 # 4-byte Folded Reload
+; AVX-NEXT:    addq $24, %rsp
+; AVX-NEXT:    retq
+;
+; F16C-LABEL: ir_fadd_v2f16:
+; F16C:       # BB#0:
+; F16C-NEXT:    vcvtps2ph $4, %xmm3, %xmm3
+; F16C-NEXT:    vcvtph2ps %xmm3, %xmm3
+; F16C-NEXT:    vcvtps2ph $4, %xmm1, %xmm1
+; F16C-NEXT:    vcvtph2ps %xmm1, %xmm1
+; F16C-NEXT:    vcvtps2ph $4, %xmm2, %xmm2
+; F16C-NEXT:    vcvtph2ps %xmm2, %xmm2
+; F16C-NEXT:    vcvtps2ph $4, %xmm0, %xmm0
+; F16C-NEXT:    vcvtph2ps %xmm0, %xmm0
+; F16C-NEXT:    vaddss %xmm2, %xmm0, %xmm0
+; F16C-NEXT:    vaddss %xmm3, %xmm1, %xmm1
+; F16C-NEXT:    retq
+  %retval = fadd <2 x half> %arg0, %arg1
+  ret <2 x half> %retval
+}
+