[RALLOC] Increase CSR cost in RegAllocGreedy to favour splitting over CSR first use

[wmi]

Summary

The patch is to solve the problem mentioned in PR29154. It is evolved from https://reviews.llvm.org/D27366.

The patch raises the CSR cost to be 1/4 of the func entry frequency, so that live range will use CSR only when its splitting cost or spill cost is close to or higher than the func entry frequency, otherwise regalloc will choose to split or spill the live range. After the split or spill, live ranges allocated to CSR registers will be shortened and will only be used in cold places, so that we may get better chances to do shrinkwrapping. Another potential benefit is that param passing copy may be sinked from entry to a colder branch.

Internal testing shows it improves several benchmarks, such as zippy (+0.8%), protobuf (+1.9%) and some other microbenchmarks without specified names.

[echristo]

In general I'm a fan of the change, however, it feels like the heuristic value is somewhat unintelligable on scan. I.e. what's the difference between 1 << 13 and 5 (or any other value)? :)

Is there something we could do to make this easier or more friendly to tune?

Thanks!

-eric

[qcolombet]

I agree with Eric, the whole constant choice seems too magic to me.

[qcolombet]

To be concrete here. I'd like to understand why we can have the regalloc to figure out what is the cost of splitting a CSR the first time (which is what it boils down to).

[Gerolf]

This is interesting. Unfortunately these heuristic changes are always tricky and never satisfying. Is this change motivated entirely by limitations of the current shrink-wrapping algorithm or do you see gains from better allocation also.

-Gerolf

[• wuzish]

Should this good patch be rebased and continued to move on? @wmi
it'd be better to move on this work because D27366 is abandoned and D34608 is not updated for a long time, and those 3 patches are all trying to fix same issue and not landed successfully.
It would be great If it can land.

[wmi]

In D32201#1620644, @wuzish wrote:

Should this good patch be rebased and continued to move on? @wmi
it'd be better to move on this work because D27366 is abandoned and D34608 is not updated for a long time, and those 3 patches are all trying to fix same issue and not landed successfully.
It would be great If it can land.

Thanks for bringing it to attention again.

I still think the patch will be very helpful for some cases especially when dynamic profile information is available (when FDO/SampleFDO is used). It is tricky if there is only static profile available. I will reevaluate the patch and see how it works if I change the patch to be functioning only when we have dynamic profile. If you are more interesting on the case when dynamic profile is not available -- i.e., try to make the patch more general, feel free to take over it and I will be happy to join discussion and review.

[• wuzish]

In D32201#1625379, @wmi wrote:

In D32201#1620644, @wuzish wrote:

Should this good patch be rebased and continued to move on? @wmi
it'd be better to move on this work because D27366 is abandoned and D34608 is not updated for a long time, and those 3 patches are all trying to fix same issue and not landed successfully.
It would be great If it can land.

Thanks for bringing it to attention again.

I still think the patch will be very helpful for some cases especially when dynamic profile information is available (when FDO/SampleFDO is used). It is tricky if there is only static profile available. I will reevaluate the patch and see how it works if I change the patch to be functioning only when we have dynamic profile. If you are more interesting on the case when dynamic profile is not available -- i.e., try to make the patch more general, feel free to take over it and I will be happy to join discussion and review.

How about using block frequency instead of dynamic profile information as reference if dynamic profile information is not available? And CSR cost may need to be adjusted to this comment said https://reviews.llvm.org/D27366#617886. For example, separate 2 cost, one for split and one for spill. And make the digital value sensible that if it's related to the target-dependent cost such as the equivalent number of copy which is related to the cycles between copy instruction and load/store instruction.

lib/CodeGen/RegAllocGreedy.cpp

static cl::opt<bool> EnableDeferredSpilling(
     "enable-deferred-spilling", cl::Hidden,
     cl::desc("Instead of spilling a variable right away, defer the actual "
              "code insertion to the end of the allocation. That way the "
              "allocator might still find a suitable coloring for this "
              "variable because of other evicted variables."),
     cl::init(false));
 
 // FIXME: Find a good default for this flag and remove the flag.
-static cl::opt<unsigned>
-CSRFirstTimeCost("regalloc-csr-first-time-cost",
-              cl::desc("Cost for first time use of callee-saved register."),
-              cl::init(0), cl::Hidden);
+static cl::opt<int> CSRFirstTimeCost(
+    "regalloc-csr-first-time-cost",
+    cl::desc("Cost for first time use of callee-saved register."), cl::init(-1),
+    cl::Hidden);
 
 static RegisterRegAlloc greedyRegAlloc("greedy", "greedy register allocator",
                                        createGreedyRegisterAllocator);
 
 namespace {
 class RAGreedy : public MachineFunctionPass,
                  public RegAllocBase,
                  private LiveRangeEdit::Delegate {

 }
 
 void RAGreedy::aboutToRemoveInterval(LiveInterval &LI) {
   // Do not keep invalid information around.
   SetOfBrokenHints.remove(&LI);
 }
 
 void RAGreedy::initializeCSRCost() {
-  // We use the larger one out of the command-line option and the value report
-  // by TRI.
-  CSRCost = BlockFrequency(
-      std::max((unsigned)CSRFirstTimeCost, TRI->getCSRFirstUseCost()));
+  // The cost from command-line option will override the value reported by TRI.
+  if (CSRFirstTimeCost != -1)
+    CSRCost = BlockFrequency(CSRFirstTimeCost);
+  else
+    CSRCost = BlockFrequency(TRI->getCSRFirstUseCost());
   if (!CSRCost.getFrequency())
     return;
 
   // Raw cost is relative to Entry == 2^14; scale it appropriately.
   uint64_t ActualEntry = MBFI->getEntryFreq();
   if (!ActualEntry) {
     CSRCost = 0;
     return;
do {
     Info.clear();
     collectHintInfo(Reg, Info);
     // Check if recoloring the live-range will increase the cost of the
     // non-identity copies.
     if (CurrPhys != PhysReg) {
       DEBUG(dbgs() << "Checking profitability:\n");
       BlockFrequency OldCopiesCost = getBrokenHintFreq(Info, CurrPhys);
       BlockFrequency NewCopiesCost = getBrokenHintFreq(Info, PhysReg);
+      // If we switch from a non-CSR register to a CSR register, we require
+      // the cost difference is larger than CSRCost to justify the recoloring,
+      // because such recoloring is possible to hinder shrinkwrapping.
+      bool ChangedToCSR = !RegClassInfo.getLastCalleeSavedAlias(CurrPhys) &&
+                          RegClassInfo.getLastCalleeSavedAlias(PhysReg);
       DEBUG(dbgs() << "Old Cost: " << OldCopiesCost.getFrequency()
-                   << "\nNew Cost: " << NewCopiesCost.getFrequency() << '\n');
-      if (OldCopiesCost < NewCopiesCost) {
+                   << "\nNew Cost: " << NewCopiesCost.getFrequency()
+                   << "\nCSRCost: "
+                   << (ChangedToCSR ? CSRCost.getFrequency() : 0) << '\n');
+      if (OldCopiesCost < NewCopiesCost + (ChangedToCSR ? CSRCost : 0)) {
         DEBUG(dbgs() << "=> Not profitable.\n");
         continue;
       }
       // At this point, the cost is either cheaper or equal. If it is
       // equal, we consider this is profitable because it may expose
       // more recoloring opportunities.
       DEBUG(dbgs() << "=> Profitable.\n");
       // Recolor the live-range.

lib/Target/AArch64/AArch64RegisterInfo.h

public:
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const MCPhysReg *
   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
-  unsigned getCSRFirstUseCost() const override {
-    // The cost will be compared against BlockFrequency where entry has the
-    // value of 1 << 14. A value of 5 will choose to spill or split really
-    // cold path instead of using a callee-saved register.
-    return 5;
-  }
+  unsigned getCSRFirstUseCost() const override { return 1 << 13; }
 
   // Calls involved in thread-local variable lookup save more registers than
   // normal calls, so they need a different mask to represent this.
   const uint32_t *getTLSCallPreservedMask() const;
 
   /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
   /// case that 'returned' is on an i64 first argument if the calling convention
   /// is one that can (partially) model this attribute with a preserved mask

lib/Target/ARM/ARMBaseRegisterInfo.h

public:
 
   void getRegAllocationHints(unsigned VirtReg,
                              ArrayRef<MCPhysReg> Order,
                              SmallVectorImpl<MCPhysReg> &Hints,
                              const MachineFunction &MF,
                              const VirtRegMap *VRM,
                              const LiveRegMatrix *Matrix) const override;
 
+  unsigned getCSRFirstUseCost() const override { return 1 << 13; }
+
   void updateRegAllocHint(unsigned Reg, unsigned NewReg,
                           MachineFunction &MF) const override;
 
   bool hasBasePointer(const MachineFunction &MF) const;
 
   bool canRealignStack(const MachineFunction &MF) const override;
   int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
                                    int Idx) const override;

lib/Target/PowerPC/PPCRegisterInfo.h

public:
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   void adjustStackMapLiveOutMask(uint32_t *Mask) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
 
+  unsigned getCSRFirstUseCost() const override { return 1 << 13; }
+
   /// We require the register scavenger.
   bool requiresRegisterScavenging(const MachineFunction &MF) const override {
     return true;
   }
 
   bool requiresFrameIndexScavenging(const MachineFunction &MF) const override {
     return true;
   }

lib/Target/X86/X86RegisterInfo.h

public:
   const MCPhysReg *
   getCalleeSavedRegs(const MachineFunction* MF) const override;
   const MCPhysReg *
   getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   const uint32_t *getNoPreservedMask() const override;
 
+  unsigned getCSRFirstUseCost() const override { return 1 << 13; }
+
   // Calls involved in thread-local variable lookup save more registers than
   // normal calls, so they need a different mask to represent this.
   const uint32_t *getDarwinTLSCallPreservedMask() const;
 
   /// getReservedRegs - Returns a bitset indexed by physical register number
   /// indicating if a register is a special register that has particular uses and
   /// should be considered unavailable at all times, e.g. SP, RA. This is used by
   /// register scavenger to determine what registers are free.

test/CodeGen/ARM/divmod-eabi.ll

 ; WINDOWS-LABEL: g3:
 entry:
   %rem = srem i32 %a, %b
 ; EABI: __aeabi_idivmod
 ; EABI: mov [[mod:r[0-9]+]], r1
 ; DARWIN: __modsi3
 ; DARWIN: mov [[sum:r[0-9]+]], r0
 ; WINDOWS: __rt_sdiv
+; WINDOWS: mov r0, r1
 ; WINDOWS: mov [[rem:r[0-9]+]], r1
   %rem1 = srem i32 %b, %rem
 ; EABI: __aeabi_idivmod
 ; DARWIN: __modsi3
 ; WINDOWS: __rt_sdiv
   %add = add nsw i32 %rem1, %rem
 ; EABI: add r0, r1, [[mod]]
 ; DARWIN: add r0{{.*}}[[sum]]

test/CodeGen/X86/atom-fixup-lea2.ll

 ; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
 ; CHECK:BB#5
-; CHECK-NEXT:leal
+; CHECK-NEXT:addl 12(%esp), %esi
 ; CHECK-NEXT:leal
 ; CHECK-NEXT:leal
 ; CHECK-NEXT:movl
 
 
 ; Test for fixup lea pre-emit pass. LEA instructions should be substituted for
 ; ADD instructions which compute the address and index of the load because they
 ; precede the load within 5 instructions. An LEA should also be substituted for

test/CodeGen/X86/block-placement.ll

 
 define i32 @test_cold_calls(i32* %a) {
 ; Test that edges to blocks post-dominated by cold calls are
 ; marked as not expected to be taken.  They should be laid out
 ; at the bottom.
 ; CHECK-LABEL: test_cold_calls:
 ; CHECK: %entry
 ; CHECK: %else
-; CHECK: %exit
 ; CHECK: %then
 
 entry:
   %gep1 = getelementptr i32, i32* %a, i32 1
   %val1 = load i32, i32* %gep1
   %cond1 = icmp ugt i32 %val1, 1
   br i1 %cond1, label %then, label %else
 

test/CodeGen/X86/csr-split1.ll

+; RUN: llc -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+; Check CSR split can work properly for tests below.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+@cond = common local_unnamed_addr global i64 0, align 8
+@ret = common local_unnamed_addr global i64 0, align 8
+@p = common local_unnamed_addr global i64* null, align 8
+declare void @foo(i64, i64, i64)
+
+; After CSR split, ShrinkWrap is enabled and prologue are moved from entry
+; to BB#1.
+;
+; CHECK-LABEL: test1:
+; CHECK: .LBB0_1:
+; CHECK-NEXT:   push
+; CHECK-NEXT:   push
+; CHECK-NEXT:   push
+; CHECK:        callq foo
+; CHECK:        pop
+; CHECK-NEXT:   pop
+; CHECK-NEXT:   pop
+; CHECK-NEXT:   jmp .LBB0_2
+define void @test1(i64 %i, i64 %j, i64 %k) nounwind {
+entry:
+  %t0 = load i64, i64* @cond, align 8
+  %tobool = icmp eq i64 %t0, 0
+  br i1 %tobool, label %if.end, label %if.then, !prof !0
+
+if.then:                                          ; preds = %entry
+  tail call void @foo(i64 %i, i64 %j, i64 %k)
+  %add = add nsw i64 %j, %i
+  %add1 = add nsw i64 %add, %k
+  store i64 %add1, i64* @ret, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %t1 = load i64*, i64** @p, align 8
+  store volatile i64 3, i64* %t1, align 8
+  ret void
+}
+!0 = !{!"branch_weights", i32 2000, i32 1}
+
+; After CSR split, even if ShrinkWrap is not enabled because stack
+; alloc space is used. param passing moves still can be moved from
+; prologue to BB#1.
+;
+; CHECK-LABEL: test2:
+; CHECK-NEXT: # BB#0:
+; CHECK-NEXT:   pushq  %rbp
+; CHECK-NEXT:   movq  %rsp, %rbp
+; CHECK-NEXT:   pushq  %r15
+; CHECK-NEXT:   pushq  %r14
+; CHECK-NEXT:   pushq  %rbx
+; CHECK-NEXT:   pushq  %rax
+; CHECK-NEXT:   cmpq
+; CHECK-NEXT:   jne .LBB1_1
+; CHECK:      .LBB1_1:
+; CHECK-NEXT:   movq  %rdi,
+; CHECK-NEXT:   movq  %rsi,
+; CHECK-NEXT:   movq  %rdx,
+; CHECK-NEXT:   callq  foo
+;
+define void @test2(i64 %i, i64 %j, i64 %k) nounwind {
+entry:
+  %t0 = load i64, i64* @cond, align 8
+  %tobool = icmp eq i64 %t0, 0
+  br i1 %tobool, label %if.end, label %if.then, !prof !1
+
+if.then:                                          ; preds = %entry
+  tail call void @foo(i64 %i, i64 %j, i64 %k)
+  %add = add nsw i64 %j, %i
+  %add1 = add nsw i64 %add, %k
+  store i64 %add1, i64* @ret, align 8
+  br label %if.end
+
+if.end:                                           ; preds = %entry, %if.then
+  %t1 = alloca [3 x i8], align 16
+  store [3 x i8]* %t1, [3 x i8]** bitcast (i64** @p to [3 x i8]**), align 8
+  ret void
+}
+!1 = !{!"branch_weights", i32 2000, i32 1}

test/CodeGen/X86/mul-i1024.ll

 ; X64-NEXT:    addq %rax, %rbx
 ; X64-NEXT:    adcq %rdx, %rbp
 ; X64-NEXT:    movq 16(%r8), %rax
 ; X64-NEXT:    movq %r8, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    mulq %r9
 ; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill
-; X64-NEXT:    movq %r14, %r9
+; X64-NEXT:    movq %r14, %rdi
+; X64-NEXT:    movq %rdi, %r9
 ; X64-NEXT:    addq %rax, %r9
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    adcq %rdx, %rax
 ; X64-NEXT:    addq %rbx, %r9
 ; X64-NEXT:    adcq %rbp, %rax
 ; X64-NEXT:    movq %rax, %rbp
 ; X64-NEXT:    movq %r11, %rax
 ; X64-NEXT:    movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill
-; X64-NEXT:    addq %r14, %rax
+; X64-NEXT:    addq %rdi, %rax
 ; X64-NEXT:    adcq %rcx, %r15
 ; X64-NEXT:    movq %r15, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq (%r10), %rax
 ; X64-NEXT:    movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    xorl %r15d, %r15d
 ; X64-NEXT:    mulq %r15
 ; X64-NEXT:    movq %rdx, %rsi
-; X64-NEXT:    movq %rax, %rbx
-; X64-NEXT:    addq %r14, %rax
-; X64-NEXT:    movq %r14, %rdi
+; X64-NEXT:    movq %rax, %r14
+; X64-NEXT:    addq %rdi, %rax
 ; X64-NEXT:    movq %rsi, %rax
 ; X64-NEXT:    adcq %rcx, %rax
 ; X64-NEXT:    movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq 32(%r8), %rax
 ; X64-NEXT:    movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    mulq %r15
 ; X64-NEXT:    xorl %r8d, %r8d
 ; X64-NEXT:    movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rdx, -{{[0-9]+}}(%rsp) # 8-byte Spill
-; X64-NEXT:    movq %rbx, %rcx
-; X64-NEXT:    movq %rbx, %r14
+; X64-NEXT:    movq %r14, %rcx
 ; X64-NEXT:    addq %rax, %rcx
 ; X64-NEXT:    movq %rsi, %rax
 ; X64-NEXT:    adcq %rdx, %rax
 ; X64-NEXT:    movq %rax, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    addq %rdi, %r11
 ; X64-NEXT:    movq %r11, {{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rdi, %r11
 ; X64-NEXT:    movq %r11, -{{[0-9]+}}(%rsp) # 8-byte Spill

 ; X64-NEXT:    adcq %rsi, %r8
 ; X64-NEXT:    movq %r11, %rsi
 ; X64-NEXT:    movq 64(%rsi), %r11
 ; X64-NEXT:    movq %r11, %rax
 ; X64-NEXT:    movq %rbx, %rdi
 ; X64-NEXT:    mulq %rdi
 ; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rdx, %rcx
-; X64-NEXT:    movq 72(%rsi), %rbx
-; X64-NEXT:    movq %rbx, %rax
+; X64-NEXT:    movq 72(%rsi), %rax
+; X64-NEXT:    movq %rax, %rbx
 ; X64-NEXT:    mulq %rdi
 ; X64-NEXT:    movq %rdx, %rsi
 ; X64-NEXT:    movq %rax, %rbp
 ; X64-NEXT:    addq %rcx, %rbp
 ; X64-NEXT:    adcq $0, %rsi
 ; X64-NEXT:    movq %r11, %rax
 ; X64-NEXT:    mulq %r15
 ; X64-NEXT:    movq %rdx, %rcx

 ; X64-NEXT:    mulq %r8
 ; X64-NEXT:    movq %rdx, %r8
 ; X64-NEXT:    movq %rax, %r9
 ; X64-NEXT:    addq %rbp, %r9
 ; X64-NEXT:    adcq %rcx, %r8
 ; X64-NEXT:    addq %r13, %r9
 ; X64-NEXT:    adcq %rdi, %r8
 ; X64-NEXT:    movq -{{[0-9]+}}(%rsp), %rsi # 8-byte Reload
-; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rbx # 8-byte Reload
-; X64-NEXT:    imulq %rbx, %rsi
-; X64-NEXT:    movq %rbx, %rax
+; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rax # 8-byte Reload
+; X64-NEXT:    imulq %rax, %rsi
+; X64-NEXT:    movq %rax, %rbx
 ; X64-NEXT:    movq {{[0-9]+}}(%rsp), %rcx # 8-byte Reload
 ; X64-NEXT:    mulq %rcx
 ; X64-NEXT:    movq %rax, %r10
 ; X64-NEXT:    addq %rsi, %rdx
 ; X64-NEXT:    movq {{[0-9]+}}(%rsp), %r11 # 8-byte Reload
 ; X64-NEXT:    imulq %r11, %rcx
 ; X64-NEXT:    addq %rdx, %rcx
 ; X64-NEXT:    movq %rcx, %rsi

test/CodeGen/X86/mul-i512.ll

 ; X64-NEXT:    movq %rbx, %rax
 ; X64-NEXT:    mulq %rcx
 ; X64-NEXT:    movq %rdx, %r13
 ; X64-NEXT:    movq %rax, %r10
 ; X64-NEXT:    movq %r11, %rax
 ; X64-NEXT:    mulq %rcx
 ; X64-NEXT:    movq %rdx, %r9
 ; X64-NEXT:    movq %r9, -{{[0-9]+}}(%rsp) # 8-byte Spill
+; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rax, %r15
-; X64-NEXT:    movq %r15, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    addq %r10, %r15
 ; X64-NEXT:    adcq %r13, %r9
 ; X64-NEXT:    addq %rbp, %r15
 ; X64-NEXT:    adcq %rsi, %r9
 ; X64-NEXT:    movq %rdi, -{{[0-9]+}}(%rsp) # 8-byte Spill
-; X64-NEXT:    movq (%rdi), %r14
-; X64-NEXT:    movq %r14, %rax
+; X64-NEXT:    movq (%rdi), %rax
+; X64-NEXT:    movq %rax, %r14
 ; X64-NEXT:    mulq %rbx
 ; X64-NEXT:    movq %rax, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    movq %rdx, %r11
 ; X64-NEXT:    movq 8(%rdi), %rcx
 ; X64-NEXT:    movq %rcx, %rax
 ; X64-NEXT:    movq %rcx, -{{[0-9]+}}(%rsp) # 8-byte Spill
 ; X64-NEXT:    mulq %rbx
 ; X64-NEXT:    movq %rdx, %rbp

test/CodeGen/X86/ragreedy-bug.ll

-; RUN: llc < %s -mtriple=x86_64-apple-macosx -regalloc=greedy | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx -regalloc=greedy -regalloc-csr-first-time-cost=0 | FileCheck %s
 
 ; This testing case is reduced from 197.parser prune_match function.
 ; We make sure register copies are not generated on isupper.exit blocks.
 
 ; isupper.exit and isupper.exit223 get tail-duplicated into all their
 ; predecessors.
 ; CHECK: cond.true.i.i
 ; CHECK-NEXT: in Loop

test/CodeGen/X86/ragreedy-hoist-spill.ll

-; RUN: llc < %s -mtriple=x86_64-apple-macosx -regalloc=greedy | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-macosx -regalloc=greedy -regalloc-csr-first-time-cost=0 | FileCheck %s
 
 ; This testing case is reduced from 254.gap SyFgets function.
 ; We make sure a spill is hoisted to a cold BB inside the hotter outer loop.
 
 %struct.TMP.1 = type { %struct.TMP.2*, %struct.TMP.2*, [1024 x i8] }
 %struct.TMP.2 = type { i8*, i32, i32, i16, i16, %struct.TMP.3, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.TMP.3, %struct.TMP.4*, i32, [3 x i8], [1 x i8], %struct.TMP.3, i32, i64 }
 %struct.TMP.4 = type opaque
 %struct.TMP.3 = type { i8*, i32 }

test/CodeGen/X86/sjlj-eh.ll

 ; CHECK: leal -64(%ebp), %eax
 ; CHECK: pushl %eax
 ; CHECK: calll __Unwind_SjLj_Register
 ; CHECK: addl $4, %esp
 ;     function_that_throws();
 ; CHECK: calll __Z20function_that_throwsv
 ;     _Unwind_SjLj_Unregister(&UFC);
 ; CHECK: leal -64(%ebp), %eax
+; CHECK: pushl %eax
 ; CHECK: calll __Unwind_SjLj_Unregister
 ;
 ; CHECK: [[RESUME]]:
-; CHECK: leal -64(%ebp), %esi
 ;     assert(UFC.__callsite <= 1);
 ; CHECK: movl -60(%ebp), %eax
 ; CHECK: cmpl $1, %eax
 ; CHECK: jbe [[CONT:LBB[0-9]+_[0-9]+]]
 ; CHECK: ud2
 ; CHECK: [[CONT]]:
 ;     *Handlers[--UFC.__callsite]
 ; CHECK: subl $1, %eax
 ; CHECK: jmpl *LJTI
 

test/CodeGen/X86/x86-shrink-wrapping.ll

 ; CHECK-LABEL: irreducibleCFG:
 ; CHECK: %entry
 ; Make sure the prologue happens in the entry block.
 ; CHECK-NEXT: pushq
 ; ...
 ; Make sure the epilogue happens in the exit block.
 ; CHECK-NOT: popq
 ; CHECK: popq
-; CHECK-NEXT: popq
 ; CHECK-NEXT: retq
 define i32 @irreducibleCFG() #4 {
 entry:
   %i0 = load i32, i32* @irreducibleCFGa, align 4
   %.pr = load i8, i8* @irreducibleCFGf, align 1
   %bool = icmp eq i8 %.pr, 0
   br i1 %bool, label %split, label %preheader
 

test/DebugInfo/X86/live-debug-values.ll

-; RUN: llc -filetype=asm %s -o - | FileCheck %s
+; RUN: llc -filetype=asm -regalloc-csr-first-time-cost=0 %s -o - | FileCheck %s
 
 ; Test the extension of debug ranges from predecessors.
 ; Generated from the source file LiveDebugValues.c:
 ; #include <stdio.h>
 ; int m;
 ; extern int inc(int n); 
 ; extern int change(int n); 
 ; extern int modify(int n);