[X86][GlobalISel] Add minimal call lowering support to the IRTranslator

[zvi]

Summary

Add basic functionality to support call lowering for X86.
Currently only supports functions which return void and take zero arguments.
Inspired by commit 286573.

[davide]

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

[zvi]

In D26593#593918, @davide wrote:

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

I believe that @echristo's concern was about running in a mixed mode of existing ISel (SelectionDAG) and Global ISel, but better let him speak for himself.
At the moment I am not aware of plans to run the X86 ISel in such a mixed mode. This patch is intended to jumpstart implemention of the X86 part of the Global Isel as designed by the team lead by Quentin and in par with the documentation. The development team presented the current status of the work on Global ISel at the recent dev meeting, and called out to developers of other targets to join this effort. We agreed that we could start development of the X86 part in low gear and speed-up after some additional work will be completed, mainly related to tablegen uses.

[davide]

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

In D26593#593922, @zvi wrote:

In D26593#593918, @davide wrote:

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

I believe that @echristo's concern was about running in a mixed mode of existing ISel (SelectionDAG) and Global ISel, but better let him speak for himself.
At the moment I am not aware of plans to run the X86 ISel in such a mixed mode. This patch is intended to jumpstart implemention of the X86 part of the Global Isel as designed by the team lead by Quentin and in par with the documentation. The development team presented the current status of the work on Global ISel at the recent dev meeting, and called out to developers of other targets to join this effort. We agreed that we could start development of the X86 part in low gear and speed-up after some additional work will be completed, mainly related to tablegen uses.

OK, I apologize if I missed the whole plan. So, is the goal that of growing this prototype into something ready for production? I remember there were some aspects that, although valuable, were voluntarily ignored for the prototype timeframe because there wasn't enough time (e.g. reuse of instcombine for the new selector).
I'm pretty sure there are others (which I don't have off the top of my head).
Are these aspects being reconsidered now (out of curiosity)?

[dberris]

It's really hard for me to see how this works without a more useful/completed implementation. It's also very under-specified at this time.

lib/Target/X86/X86CallLowering.cpp

30–39 ↗

(On Diff #77752)

I'm interested in this bit -- how will a return be lowered? i.e. what will call this function, and will it happen for any instruction that counts as a return?

lib/Target/X86/X86CallLowering.h

32–33 ↗

(On Diff #77752)

I may be missing something obvious, but why does call lowering need to lower a return? I would have thought return-lowering might happen in function lowering.

[hfinkel]

In D26593#593918, @davide wrote:

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

Frankly, I see no better way to give GlobalISel the scrutiny it requires than by starting to port backends to it. We just need to have the right mindset about it.

[mehdi_amini]

In D26593#594014, @hfinkel wrote:

In D26593#593918, @davide wrote:

Picking this one (but the same applies to the ARM global isel skeleton commit).
I'm a little bit concerned to see various targets moving to global isel without proper scrutiny, as already pointed out by @echristo on llvm-dev. Don't get me wrong, I'm personally very excited about the whole idea, and it's likely that my organization will put some resources on it in the foreseeable future, but I would be less worried if Eric's concerns are addressed before moving forward.

Frankly, I see no better way to give GlobalISel the scrutiny it requires than by starting to port backends to it. We just need to have the right mindset about it.

There is always a tradeoff though: it makes harder to change pieces of the design as you increase the number of client of a framework/API. So it has to be carefully planned. But the core devs of GlobalISel are the best people to evaluate this tradeoff!

[zvi]

lib/Target/X86/X86CallLowering.cpp

30–39 ↗

(On Diff #77752)

This target hook is called by the IRTranslator to lower a LLVM IR 'ret' instruction to the target's preferred machine IR sequence. See IRTranslator::translateRet().

lib/Target/X86/X86CallLowering.h

32–33 ↗

(On Diff #77752)

The CallLowering interface is a target-hook for lowering both caller and calee -related constructs. This patch only implements the callee part. The caller-part (i.e. lowering call sites) will be added in the future.

[dberris]

lib/Target/X86/X86CallLowering.h

32–33 ↗

(On Diff #77752)

I think I'm still missing something but maybe this is because of my confusion in naming -- this class is named X86CallLowering but it's implementing the lowering of the return instruction and the formal arguments.

Wouldn't the function-lowering specific ("callee-side") code be better in a class named more appropriately specifically for function-lowering? Because I might expect to see that code alongside stack adjustment and prologue/epilogue lowering of a function rather than for lowering "calls".

Does that make sense?

[zvi]

lib/Target/X86/X86CallLowering.h

32–33 ↗

(On Diff #77752)

We are going off-topic, but i don't mind to continue this discussion if you find it useful.

this class is named X86CallLowering but it's implementing the lowering of the return instruction and the formal arguments.
Wouldn't the function-lowering specific ("callee-side") code be better in a class named more appropriately specifically for function-lowering?

This class also inherits empty overloads of a method named lowerCall(). A follow-up task is to override these methods.

Because I might expect to see that code alongside stack adjustment and prologue/epilogue lowering of a function rather than for lowering "calls".

If you haven't done this already, I suggest you read the documentation about the LLVM Codegen [http://llvm.org/docs/CodeGenerator.html], There you will see that in the codegen-scale the initial lowering of LLVM IR to Machine IR and prologue/epilogue insertion happen in different (and distant) stages. Just to give you perspective, Global ISel only intends to replace the "Instruction Selection" phase of the entire code-generation pipe.

[zvi]

In D26593#593924, @davide wrote:

OK, I apologize if I missed the whole plan. So, is the goal that of growing this prototype into something ready for production? I remember there were some aspects that, although valuable, were voluntarily ignored for the prototype timeframe because there wasn't enough time (e.g. reuse of instcombine for the new selector).
I'm pretty sure there are others (which I don't have off the top of my head).
Are these aspects being reconsidered now (out of curiosity)?

No need to apologize - you should feel free to raise your concerns.
The questions in your last comment are about GlobalISel in general which I would prefer the core development team (which are also the reviewers) answer them. Perhaps open a thread in llvm-dev?

[t.p.northover]

From a GlobalISel perspective this looks like the obvious minimal x86 stub.

I think Zvi said he might be experimenting with IRTranslator coverage at the conference, so I assume this is part of making sure that work can be used by anyone else with an interest.

[zvi]

Thanks for the review, Tim.

In D26593#595109, @t.p.northover wrote:

From a GlobalISel perspective this looks like the obvious minimal x86 stub.

I think Zvi said he might be experimenting with IRTranslator coverage at the conference, so I assume this is part of making sure that work can be used by anyone else with an interest.

I was not me. It was Philip if I am not mistaken.

llvm/trunk/lib/Target/X86/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS X86.td)
 
 tablegen(LLVM X86GenRegisterInfo.inc -gen-register-info)
 tablegen(LLVM X86GenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM X86GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM X86GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM X86GenAsmMatcher.inc -gen-asm-matcher)
 tablegen(LLVM X86GenDAGISel.inc -gen-dag-isel)
 tablegen(LLVM X86GenFastISel.inc -gen-fast-isel)
 tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
 tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
 add_public_tablegen_target(X86CommonTableGen)
 
+# Add GlobalISel files if the build option was enabled.
+set(GLOBAL_ISEL_FILES
+  X86CallLowering.cpp
+  )
+
+if(LLVM_BUILD_GLOBAL_ISEL)
+  set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES})
+else()
+  set(GLOBAL_ISEL_BUILD_FILES "")
+  set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES})
+endif()
+
+
 set(sources
   X86AsmPrinter.cpp
   X86CallFrameOptimization.cpp
   X86ExpandPseudo.cpp
   X86FastISel.cpp
   X86FixupBWInsts.cpp
   X86FixupLEAs.cpp
   X86FixupSetCC.cpp
set(sources
   X86ShuffleDecodeConstantPool.cpp
   X86Subtarget.cpp
   X86TargetMachine.cpp
   X86TargetObjectFile.cpp
   X86TargetTransformInfo.cpp
   X86VZeroUpper.cpp
   X86WinAllocaExpander.cpp
   X86WinEHState.cpp
+  ${GLOBAL_ISEL_BUILD_FILES}
   )
 
 add_llvm_target(X86CodeGen ${sources})
 
 add_subdirectory(AsmParser)
 add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
 add_subdirectory(Utils)

llvm/trunk/lib/Target/X86/LLVMBuild.txt

 has_asmprinter = 1
 has_disassembler = 1
 has_jit = 1
 
 [component_1]
 type = Library
 name = X86CodeGen
 parent = X86
-required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils
+required_libraries = Analysis AsmPrinter CodeGen Core MC SelectionDAG Support Target X86AsmPrinter X86Desc X86Info X86Utils GlobalISel
 add_to_library_groups = X86

llvm/trunk/lib/Target/X86/X86CallLowering.h

+//===-- llvm/lib/Target/X86/X86CallLowering.h - Call lowering -----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file describes how to lower LLVM calls to machine code calls.
+///
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_LIB_TARGET_X86_X86CALLLOWERING
+#define LLVM_LIB_TARGET_X86_X86CALLLOWERING
+
+#include "llvm/ADT/ArrayRef.h"
+#include "llvm/CodeGen/GlobalISel/CallLowering.h"
+
+namespace llvm {
+
+class Function;
+class MachineIRBuilder;
+class X86TargetLowering;
+class Value;
+
+class X86CallLowering : public CallLowering {
+public:
+  X86CallLowering(const X86TargetLowering &TLI);
+
+  bool lowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val,
+                   unsigned VReg) const override;
+
+  bool lowerFormalArguments(MachineIRBuilder &MIRBuilder, const Function &F,
+                            ArrayRef<unsigned> VRegs) const override;
+};
+} // End of namespace llvm;
+#endif

llvm/trunk/lib/Target/X86/X86CallLowering.cpp

+//===-- llvm/lib/Target/X86/X86CallLowering.cpp - Call lowering -----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+///
+/// \file
+/// This file implements the lowering of LLVM calls to machine code calls for
+/// GlobalISel.
+///
+//===----------------------------------------------------------------------===//
+
+#include "X86CallLowering.h"
+#include "X86ISelLowering.h"
+#include "X86InstrInfo.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
+
+using namespace llvm;
+
+#ifndef LLVM_BUILD_GLOBAL_ISEL
+#error "This shouldn't be built without GISel"
+#endif
+
+X86CallLowering::X86CallLowering(const X86TargetLowering &TLI)
+    : CallLowering(&TLI) {}
+
+bool X86CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
+                                  const Value *Val, unsigned VReg) const {
+  // TODO: handle functions returning non-void values.
+  if (Val)
+    return false;
+
+  MIRBuilder.buildInstr(X86::RET).addImm(0);
+
+  return true;
+}
+
+bool X86CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
+                                           const Function &F,
+                                           ArrayRef<unsigned> VRegs) const {
+  // TODO: handle functions with one or more arguments.
+  return F.arg_empty();
+}

llvm/trunk/lib/Target/X86/X86Subtarget.h

 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
 
 #include "X86FrameLowering.h"
 #include "X86ISelLowering.h"
 #include "X86InstrInfo.h"
 #include "X86SelectionDAGInfo.h"
 #include "llvm/ADT/Triple.h"
+#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/Target/TargetSubtargetInfo.h"
 #include <string>
 
 #define GET_SUBTARGETINFO_HEADER
 #include "X86GenSubtargetInfo.inc"
 
 namespace llvm {
protected:
   unsigned MaxInlineSizeThreshold;
 
   /// What processor and OS we're targeting.
   Triple TargetTriple;
 
   /// Instruction itineraries for scheduling
   InstrItineraryData InstrItins;
 
+  /// Gather the accessor points to GlobalISel-related APIs.
+  /// This is used to avoid ifndefs spreading around while GISel is
+  /// an optional library.
+  std::unique_ptr<GISelAccessor> GISel;
 private:
 
   /// Override the stack alignment.
   unsigned StackAlignOverride;
 
   /// True if compiling for 64-bit, false for 16-bit or 32-bit.
   bool In64BitMode;
 

 
 public:
   /// This constructor initializes the data members to match that
   /// of the specified triple.
   ///
   X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
                const X86TargetMachine &TM, unsigned StackAlignOverride);
 
+  /// This object will take onwership of \p GISelAccessor.
+  void setGISelAccessor(GISelAccessor &GISel) { this->GISel.reset(&GISel); }
+
   const X86TargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
   const X86FrameLowering *getFrameLowering() const override {
     return &FrameLowering;
   }
   const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
public:
   /// Returns the maximum memset / memcpy size
   /// that still makes it profitable to inline the call.
   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
 
+  /// Methods used by Global ISel
+  const CallLowering *getCallLowering() const override;
+  const InstructionSelector *getInstructionSelector() const override;
+  const LegalizerInfo *getLegalizerInfo() const override;
+  const RegisterBankInfo *getRegBankInfo() const override;
 private:
   /// Initialize the full set of dependencies so we can use an initializer
   /// list for X86Subtarget.
   X86Subtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
   void initializeEnvironment();
   void initSubtargetFeatures(StringRef CPU, StringRef FS);
 public:
   /// Is this x86_64? (disregarding specific ABI / programming model)

llvm/trunk/lib/Target/X86/X86Subtarget.cpp

X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
   else if (isTargetCOFF())
     setPICStyle(PICStyles::None);
   else if (isTargetDarwin())
     setPICStyle(PICStyles::StubPIC);
   else if (isTargetELF())
     setPICStyle(PICStyles::GOT);
 }
 
+const CallLowering *X86Subtarget::getCallLowering() const {
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getCallLowering();
+}
+
+const InstructionSelector *X86Subtarget::getInstructionSelector() const {
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getInstructionSelector();
+}
+
+const LegalizerInfo *X86Subtarget::getLegalizerInfo() const {
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getLegalizerInfo();
+}
+
+const RegisterBankInfo *X86Subtarget::getRegBankInfo() const {
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getRegBankInfo();
+}
+
 bool X86Subtarget::enableEarlyIfConversion() const {
   return hasCMov() && X86EarlyIfConv;
 }
 

llvm/trunk/lib/Target/X86/X86TargetMachine.cpp

 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the X86 specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
 
 #include "X86TargetMachine.h"
 #include "X86.h"
+#include "X86CallLowering.h"
 #include "X86TargetObjectFile.h"
 #include "X86TargetTransformInfo.h"
+#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
+#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/LegacyPassManager.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/FormattedStream.h"
 #include "llvm/Support/TargetRegistry.h"
 #include "llvm/Target/TargetOptions.h"
 using namespace llvm;
 
 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
                                cl::desc("Enable the machine combiner pass"),
                                cl::init(true), cl::Hidden);
 
 namespace llvm {
 void initializeWinEHStatePassPass(PassRegistry &);
 }
 
 extern "C" void LLVMInitializeX86Target() {
   // Register the target.
   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
+  initializeGlobalISel(PR);
   initializeWinEHStatePassPass(PR);
   initializeFixupBWInstPassPass(PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO()) {
     if (TT.getArch() == Triple::x86_64)
       return make_unique<X86_64MachoTargetObjectFile>();
X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
   if ((TT.isOSWindows() && TT.getArch() == Triple::x86_64) || TT.isPS4())
     this->Options.TrapUnreachable = true;
 
   initAsmInfo();
 }
 
 X86TargetMachine::~X86TargetMachine() {}
 
+#ifdef LLVM_BUILD_GLOBAL_ISEL
+namespace {
+struct X86GISelActualAccessor : public GISelAccessor {
+  std::unique_ptr<CallLowering> CL;
+  X86GISelActualAccessor(CallLowering* CL): CL(CL) {}
+  const CallLowering *getCallLowering() const override {
+    return CL.get();
+  }
+  const InstructionSelector *getInstructionSelector() const override {
+    //TODO: Implement
+    return nullptr;
+  }
+  const class LegalizerInfo *getLegalizerInfo() const override {
+    //TODO: Implement
+    return nullptr;
+  }
+  const RegisterBankInfo *getRegBankInfo() const override {
+    //TODO: Implement
+    return nullptr;
+  }
+};
+} // End anonymous namespace.
+#endif
 const X86Subtarget *
 X86TargetMachine::getSubtargetImpl(const Function &F) const {
   Attribute CPUAttr = F.getFnAttribute("target-cpu");
   Attribute FSAttr = F.getFnAttribute("target-features");
 
   StringRef CPU = !CPUAttr.hasAttribute(Attribute::None)
                       ? CPUAttr.getValueAsString()
                       : (StringRef)TargetCPU;
X86TargetMachine::getSubtargetImpl(const Function &F) const {
   auto &I = SubtargetMap[Key];
   if (!I) {
     // This needs to be done before we create a new subtarget since any
     // creation will depend on the TM and the code generation flags on the
     // function that reside in TargetOptions.
     resetTargetOptions(F);
     I = llvm::make_unique<X86Subtarget>(TargetTriple, CPU, FS, *this,
                                         Options.StackAlignmentOverride);
+#ifndef LLVM_BUILD_GLOBAL_ISEL
+    GISelAccessor *GISel = new GISelAccessor();
+#else
+    X86GISelActualAccessor *GISel = new X86GISelActualAccessor(
+        new X86CallLowering(*I->getTargetLowering()));
+#endif
+    I->setGISelAccessor(*GISel);
   }
   return I.get();
 }
 
 //===----------------------------------------------------------------------===//
 // Command line options for x86
 //===----------------------------------------------------------------------===//
 static cl::opt<bool>
X86PassConfig(X86TargetMachine *TM, PassManagerBase &PM)
     : TargetPassConfig(TM, PM) {}
 
   X86TargetMachine &getX86TargetMachine() const {
     return getTM<X86TargetMachine>();
   }
 
   void addIRPasses() override;
   bool addInstSelector() override;
-  bool addILPOpts() override;
+#ifdef LLVM_BUILD_GLOBAL_ISEL
+  bool addIRTranslator() override;
+  bool addLegalizeMachineIR() override;
+  bool addRegBankSelect() override;
+  bool addGlobalInstructionSelect() override;
+#endif
   bool addPreISel() override;
   void addPreRegAlloc() override;
   void addPostRegAlloc() override;
   void addPreEmitPass() override;
   void addPreSched2() override;
 };
 } // namespace
 
bool X86PassConfig::addInstSelector() {
   if (TM->getTargetTriple().isOSBinFormatELF() &&
       getOptLevel() != CodeGenOpt::None)
     addPass(createCleanupLocalDynamicTLSPass());
 
   addPass(createX86GlobalBaseRegPass());
   return false;
 }
 
+#ifdef LLVM_BUILD_GLOBAL_ISEL
+bool X86PassConfig::addIRTranslator() {
+  addPass(new IRTranslator());
+  return false;
+}
+
+bool X86PassConfig::addLegalizeMachineIR() {
+  //TODO: Implement
+  return false;
+}
+
+bool X86PassConfig::addRegBankSelect() {
+  //TODO: Implement
+  return false;
+}
+
+bool X86PassConfig::addGlobalInstructionSelect() {
+  //TODO: Implement
+  return false;
+}
+#endif
+
 bool X86PassConfig::addILPOpts() {
   addPass(&EarlyIfConverterID);
   if (EnableMachineCombinerPass)
     addPass(&MachineCombinerID);
   return true;
 }
 
 bool X86PassConfig::addPreISel() {

llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll

+; RUN: llc -mtriple i386 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+; RUN: llc -mtriple x86_64 -global-isel -stop-after=irtranslator %s -o - | FileCheck %s
+
+define void @test_void_return() {
+; CHECK-LABEL: name:            test_void_return
+; CHECK:      alignment:       4
+; CHECK-NEXT: exposesReturnsTwice: false
+; CHECK-NEXT: legalized:       false
+; CHECK-NEXT: regBankSelected: false
+; CHECK-NEXT: selected:        false
+; CHECK-NEXT: tracksRegLiveness: true
+; CHECK-NEXT: frameInfo:
+; CHECK-NEXT:   isFrameAddressTaken: false
+; CHECK-NEXT:   isReturnAddressTaken: false
+; CHECK-NEXT:   hasStackMap:     false
+; CHECK-NEXT:   hasPatchPoint:   false
+; CHECK-NEXT:   stackSize:       0
+; CHECK-NEXT:   offsetAdjustment: 0
+; CHECK-NEXT:   maxAlignment:    0
+; CHECK-NEXT:   adjustsStack:    false
+; CHECK-NEXT:   hasCalls:        false
+; CHECK-NEXT:   maxCallFrameSize: 0
+; CHECK-NEXT:   hasOpaqueSPAdjustment: false
+; CHECK-NEXT:   hasVAStart:      false
+; CHECK-NEXT:   hasMustTailInVarArgFunc: false
+; CHECK-NEXT: body:
+; CHECK-NEXT:   bb.0:
+; CHECK-NEXT:     RET 0
+entry:
+  ret void
+}

llvm/trunk/test/CodeGen/X86/GlobalISel/lit.local.cfg

+if not 'global-isel' in config.root.available_features:
+    config.unsupported = True