[X86][CodeGen] Add a dag pattern to fix #64323

[Peter]

Summary

After recent patch D30189, #64323's error message become a new one.
When DAGCombiner was optimizing (vextract (scalar_to_vector val, 0) -> val, it didn't
consider the possibility that the inserted value type has less bit than the dest type.
This patch fixes that.

[pengfei]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

21705–21708

The comments need update.

21714

Do not use else when the previous condition ends with return.

21716

ditto.

[RKSimon]

llvm/test/CodeGen/X86/pr64323.ll

6

nounwind to reduce cfi noise

[goldstein.w.n]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

21714

you can also just remove second if entirely.

[Peter]

Update comment per request.

[Peter]

nounwind for testcases to reduce noise.

[pengfei]

LGTM.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

if (VecOp.getOpcode() == ISD::INSERT_VECTOR_ELT &&
     return VecVT.isInteger() ? DAG.getAnyExtOrTrunc(Elt, DL, ScalarVT) : Elt;
   }
 
   // (vextract (scalar_to_vector val, 0) -> val
   if (VecOp.getOpcode() == ISD::SCALAR_TO_VECTOR) {
     // Only 0'th element of SCALAR_TO_VECTOR is defined.
     if (DAG.isKnownNeverZero(Index))
       return DAG.getUNDEF(ScalarVT);
 
-    // Check if the result type doesn't match the inserted element type. A
-    // SCALAR_TO_VECTOR may truncate the inserted element and the
-    // EXTRACT_VECTOR_ELT may widen the extracted vector.
+    // Check if the result type doesn't match the inserted element type. 
+    // The inserted element and extracted element may have mismatched bitwidth.
+    // As a result, EXTRACT_VECTOR_ELT may extend or truncate the extracted vector.
     SDValue InOp = VecOp.getOperand(0);
     if (InOp.getValueType() != ScalarVT) {
-      assert(InOp.getValueType().isInteger() && ScalarVT.isInteger() &&
-             InOp.getValueType().bitsGT(ScalarVT));
+      assert(InOp.getValueType().isInteger() && ScalarVT.isInteger());
+      if (InOp.getValueType().bitsGT(ScalarVT))
         return DAG.getNode(ISD::TRUNCATE, DL, ScalarVT, InOp);
+      return DAG.getNode(ISD::ANY_EXTEND, DL, ScalarVT, InOp);
     }
     return InOp;
   }
 
   // extract_vector_elt of out-of-bounds element -> UNDEF
   auto *IndexC = dyn_cast<ConstantSDNode>(Index);
   if (IndexC && VecVT.isFixedLengthVector() &&
       IndexC->getAPIntValue().uge(VecVT.getVectorNumElements()))
     return DAG.getUNDEF(ScalarVT);
 

llvm/test/CodeGen/X86/pr64323.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+
+; RUN: llc < %s -mtriple=x86_64 -mcpu=icelake-server | FileCheck %s
+
+define <1 x i1> @f(<1 x float> %0) nounwind {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    vcmpeqss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %k0
+; CHECK-NEXT:    kmovd %k0, %edi
+; CHECK-NEXT:    callq g@PLT
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+  %A = fcmp oeq <1 x float> %0, <float 0x36A0000000000000>
+  %B = call <1 x i1> @g(<1 x i1> %A)
+  ret <1 x i1> %B
+}
+
+declare <1 x i1> @g(<1 x i1> %0) nounwind