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Differential D157770

[RISCV][GISel] Make s32 a legal type for RV64 for any operation that has a W version.
ClosedPublic

Authored by craig.topper on Aug 11 2023, 7:58 PM.

Details

Reviewers
nitinjohnraj
reames
asb
arsenm
Commits
rGb41e75c8a422: [RISCV][GISel] Make s32 a legal type for RV64 for any operation that has a W…
Summary

My thought is that we can directly select W instructions using s32.

This will likely require combines and other optimizations eventually,
but this makes a simple starting point.

I'm slowly prototyping a similar approach for SelectionDAG.

Diff Detail

Event Timeline

craig.topper created this revision.Aug 11 2023, 7:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2023, 7:58 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 27 others. · View Herald Transcript
craig.topper requested review of this revision.Aug 11 2023, 7:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 11 2023, 7:58 PM
Herald added subscribers: wangpc, eopXD, MaskRay, wdng. · View Herald Transcript
Harbormaster completed remote builds in B252076: Diff 549567.Aug 11 2023, 9:36 PM
reames accepted this revision.Aug 14 2023, 9:22 AM

LGTM

For context, Craig and I chatted about general directions here for a good while on Friday. This is not a high confidence statement that we'll definitely end up with i32 legal on RV64. It's instead a low confidence guess as to where SDAG will be in about a year. If it turns out we're wrong, we'll reverse direction and move GISEL towards the current model that SDAG is using. We're so far from O3 code quality on GISEL that we don't expect to hit the code quality questions in practice to well beyond that rough 1yr timeline.

So basically, if you're looking at this later and think we went the wrong direction, it's entirely possible you're right.

This revision is now accepted and ready to land.Aug 14 2023, 9:22 AM
craig.topper updated this revision to Diff 550022.Aug 14 2023, 10:40 AM

Rebase

Harbormaster completed remote builds in B252426: Diff 550022.Aug 14 2023, 4:15 PM
craig.topper updated this revision to Diff 551325.Aug 17 2023, 4:55 PM

Rebase

Herald added a subscriber: sunshaoce. · View Herald TranscriptAug 17 2023, 4:55 PM
Harbormaster completed remote builds in B253351: Diff 551325.Aug 17 2023, 5:36 PM
craig.topper mentioned this in D76051: [RISCV][GlobalISel] Select register banks for GPR ALU instructions.Aug 17 2023, 11:01 PM
craig.topper updated this revision to Diff 551715.Aug 19 2023, 12:44 AM

Rebase

Harbormaster completed remote builds in B253631: Diff 551715.Aug 19 2023, 1:37 AM
This revision was landed with ongoing or failed builds.Aug 19 2023, 11:21 AM
Closed by commit rGb41e75c8a422: [RISCV][GISel] Make s32 a legal type for RV64 for any operation that has a W… (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGb41e75c8a422: [RISCV][GISel] Make s32 a legal type for RV64 for any operation that has a W….

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
GISel/
14 lines
test/
CodeGen/
RISCV/
GlobalISel/
legalizer/
rv64/
28 lines
12 lines
42 lines
11 lines
9 lines
28 lines

Diff 550022

llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp

//===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===// //===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===//
Lint: Lint
Inline Actions

clang-format not found in user’s local PATH; not linting file.

Lint: Lint: clang-format not found in user’s local PATH; not linting file.
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
/// This file implements the targeting of the Machinelegalizer class for RISC-V. /// This file implements the targeting of the Machinelegalizer class for RISC-V.
/// \todo This should be generated by TableGen. /// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "RISCVLegalizerInfo.h" #include "RISCVLegalizerInfo.h"
#include "RISCVSubtarget.h" #include "RISCVSubtarget.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
using namespace llvm; using namespace llvm;
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) { RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
const unsigned XLen = ST.getXLen(); const unsigned XLen = ST.getXLen();
const LLT s32 = LLT::scalar(32);
const LLT XLenLLT = LLT::scalar(XLen); const LLT XLenLLT = LLT::scalar(XLen);
const LLT p0 = LLT::pointer(0, XLen); const LLT p0 = LLT::pointer(0, XLen);
using namespace TargetOpcode; using namespace TargetOpcode;
getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR}) getActionDefinitionsBuilder({G_AND, G_OR, G_XOR})
.legalFor({XLenLLT}) .legalFor({XLenLLT})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder({G_ADD, G_SUB})
.legalFor({s32, XLenLLT})
.widenScalarToNextPow2(0)
.clampScalar(0, s32, XLenLLT);
getActionDefinitionsBuilder( getActionDefinitionsBuilder(
{G_UADDE, G_UADDO, G_USUBE, G_USUBO, G_SADDE, G_SADDO, G_SSUBE, G_SSUBO}) {G_UADDE, G_UADDO, G_USUBE, G_USUBO, G_SADDE, G_SADDO, G_SSUBE, G_SSUBO})
.legalFor({{XLenLLT, XLenLLT}}) .legalFor({{XLenLLT, XLenLLT}})
.clampScalar(0, XLenLLT, XLenLLT) .clampScalar(0, XLenLLT, XLenLLT)
.clampScalar(1, XLenLLT, XLenLLT) .clampScalar(1, XLenLLT, XLenLLT)
.widenScalarToNextPow2(0); .widenScalarToNextPow2(0);
getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL}) getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
.legalFor({{XLenLLT, XLenLLT}}) .legalFor({{s32, s32}, {s32, XLenLLT}, {XLenLLT, XLenLLT}})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(1, XLenLLT, XLenLLT) .clampScalar(1, XLenLLT, XLenLLT)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
// Extensions // Extensions
auto ExtLegalFunc = [=](const LegalityQuery &Query) { auto ExtLegalFunc = [=](const LegalityQuery &Query) {
unsigned DstSize = Query.Types[0].getSizeInBits(); unsigned DstSize = Query.Types[0].getSizeInBits();
Show All 26 Lines for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
getActionDefinitionsBuilder(Op) getActionDefinitionsBuilder(Op)
.widenScalarToNextPow2(LitTyIdx, XLen) .widenScalarToNextPow2(LitTyIdx, XLen)
.widenScalarToNextPow2(BigTyIdx, XLen) .widenScalarToNextPow2(BigTyIdx, XLen)
.clampScalar(LitTyIdx, XLenLLT, XLenLLT) .clampScalar(LitTyIdx, XLenLLT, XLenLLT)
.clampScalar(BigTyIdx, XLenLLT, XLenLLT); .clampScalar(BigTyIdx, XLenLLT, XLenLLT);
} }
getActionDefinitionsBuilder({G_CONSTANT, G_IMPLICIT_DEF}) getActionDefinitionsBuilder({G_CONSTANT, G_IMPLICIT_DEF})
.legalFor({XLenLLT, p0}) .legalFor({s32, XLenLLT, p0})
.widenScalarToNextPow2(0) .widenScalarToNextPow2(0)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, s32, XLenLLT);
getActionDefinitionsBuilder(G_ICMP) getActionDefinitionsBuilder(G_ICMP)
.legalFor({{XLenLLT, XLenLLT}}) .legalFor({{XLenLLT, XLenLLT}})
.widenScalarToNextPow2(1) .widenScalarToNextPow2(1)
.clampScalar(1, XLenLLT, XLenLLT) .clampScalar(1, XLenLLT, XLenLLT)
.clampScalar(0, XLenLLT, XLenLLT); .clampScalar(0, XLenLLT, XLenLLT);
getActionDefinitionsBuilder(G_SELECT) getActionDefinitionsBuilder(G_SELECT)
Show All 16 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s # RUN: | FileCheck %s
--- ---
name: add_i8 name: add_i8
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i8 ; CHECK-LABEL: name: add_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[ADD]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64) %3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_ADD %2, %3 %4:_(s8) = G_ADD %2, %3
%5:_(s64) = G_ANYEXT %4(s8) %5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: add_i15 name: add_i15
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i15 ; CHECK-LABEL: name: add_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[ADD]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s15) = G_TRUNC %0(s64) %2:_(s15) = G_TRUNC %0(s64)
%3:_(s15) = G_TRUNC %1(s64) %3:_(s15) = G_TRUNC %1(s64)
%4:_(s15) = G_ADD %2, %3 %4:_(s15) = G_ADD %2, %3
%5:_(s64) = G_ANYEXT %4(s15) %5:_(s64) = G_ANYEXT %4(s15)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: add_i16 name: add_i16
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i16 ; CHECK-LABEL: name: add_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[ADD]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64) %2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64) %3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_ADD %2, %3 %4:_(s16) = G_ADD %2, %3
%5:_(s64) = G_ANYEXT %4(s16) %5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: add_i32 name: add_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: add_i32 ; CHECK-LABEL: name: add_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[ADD]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_ADD %2, %3 %4:_(s32) = G_ADD %2, %3
%5:_(s64) = G_ANYEXT %4(s32) %5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
▲ Show 20 Lines • Show All 119 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir

Show All 22 Lines bb.0.entry:
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: ashr_i15 name: ashr_i15
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: ashr_i1 ; CHECK-LABEL: name: ashr_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 32767
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]]
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 15 ; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 15
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64) ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-NEXT: $x10 = COPY [[ASHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
Show All 32 Lines
... ...
--- ---
name: ashr_i32 name: ashr_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: ashr_i32 ; CHECK-LABEL: name: ashr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[COPY]], 32 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[TRUNC]], [[TRUNC1]](s32)
; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[SEXT_INREG]], [[AND]](s64) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ASHR]](s32)
; CHECK-NEXT: $x10 = COPY [[ASHR]](s64) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_ASHR %2, %3 %4:_(s32) = G_ASHR %2, %3
%5:_(s64) = G_ANYEXT %4(s32) %5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
Show All 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-const.mir

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 ; CHECK: [[C:%[0-9]+]]:_(p0) = G_CONSTANT i64 0
; CHECK-NEXT: $x10 = COPY [[C]](p0) ; CHECK-NEXT: $x10 = COPY [[C]](p0)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(p0) = G_CONSTANT i64 0 %0:_(p0) = G_CONSTANT i64 0
$x10 = COPY %0(p0) $x10 = COPY %0(p0)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
---
name: const_add_i32
body: |
bb.0.entry:
; CHECK-LABEL: name: const_add_i32
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -64769
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[C]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s32) = G_CONSTANT i32 -64769
%1:_(s64) = COPY $x10
%2:_(s32) = G_TRUNC %1(s64)
%3:_(s32) = G_ADD %2, %0
%4:_(s64) = G_ANYEXT %3(s32)
$x10 = COPY %4(s64)
PseudoRET implicit $x10
...
---
name: const_add_i8
body: |
bb.0.entry:
; CHECK-LABEL: name: const_add_i8
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[TRUNC]], [[C]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[ADD]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s8) = G_CONSTANT i8 1
%1:_(s64) = COPY $x10
%2:_(s8) = G_TRUNC %1(s64)
%3:_(s8) = G_ADD %2, %0
%4:_(s64) = G_ANYEXT %3(s8)
$x10 = COPY %4(s64)
PseudoRET implicit $x10
...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines
... ...
--- ---
name: lshr_i32 name: lshr_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: lshr_i32 ; CHECK-LABEL: name: lshr_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[TRUNC1]](s32)
; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[C1]] ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[LSHR]](s32)
; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[AND1]], [[AND]](s64) ; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: $x10 = COPY [[LSHR]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_LSHR %2, %3 %4:_(s32) = G_LSHR %2, %3
%5:_(s64) = G_ANYEXT %4(s32) %5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
Show All 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir

Show First 20 Lines • Show All 68 Lines • ▼ Show 20 Lines
... ...
--- ---
name: shl_i32 name: shl_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: shl_i32 ; CHECK-LABEL: name: shl_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY1]], [[C]] ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[COPY]], [[AND]](s64) ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[TRUNC]], [[TRUNC1]](s32)
; CHECK-NEXT: $x10 = COPY [[SHL]](s64) ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SHL]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_SHL %2, %3 %4:_(s32) = G_SHL %2, %3
%5:_(s64) = G_ANYEXT %4(s32) %5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
Show All 20 Lines

llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \ # RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
# RUN: | FileCheck %s # RUN: | FileCheck %s
--- ---
name: sub_i8 name: sub_i8
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i8 ; CHECK-LABEL: name: sub_i8
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[SUB]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s8) = G_TRUNC %0(s64) %2:_(s8) = G_TRUNC %0(s64)
%3:_(s8) = G_TRUNC %1(s64) %3:_(s8) = G_TRUNC %1(s64)
%4:_(s8) = G_SUB %2, %3 %4:_(s8) = G_SUB %2, %3
%5:_(s64) = G_ANYEXT %4(s8) %5:_(s64) = G_ANYEXT %4(s8)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: sub_i15 name: sub_i15
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i15 ; CHECK-LABEL: name: sub_i15
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[SUB]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s15) = G_TRUNC %0(s64) %2:_(s15) = G_TRUNC %0(s64)
%3:_(s15) = G_TRUNC %1(s64) %3:_(s15) = G_TRUNC %1(s64)
%4:_(s15) = G_SUB %2, %3 %4:_(s15) = G_SUB %2, %3
%5:_(s64) = G_ANYEXT %4(s15) %5:_(s64) = G_ANYEXT %4(s15)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: sub_i16 name: sub_i16
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i16 ; CHECK-LABEL: name: sub_i16
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[SUB]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s16) = G_TRUNC %0(s64) %2:_(s16) = G_TRUNC %0(s64)
%3:_(s16) = G_TRUNC %1(s64) %3:_(s16) = G_TRUNC %1(s64)
%4:_(s16) = G_SUB %2, %3 %4:_(s16) = G_SUB %2, %3
%5:_(s64) = G_ANYEXT %4(s16) %5:_(s64) = G_ANYEXT %4(s16)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: sub_i32 name: sub_i32
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: sub_i32 ; CHECK-LABEL: name: sub_i32
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10 ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]] ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
; CHECK-NEXT: $x10 = COPY [[SUB]](s64) ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[SUB]](s32)
; CHECK-NEXT: $x10 = COPY [[ANYEXT]](s64)
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%0:_(s64) = COPY $x10 %0:_(s64) = COPY $x10
%1:_(s64) = COPY $x11 %1:_(s64) = COPY $x11
%2:_(s32) = G_TRUNC %0(s64) %2:_(s32) = G_TRUNC %0(s64)
%3:_(s32) = G_TRUNC %1(s64) %3:_(s32) = G_TRUNC %1(s64)
%4:_(s32) = G_SUB %2, %3 %4:_(s32) = G_SUB %2, %3
%5:_(s64) = G_ANYEXT %4(s32) %5:_(s64) = G_ANYEXT %4(s32)
$x10 = COPY %5(s64) $x10 = COPY %5(s64)
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