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Differential D157591

[AArch64][GlobalISel] Optimize Combine Funnel Shift
ClosedPublic

Authored by chuongg3 on Aug 10 2023, 2:02 AM.

Details

Reviewers
dmgreen
arsenm
SjoerdMeijer
paquette
aemerson
Pierre-vh
Commits
rGb7a305deca80: [AArch64][GlobalISel] Optimise Combine Funnel Shift
Summary

Optimize combine for funnel shift

Diff Detail

Unit TestsFailed

TimeTest
60,030 msx64 debian > MLIR.Examples/standalone::test.toy

Event Timeline

chuongg3 created this revision.Aug 10 2023, 2:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 2:02 AM
Herald added subscribers: kerbowa, hiraditya, kristof.beyls, jvesely. · View Herald Transcript
chuongg3 requested review of this revision.Aug 10 2023, 2:02 AM
Herald added a project: Restricted Project. · View Herald TranscriptAug 10 2023, 2:02 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
chuongg3 added a parent revision: D155484: [AArch64] Global Isel Funnel Shift Lowering.Aug 10 2023, 2:03 AM
Harbormaster completed remote builds in B251614: Diff 548927.Aug 10 2023, 5:32 AM
dmgreen added a comment.Aug 11 2023, 12:17 AM

Is it possible to add a vector test to the mir tests too?

llvm/include/llvm/Target/GlobalISel/Combine.td
387

I would move these down to next to the other funnel shift combines

843–846

Can you format this to be a shorter line.

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
2623

This comment maybe doesn't add much

2631

It would be good to have a comment here that explains what this is doing.

chuongg3 updated this revision to Diff 549395.Aug 11 2023, 7:54 AM
chuongg3 marked 4 inline comments as done.
chuongg3 updated this revision to Diff 549399.Aug 11 2023, 7:59 AM
Harbormaster completed remote builds in B251964: Diff 549399.Aug 11 2023, 10:28 AM
arsenm added inline comments.Aug 11 2023, 11:04 AM
llvm/include/llvm/Target/GlobalISel/Combine.td
785

Can you try using the new combiner patterns added in 63afb70503bf254bb3cdd8acc6bd1ad25c66e0d8

chuongg3 updated this revision to Diff 549893.Aug 14 2023, 5:47 AM
chuongg3 marked an inline comment as done.

Used new MIR pattern matcher for the combiner

chuongg3 updated this revision to Diff 549894.Aug 14 2023, 5:52 AM
Harbormaster completed remote builds in B252325: Diff 549894.Aug 14 2023, 7:08 AM
dmgreen added a reviewer: Pierre-vh.Aug 15 2023, 12:04 AM
arsenm added inline comments.Aug 15 2023, 4:16 PM
llvm/include/llvm/Target/GlobalISel/Combine.td
799

not sure if ImmLeafs work

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
2614

Don't need to construct an APInt just to do uge

chuongg3 updated this revision to Diff 550741.Aug 16 2023, 7:06 AM
chuongg3 marked 2 inline comments as done.

Removed an unnecessary creation of APInt pointed out by arsenm

Harbormaster completed remote builds in B252945: Diff 550741.Aug 16 2023, 9:03 AM
chuongg3 updated this revision to Diff 551053.Aug 17 2023, 2:16 AM

Moved funnel-shift.ll test update to D155484

Harbormaster completed remote builds in B253160: Diff 551053.Aug 17 2023, 3:46 AM
Pierre-vh added inline comments.Aug 22 2023, 12:39 AM
llvm/include/llvm/Target/GlobalISel/Combine.td
785

In theory this should just be

(match (G_FSHR $x, $y, 0))
(apply (COPY $x, $y))

Same deal below but with G_FSHL

funnel_shift_overshift can stay the same though, there's no way to express that using MIR patterns easily right now.

chuongg3 updated this revision to Diff 552324.Aug 22 2023, 5:37 AM
chuongg3 marked an inline comment as done.
Harbormaster completed remote builds in B254069: Diff 552324.Aug 22 2023, 6:57 AM
chuongg3 added inline comments.Aug 24 2023, 8:10 AM
llvm/include/llvm/Target/GlobalISel/Combine.td
799

It looks like ImmLeaf will currently take a type and use an int64_t for the internal type. These patterns want to handle any types, so it doesn't look like they can be used as-is here.

chuongg3 added a comment.Aug 31 2023, 7:52 AM

Ping

aemerson added a comment.Sep 4 2023, 12:34 AM

Are there existing aarch64 IR tests that you can add a global-isel RUN line to? That way we can also check how the codegen compares to SelectionDAG,

llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir
3

No need for -O0 or abort=1

chuongg3 updated this revision to Diff 555702.Sep 4 2023, 3:49 AM
chuongg3 marked an inline comment as done.
Harbormaster completed remote builds in B256504: Diff 555702.Sep 4 2023, 4:21 AM
aemerson accepted this revision.Sep 4 2023, 6:33 PM
This revision is now accepted and ready to land.Sep 4 2023, 6:33 PM
Closed by commit rGb7a305deca80: [AArch64][GlobalISel] Optimise Combine Funnel Shift (authored by chuongg3). · Explain WhySep 7 2023, 4:11 AM
This revision was automatically updated to reflect the committed changes.
chuongg3 added a commit: rGb7a305deca80: [AArch64][GlobalISel] Optimise Combine Funnel Shift.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
8 lines
Target/
GlobalISel/
29 lines
lib/
CodeGen/
GlobalISel/
41 lines
test/
CodeGen/
AArch64/
GlobalISel/
452 lines
452 lines
587 lines
AMDGPU/
GlobalISel/
28 lines

Diff 549399

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 449 Lines • ▼ Show 20 Linespublic:
void replaceInstWithUndef(MachineInstr &MI); void replaceInstWithUndef(MachineInstr &MI);
/// Delete \p MI and replace all of its uses with its \p OpIdx-th operand. /// Delete \p MI and replace all of its uses with its \p OpIdx-th operand.
void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx); void replaceSingleDefInstWithOperand(MachineInstr &MI, unsigned OpIdx);
/// Delete \p MI and replace all of its uses with \p Replacement. /// Delete \p MI and replace all of its uses with \p Replacement.
void replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement); void replaceSingleDefInstWithReg(MachineInstr &MI, Register Replacement);
/// @brief Replaces the shift amount in \p MI with ShiftAmt % BW
/// @param MI
void applyFunnelShiftConstantModulo(MachineInstr &MI);
/// Return true if \p MOP1 and \p MOP2 are register operands are defined by /// Return true if \p MOP1 and \p MOP2 are register operands are defined by
/// equivalent instructions. /// equivalent instructions.
bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2); bool matchEqualDefs(const MachineOperand &MOP1, const MachineOperand &MOP2);
/// Return true if \p MOP is defined by a G_CONSTANT with a value equal to /// Return true if \p MOP is defined by a G_CONSTANT with a value equal to
/// \p C. /// \p C.
bool matchConstantOp(const MachineOperand &MOP, int64_t C); bool matchConstantOp(const MachineOperand &MOP, int64_t C);
/// @brief Checks if constant at \p ConstIdx is larger than \p MI 's bitwidth
/// @param ConstIdx Index of the constant
bool matchConstantLargerBitWidth(MachineInstr &MI, unsigned ConstIdx);
/// Optimize (cond ? x : x) -> x /// Optimize (cond ? x : x) -> x
bool matchSelectSameVal(MachineInstr &MI); bool matchSelectSameVal(MachineInstr &MI);
/// Optimize (x op x) -> x /// Optimize (x op x) -> x
bool matchBinOpSameVal(MachineInstr &MI); bool matchBinOpSameVal(MachineInstr &MI);
/// Check if operand \p OpIdx is zero. /// Check if operand \p OpIdx is zero.
bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx); bool matchOperandIsZero(MachineInstr &MI, unsigned OpIdx);
▲ Show 20 Lines • Show All 408 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 378 Lines • ▼ Show 20 Linesdef right_identity_zero: GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR, (match (wip_match_opcode G_SUB, G_ADD, G_OR, G_XOR, G_SHL, G_ASHR, G_LSHR,
G_PTR_ADD, G_ROTL, G_ROTR):$root, G_PTR_ADD, G_ROTL, G_ROTR):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]), [{ return Helper.matchConstantOp(${root}->getOperand(2), 0); }]),
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }]) (apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>; >;
// Fold x op 1 -> x // Fold x op 1 -> x
def right_identity_one: GICombineRule< def right_identity_one: GICombineRule<
dmgreenUnsubmitted
Done
ReplyInline Actions

I would move these down to next to the other funnel shift combines

dmgreen: I would move these down to next to the other funnel shift combines
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_MUL):$root, (match (wip_match_opcode G_MUL):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(2), 1); }]), [{ return Helper.matchConstantOp(${root}->getOperand(2), 1); }]),
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }]) (apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>; >;
// Fold (x op x) - > x // Fold (x op x) - > x
def binop_same_val: GICombineRule< def binop_same_val: GICombineRule<
▲ Show 20 Lines • Show All 377 Lines • ▼ Show 20 Lines
def funnel_shift_to_rotate : GICombineRule< def funnel_shift_to_rotate : GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_FSHL, G_FSHR):$root, (match (wip_match_opcode G_FSHL, G_FSHR):$root,
[{ return Helper.matchFunnelShiftToRotate(*${root}); }]), [{ return Helper.matchFunnelShiftToRotate(*${root}); }]),
(apply [{ Helper.applyFunnelShiftToRotate(*${root}); }]) (apply [{ Helper.applyFunnelShiftToRotate(*${root}); }])
>; >;
// Fold fshr x, y, 0 -> y
def funnel_shift_right_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_FSHR):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(3), 0); }]),
arsenmUnsubmitted
Done
ReplyInline Actions

Can you try using the new combiner patterns added in 63afb70503bf254bb3cdd8acc6bd1ad25c66e0d8

arsenm: Can you try using the new combiner patterns added in 63afb70503bf254bb3cdd8acc6bd1ad25c66e0d8
Pierre-vhUnsubmitted
Done
ReplyInline Actions

In theory this should just be

(match (G_FSHR $x, $y, 0))
(apply (COPY $x, $y))

Same deal below but with G_FSHL

funnel_shift_overshift can stay the same though, there's no way to express that using MIR patterns easily right now.

Pierre-vh: In theory this should just be ``` (match (G_FSHR $x, $y, 0)) (apply (COPY $x, $y)) ``` Same…
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 2); }])
>;
// Fold fshl x, y, 0 -> x
def funnel_shift_left_zero: GICombineRule<
(defs root:$root),
(match (wip_match_opcode G_FSHL):$root,
[{ return Helper.matchConstantOp(${root}->getOperand(3), 0); }]),
(apply [{ Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
>;
// Fold fsh(l/r) x, y, C -> fsh(l/r) x, y, C % bw
def funnel_shift_overshift: GICombineRule<
(defs root:$root),
arsenmUnsubmitted
Done
ReplyInline Actions

not sure if ImmLeafs work

arsenm: not sure if ImmLeafs work
chuongg3AuthorUnsubmitted
Done
ReplyInline Actions

It looks like ImmLeaf will currently take a type and use an int64_t for the internal type. These patterns want to handle any types, so it doesn't look like they can be used as-is here.

chuongg3: It looks like ImmLeaf will currently take a type and use an int64_t for the internal type.
(match (wip_match_opcode G_FSHL, G_FSHR):$root,
[{ return Helper.matchConstantLargerBitWidth(*${root}, 3); }]),
(apply [{ Helper.applyFunnelShiftConstantModulo(*${root}); }])
>;
def rotate_out_of_range : GICombineRule< def rotate_out_of_range : GICombineRule<
(defs root:$root), (defs root:$root),
(match (wip_match_opcode G_ROTR, G_ROTL):$root, (match (wip_match_opcode G_ROTR, G_ROTL):$root,
[{ return Helper.matchRotateOutOfRange(*${root}); }]), [{ return Helper.matchRotateOutOfRange(*${root}); }]),
(apply [{ Helper.applyRotateOutOfRange(*${root}); }]) (apply [{ Helper.applyRotateOutOfRange(*${root}); }])
>; >;
def icmp_to_true_false_known_bits : GICombineRule< def icmp_to_true_false_known_bits : GICombineRule<
Show All 22 Lines
def bitfield_extract_from_and : GICombineRule< def bitfield_extract_from_and : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_AND):$root, (match (wip_match_opcode G_AND):$root,
[{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]), [{ return Helper.matchBitfieldExtractFromAnd(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def funnel_shift_combines : GICombineGroup<[funnel_shift_from_or_shift, def funnel_shift_combines : GICombineGroup<[funnel_shift_from_or_shift,
funnel_shift_to_rotate]>; funnel_shift_to_rotate,
funnel_shift_right_zero,
funnel_shift_left_zero,
funnel_shift_overshift]>;
dmgreenUnsubmitted
Done
ReplyInline Actions

Can you format this to be a shorter line.

dmgreen: Can you format this to be a shorter line.
def bitfield_extract_from_sext_inreg : GICombineRule< def bitfield_extract_from_sext_inreg : GICombineRule<
(defs root:$root, build_fn_matchinfo:$info), (defs root:$root, build_fn_matchinfo:$info),
(match (wip_match_opcode G_SEXT_INREG):$root, (match (wip_match_opcode G_SEXT_INREG):$root,
[{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]), [{ return Helper.matchBitfieldExtractFromSExtInReg(*${root}, ${info}); }]),
(apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>; (apply [{ Helper.applyBuildFn(*${root}, ${info}); }])>;
def bitfield_extract_from_shr : GICombineRule< def bitfield_extract_from_shr : GICombineRule<
▲ Show 20 Lines • Show All 318 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 2,593 Lines • ▼ Show 20 Linesvoid CombinerHelper::replaceSingleDefInstWithReg(MachineInstr &MI,
Register Replacement) { Register Replacement) {
assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?"); assert(MI.getNumExplicitDefs() == 1 && "Expected one explicit def?");
Register OldReg = MI.getOperand(0).getReg(); Register OldReg = MI.getOperand(0).getReg();
assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?"); assert(canReplaceReg(OldReg, Replacement, MRI) && "Cannot replace register?");
MI.eraseFromParent(); MI.eraseFromParent();
replaceRegWith(MRI, OldReg, Replacement); replaceRegWith(MRI, OldReg, Replacement);
} }
bool CombinerHelper::matchConstantLargerBitWidth(MachineInstr &MI,
unsigned ConstIdx) {
Register ConstReg = MI.getOperand(ConstIdx).getReg();
LLT ConstTy = MRI.getType(ConstReg);
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
// Get the shift amount
auto VRegAndVal = getIConstantVRegValWithLookThrough(ConstReg, MRI);
if (!VRegAndVal)
return false;
// Return true of shift amount >= Bitwidth
APInt BitWidth(ConstTy.getSizeInBits(), DstTy.getSizeInBits(), false);
arsenmUnsubmitted
Done
ReplyInline Actions

Don't need to construct an APInt just to do uge

arsenm: Don't need to construct an APInt just to do uge
return (VRegAndVal->Value.uge(BitWidth));
}
void CombinerHelper::applyFunnelShiftConstantModulo(MachineInstr &MI) {
assert((MI.getOpcode() == TargetOpcode::G_FSHL ||
MI.getOpcode() == TargetOpcode::G_FSHR) &&
"This is not a funnel shift operation");
Register ConstReg = MI.getOperand(3).getReg();
dmgreenUnsubmitted
Done
ReplyInline Actions

This comment maybe doesn't add much

dmgreen: This comment maybe doesn't add much
LLT ConstTy = MRI.getType(ConstReg);
LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
auto VRegAndVal = getIConstantVRegValWithLookThrough(ConstReg, MRI);
assert((VRegAndVal) && "Value is not a constant");
// Calculate the new Shift Amount = Old Shift Amount % BitWidth
APInt NewConst = VRegAndVal->Value.urem(
dmgreenUnsubmitted
Done
ReplyInline Actions

It would be good to have a comment here that explains what this is doing.

dmgreen: It would be good to have a comment here that explains what this is doing.
APInt(ConstTy.getSizeInBits(), DstTy.getScalarSizeInBits()));
Builder.setInstrAndDebugLoc(MI);
auto NewConstInstr = Builder.buildConstant(ConstTy, NewConst.getZExtValue());
Builder.buildInstr(
MI.getOpcode(), {MI.getOperand(0)},
{MI.getOperand(1), MI.getOperand(2), NewConstInstr.getReg(0)});
MI.eraseFromParent();
}
bool CombinerHelper::matchSelectSameVal(MachineInstr &MI) { bool CombinerHelper::matchSelectSameVal(MachineInstr &MI) {
assert(MI.getOpcode() == TargetOpcode::G_SELECT); assert(MI.getOpcode() == TargetOpcode::G_SELECT);
// Match (cond ? x : x) // Match (cond ? x : x)
return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) && return matchEqualDefs(MI.getOperand(2), MI.getOperand(3)) &&
canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(), canReplaceReg(MI.getOperand(0).getReg(), MI.getOperand(2).getReg(),
MRI); MRI);
} }
▲ Show 20 Lines • Show All 3,420 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/combine-fshl.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=aarch64-prelegalizer-combiner -global-isel-abort=1 %s -o - | FileCheck %s
aemersonUnsubmitted
Done
ReplyInline Actions

No need for -O0 or abort=1

aemerson: No need for -O0 or `abort=1`
---
name: fshl_i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshl_i8
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s8) = G_FSHL [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_FSHL %0, %1, %2(s8)
%7:_(s32) = G_ANYEXT %6(s8)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshl_i16
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s16) = G_FSHL [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_FSHL %0, %1, %2(s16)
%7:_(s32) = G_ANYEXT %6(s16)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshl_i32
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s32) = G_FSHL [[COPY]], [[COPY1]], [[COPY2]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHL]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
%3:_(s32) = G_FSHL %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i64
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: fshl_i64
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s64) = G_FSHL [[COPY]], [[COPY1]], [[COPY2]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHL]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = G_FSHL %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshl_i8_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i8_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 5
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s8) = G_FSHL [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 5
%5:_(s8) = G_FSHL %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i8_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i8_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s8) = G_FSHL [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 10
%5:_(s8) = G_FSHL %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i8_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i8_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 8
%5:_(s8) = G_FSHL %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i16_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i16_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s16) = G_FSHL [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 5
%5:_(s16) = G_FSHL %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i16_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i16_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s16) = G_FSHL [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHL]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 20
%5:_(s16) = G_FSHL %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i16_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i16_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 16
%5:_(s16) = G_FSHL %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i32_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i32_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s32) = G_FSHL [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHL]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 5
%3:_(s32) = G_FSHL %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i32_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i32_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s32) = G_FSHL [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHL]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 42
%3:_(s32) = G_FSHL %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i32_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshl_i32_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 32
%3:_(s32) = G_FSHL %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshl_i64_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshl_i64_const_shift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s64) = G_FSHL [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHL]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 5
%3:_(s64) = G_FSHL %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshl_i64_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshl_i64_const_overshift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[FSHL:%[0-9]+]]:_(s64) = G_FSHL [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHL]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 72
%3:_(s64) = G_FSHL %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshl_i64_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshl_i64_shift_by_bidwidth
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 64
%3:_(s64) = G_FSHL %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...

llvm/test/CodeGen/AArch64/GlobalISel/combine-fshr.mir

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -O0 -mtriple=arm64-unknown-unknown -global-isel -run-pass=aarch64-prelegalizer-combiner -global-isel-abort=1 %s -o - | FileCheck %s
---
name: fshr_i8
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i8
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s8) = G_TRUNC %5(s32)
%6:_(s8) = G_FSHR %0, %1, %2(s8)
%7:_(s32) = G_ANYEXT %6(s8)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i16
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[TRUNC2]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%3:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %3(s32)
%4:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %4(s32)
%5:_(s32) = COPY $w2
%2:_(s16) = G_TRUNC %5(s32)
%6:_(s16) = G_FSHR %0, %1, %2(s16)
%7:_(s32) = G_ANYEXT %6(s16)
$w0 = COPY %7(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1, $w2
; CHECK-LABEL: name: fshr_i32
; CHECK: liveins: $w0, $w1, $w2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = COPY $w2
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i64
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1, $x2
; CHECK-LABEL: name: fshr_i64
; CHECK: liveins: $x0, $x1, $x2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[COPY2]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = COPY $x2
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i8_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 5
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i8_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s8) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s8)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s8)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 10
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i8_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i8_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s8) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s8) = G_TRUNC %3(s32)
%4:_(s8) = G_CONSTANT i8 8
%5:_(s8) = G_FSHR %0, %1, %4(s8)
%6:_(s32) = G_ANYEXT %5(s8)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 5
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s16) = G_FSHR [[TRUNC]], [[TRUNC1]], [[C]](s16)
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FSHR]](s16)
; CHECK-NEXT: $w0 = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 20
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i16_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i16_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%2:_(s32) = COPY $w0
%0:_(s16) = G_TRUNC %2(s32)
%3:_(s32) = COPY $w1
%1:_(s16) = G_TRUNC %3(s32)
%4:_(s16) = G_CONSTANT i16 16
%5:_(s16) = G_FSHR %0, %1, %4(s16)
%6:_(s32) = G_ANYEXT %5(s16)
$w0 = COPY %6(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_const_shift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 5
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_const_overshift
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s32) = G_FSHR [[COPY]], [[COPY1]], [[C]](s32)
; CHECK-NEXT: $w0 = COPY [[FSHR]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 42
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i32_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $w0, $w1
; CHECK-LABEL: name: fshr_i32_shift_by_bidwidth
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
%0:_(s32) = COPY $w0
%1:_(s32) = COPY $w1
%2:_(s32) = G_CONSTANT i32 32
%3:_(s32) = G_FSHR %0, %1, %2(s32)
$w0 = COPY %3(s32)
RET_ReallyLR implicit $w0
...
---
name: fshr_i64_const_shift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_const_shift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 5
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i64_const_overshift
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_const_overshift
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
; CHECK-NEXT: [[FSHR:%[0-9]+]]:_(s64) = G_FSHR [[COPY]], [[COPY1]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[FSHR]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 72
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...
---
name: fshr_i64_shift_by_bidwidth
alignment: 4
tracksRegLiveness: true
body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: fshr_i64_shift_by_bidwidth
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%0:_(s64) = COPY $x0
%1:_(s64) = COPY $x1
%2:_(s64) = G_CONSTANT i64 64
%3:_(s64) = G_FSHR %0, %1, %2(s64)
$x0 = COPY %3(s64)
RET_ReallyLR implicit $x0
...

llvm/test/CodeGen/AArch64/funnel-shift.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s ; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
declare i8 @llvm.fshl.i8(i8, i8, i8) declare i8 @llvm.fshl.i8(i8, i8, i8)
declare i16 @llvm.fshl.i16(i16, i16, i16) declare i16 @llvm.fshl.i16(i16, i16, i16)
declare i32 @llvm.fshl.i32(i32, i32, i32) declare i32 @llvm.fshl.i32(i32, i32, i32)
declare i64 @llvm.fshl.i64(i64, i64, i64) declare i64 @llvm.fshl.i64(i64, i64, i64)
declare i128 @llvm.fshl.i128(i128, i128, i128) declare i128 @llvm.fshl.i128(i128, i128, i128)
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
declare i8 @llvm.fshr.i8(i8, i8, i8) declare i8 @llvm.fshr.i8(i8, i8, i8)
declare i16 @llvm.fshr.i16(i16, i16, i16) declare i16 @llvm.fshr.i16(i16, i16, i16)
declare i32 @llvm.fshr.i32(i32, i32, i32) declare i32 @llvm.fshr.i32(i32, i32, i32)
declare i64 @llvm.fshr.i64(i64, i64, i64) declare i64 @llvm.fshr.i64(i64, i64, i64)
declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
; General case - all operands can be variables. ; General case - all operands can be variables.
define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) { define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshl_i32: ; CHECK-SD-LABEL: fshl_i32:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsr w9, w1, #1 ; CHECK-SD-NEXT: lsr w9, w1, #1
; CHECK-NEXT: lsl w10, w0, w2 ; CHECK-SD-NEXT: lsl w10, w0, w2
; CHECK-NEXT: lsr w8, w9, w8 ; CHECK-SD-NEXT: lsr w8, w9, w8
; CHECK-NEXT: orr w0, w10, w8 ; CHECK-SD-NEXT: orr w0, w10, w8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsr w10, w1, #1
; CHECK-GI-NEXT: lsl w9, w0, w9
; CHECK-GI-NEXT: lsr w8, w10, w8
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z) %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
ret i32 %f ret i32 %f
} }
define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) { define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
; CHECK-LABEL: fshl_i64: ; CHECK-SD-LABEL: fshl_i64:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsr x9, x1, #1 ; CHECK-SD-NEXT: lsr x9, x1, #1
; CHECK-NEXT: lsl x10, x0, x2 ; CHECK-SD-NEXT: lsl x10, x0, x2
; CHECK-NEXT: lsr x8, x9, x8 ; CHECK-SD-NEXT: lsr x8, x9, x8
; CHECK-NEXT: orr x0, x10, x8 ; CHECK-SD-NEXT: orr x0, x10, x8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #63 // =0x3f
; CHECK-GI-NEXT: and x9, x2, #0x3f
; CHECK-GI-NEXT: bic x8, x8, x2
; CHECK-GI-NEXT: lsr x10, x1, #1
; CHECK-GI-NEXT: lsl x9, x0, x9
; CHECK-GI-NEXT: lsr x8, x10, x8
; CHECK-GI-NEXT: orr x0, x9, x8
; CHECK-GI-NEXT: ret
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z) %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)
ret i64 %f ret i64 %f
} }
define i128 @fshl_i128(i128 %x, i128 %y, i128 %z) nounwind { define i128 @fshl_i128(i128 %x, i128 %y, i128 %z) nounwind {
; CHECK-LABEL: fshl_i128: ; CHECK-SD-LABEL: fshl_i128:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: tst x4, #0x40 ; CHECK-SD-NEXT: tst x4, #0x40
; CHECK-NEXT: mvn w8, w4 ; CHECK-SD-NEXT: mvn w8, w4
; CHECK-NEXT: csel x9, x2, x3, ne ; CHECK-SD-NEXT: csel x9, x2, x3, ne
; CHECK-NEXT: csel x10, x3, x0, ne ; CHECK-SD-NEXT: csel x10, x3, x0, ne
; CHECK-NEXT: lsr x9, x9, #1 ; CHECK-SD-NEXT: lsr x9, x9, #1
; CHECK-NEXT: lsl x11, x10, x4 ; CHECK-SD-NEXT: lsl x11, x10, x4
; CHECK-NEXT: csel x12, x0, x1, ne ; CHECK-SD-NEXT: csel x12, x0, x1, ne
; CHECK-NEXT: lsr x10, x10, #1 ; CHECK-SD-NEXT: lsr x10, x10, #1
; CHECK-NEXT: lsr x9, x9, x8 ; CHECK-SD-NEXT: lsr x9, x9, x8
; CHECK-NEXT: lsl x12, x12, x4 ; CHECK-SD-NEXT: lsl x12, x12, x4
; CHECK-NEXT: lsr x8, x10, x8 ; CHECK-SD-NEXT: lsr x8, x10, x8
; CHECK-NEXT: orr x0, x11, x9 ; CHECK-SD-NEXT: orr x0, x11, x9
; CHECK-NEXT: orr x1, x12, x8 ; CHECK-SD-NEXT: orr x1, x12, x8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i128:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #64 // =0x40
; CHECK-GI-NEXT: and x9, x4, #0x7f
; CHECK-GI-NEXT: sub x11, x8, x9
; CHECK-GI-NEXT: sub x13, x9, #64
; CHECK-GI-NEXT: mov w10, #127 // =0x7f
; CHECK-GI-NEXT: cmp x9, #64
; CHECK-GI-NEXT: bic x10, x10, x4
; CHECK-GI-NEXT: lsl x15, x1, x9
; CHECK-GI-NEXT: lsr x11, x0, x11
; CHECK-GI-NEXT: lsl x14, x0, x9
; CHECK-GI-NEXT: orr x11, x11, x15
; CHECK-GI-NEXT: lsl x9, x0, x13
; CHECK-GI-NEXT: sub x8, x8, x10
; CHECK-GI-NEXT: csel x9, x11, x9, lo
; CHECK-GI-NEXT: lsl x11, x3, #63
; CHECK-GI-NEXT: sub x15, x10, #64
; CHECK-GI-NEXT: csel x13, x14, xzr, lo
; CHECK-GI-NEXT: orr x11, x11, x2, lsr #1
; CHECK-GI-NEXT: lsr x14, x3, #1
; CHECK-GI-NEXT: tst x4, #0x7f
; CHECK-GI-NEXT: lsr x16, x11, x10
; CHECK-GI-NEXT: lsl x8, x14, x8
; CHECK-GI-NEXT: mvn x12, x4
; CHECK-GI-NEXT: csel x9, x1, x9, eq
; CHECK-GI-NEXT: lsr x17, x14, x10
; CHECK-GI-NEXT: orr x8, x16, x8
; CHECK-GI-NEXT: lsr x14, x14, x15
; CHECK-GI-NEXT: cmp x10, #64
; CHECK-GI-NEXT: csel x8, x8, x14, lo
; CHECK-GI-NEXT: tst x12, #0x7f
; CHECK-GI-NEXT: csel x8, x11, x8, eq
; CHECK-GI-NEXT: cmp x10, #64
; CHECK-GI-NEXT: csel x10, x17, xzr, lo
; CHECK-GI-NEXT: orr x0, x13, x8
; CHECK-GI-NEXT: orr x1, x9, x10
; CHECK-GI-NEXT: ret
%f = call i128 @llvm.fshl.i128(i128 %x, i128 %y, i128 %z) %f = call i128 @llvm.fshl.i128(i128 %x, i128 %y, i128 %z)
ret i128 %f ret i128 %f
} }
; Verify that weird types are minimally supported. ; Verify that weird types are minimally supported.
declare i37 @llvm.fshl.i37(i37, i37, i37) declare i37 @llvm.fshl.i37(i37, i37, i37)
define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) { define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshl_i37: ; CHECK-SD-LABEL: fshl_i37:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov x9, #46053 ; CHECK-SD-NEXT: mov x9, #46053 // =0xb3e5
; CHECK-NEXT: and x8, x2, #0x1fffffffff ; CHECK-SD-NEXT: and x8, x2, #0x1fffffffff
; CHECK-NEXT: movk x9, #12398, lsl #16 ; CHECK-SD-NEXT: movk x9, #12398, lsl #16
; CHECK-NEXT: ubfiz x10, x1, #26, #37 ; CHECK-SD-NEXT: ubfiz x10, x1, #26, #37
; CHECK-NEXT: movk x9, #15941, lsl #32 ; CHECK-SD-NEXT: movk x9, #15941, lsl #32
; CHECK-NEXT: movk x9, #1771, lsl #48 ; CHECK-SD-NEXT: movk x9, #1771, lsl #48
; CHECK-NEXT: umulh x8, x8, x9 ; CHECK-SD-NEXT: umulh x8, x8, x9
; CHECK-NEXT: mov w9, #37 ; CHECK-SD-NEXT: mov w9, #37 // =0x25
; CHECK-NEXT: msub w8, w8, w9, w2 ; CHECK-SD-NEXT: msub w8, w8, w9, w2
; CHECK-NEXT: mvn w9, w8 ; CHECK-SD-NEXT: mvn w9, w8
; CHECK-NEXT: lsl x8, x0, x8 ; CHECK-SD-NEXT: lsl x8, x0, x8
; CHECK-NEXT: lsr x9, x10, x9 ; CHECK-SD-NEXT: lsr x9, x10, x9
; CHECK-NEXT: orr x0, x8, x9 ; CHECK-SD-NEXT: orr x0, x8, x9
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i37:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #37 // =0x25
; CHECK-GI-NEXT: and x9, x2, #0x1fffffffff
; CHECK-GI-NEXT: udiv x10, x9, x8
; CHECK-GI-NEXT: msub x8, x10, x8, x9
; CHECK-GI-NEXT: mov w9, #36 // =0x24
; CHECK-GI-NEXT: ubfx x10, x1, #1, #36
; CHECK-GI-NEXT: sub x9, x9, x8
; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff
; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff
; CHECK-GI-NEXT: lsl x8, x0, x8
; CHECK-GI-NEXT: lsr x9, x10, x9
; CHECK-GI-NEXT: orr x0, x8, x9
; CHECK-GI-NEXT: ret
%f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z) %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f ret i37 %f
} }
; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011 ; extract(concat(0b1110000, 0b1111111) << 2) = 0b1000011
declare i7 @llvm.fshl.i7(i7, i7, i7) declare i7 @llvm.fshl.i7(i7, i7, i7)
define i7 @fshl_i7_const_fold() { define i7 @fshl_i7_const_fold() {
; CHECK-LABEL: fshl_i7_const_fold: ; CHECK-LABEL: fshl_i7_const_fold:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, #67 ; CHECK-NEXT: mov w0, #67 // =0x43
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2) %f = call i7 @llvm.fshl.i7(i7 112, i7 127, i7 2)
ret i7 %f ret i7 %f
} }
define i8 @fshl_i8_const_fold_overshift_1() { define i8 @fshl_i8_const_fold_overshift_1() {
; CHECK-LABEL: fshl_i8_const_fold_overshift_1: ; CHECK-SD-LABEL: fshl_i8_const_fold_overshift_1:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #128 ; CHECK-SD-NEXT: mov w0, #128 // =0x80
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i8_const_fold_overshift_1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w0, #-128 // =0xffffff80
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15) %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 15)
ret i8 %f ret i8 %f
} }
define i8 @fshl_i8_const_fold_overshift_2() { define i8 @fshl_i8_const_fold_overshift_2() {
; CHECK-LABEL: fshl_i8_const_fold_overshift_2: ; CHECK-SD-LABEL: fshl_i8_const_fold_overshift_2:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #120 ; CHECK-SD-NEXT: mov w0, #120 // =0x78
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i8_const_fold_overshift_2:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #15 // =0xf
; CHECK-GI-NEXT: lsl w0, w8, #3
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11) %f = call i8 @llvm.fshl.i8(i8 15, i8 15, i8 11)
ret i8 %f ret i8 %f
} }
define i8 @fshl_i8_const_fold_overshift_3() { define i8 @fshl_i8_const_fold_overshift_3() {
; CHECK-LABEL: fshl_i8_const_fold_overshift_3: ; CHECK-LABEL: fshl_i8_const_fold_overshift_3:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, wzr ; CHECK-NEXT: mov w0, wzr
Show All 33 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105) %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 105)
ret i64 %f ret i64 %f
} }
; This should work without any node-specific logic. ; This should work without any node-specific logic.
define i8 @fshl_i8_const_fold() { define i8 @fshl_i8_const_fold() {
; CHECK-LABEL: fshl_i8_const_fold: ; CHECK-SD-LABEL: fshl_i8_const_fold:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #128 ; CHECK-SD-NEXT: mov w0, #128 // =0x80
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshl_i8_const_fold:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w0, #-128 // =0xffffff80
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7) %f = call i8 @llvm.fshl.i8(i8 255, i8 0, i8 7)
ret i8 %f ret i8 %f
} }
; Repeat everything for funnel shift right. ; Repeat everything for funnel shift right.
; General case - all operands can be variables. ; General case - all operands can be variables.
define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) { define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
; CHECK-LABEL: fshr_i32: ; CHECK-SD-LABEL: fshr_i32:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsl w9, w0, #1 ; CHECK-SD-NEXT: lsl w9, w0, #1
; CHECK-NEXT: lsr w10, w1, w2 ; CHECK-SD-NEXT: lsr w10, w1, w2
; CHECK-NEXT: lsl w8, w9, w8 ; CHECK-SD-NEXT: lsl w8, w9, w8
; CHECK-NEXT: orr w0, w8, w10 ; CHECK-SD-NEXT: orr w0, w8, w10
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i32:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsl w10, w0, #1
; CHECK-GI-NEXT: lsr w9, w1, w9
; CHECK-GI-NEXT: lsl w8, w10, w8
; CHECK-GI-NEXT: orr w0, w8, w9
; CHECK-GI-NEXT: ret
%f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z) %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
ret i32 %f ret i32 %f
} }
define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) { define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {
; CHECK-LABEL: fshr_i64: ; CHECK-SD-LABEL: fshr_i64:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsl x9, x0, #1 ; CHECK-SD-NEXT: lsl x9, x0, #1
; CHECK-NEXT: lsr x10, x1, x2 ; CHECK-SD-NEXT: lsr x10, x1, x2
; CHECK-NEXT: lsl x8, x9, x8 ; CHECK-SD-NEXT: lsl x8, x9, x8
; CHECK-NEXT: orr x0, x8, x10 ; CHECK-SD-NEXT: orr x0, x8, x10
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i64:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #63 // =0x3f
; CHECK-GI-NEXT: and x9, x2, #0x3f
; CHECK-GI-NEXT: bic x8, x8, x2
; CHECK-GI-NEXT: lsl x10, x0, #1
; CHECK-GI-NEXT: lsr x9, x1, x9
; CHECK-GI-NEXT: lsl x8, x10, x8
; CHECK-GI-NEXT: orr x0, x8, x9
; CHECK-GI-NEXT: ret
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z) %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)
ret i64 %f ret i64 %f
} }
; Verify that weird types are minimally supported. ; Verify that weird types are minimally supported.
declare i37 @llvm.fshr.i37(i37, i37, i37) declare i37 @llvm.fshr.i37(i37, i37, i37)
define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) { define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
; CHECK-LABEL: fshr_i37: ; CHECK-SD-LABEL: fshr_i37:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov x9, #46053 ; CHECK-SD-NEXT: mov x9, #46053 // =0xb3e5
; CHECK-NEXT: and x8, x2, #0x1fffffffff ; CHECK-SD-NEXT: and x8, x2, #0x1fffffffff
; CHECK-NEXT: movk x9, #12398, lsl #16 ; CHECK-SD-NEXT: movk x9, #12398, lsl #16
; CHECK-NEXT: lsl x10, x1, #27 ; CHECK-SD-NEXT: lsl x10, x1, #27
; CHECK-NEXT: movk x9, #15941, lsl #32 ; CHECK-SD-NEXT: movk x9, #15941, lsl #32
; CHECK-NEXT: lsl x11, x0, #1 ; CHECK-SD-NEXT: lsl x11, x0, #1
; CHECK-NEXT: movk x9, #1771, lsl #48 ; CHECK-SD-NEXT: movk x9, #1771, lsl #48
; CHECK-NEXT: umulh x8, x8, x9 ; CHECK-SD-NEXT: umulh x8, x8, x9
; CHECK-NEXT: mov w9, #37 ; CHECK-SD-NEXT: mov w9, #37 // =0x25
; CHECK-NEXT: msub w8, w8, w9, w2 ; CHECK-SD-NEXT: msub w8, w8, w9, w2
; CHECK-NEXT: add w8, w8, #27 ; CHECK-SD-NEXT: add w8, w8, #27
; CHECK-NEXT: mvn w9, w8 ; CHECK-SD-NEXT: mvn w9, w8
; CHECK-NEXT: lsr x8, x10, x8 ; CHECK-SD-NEXT: lsr x8, x10, x8
; CHECK-NEXT: lsl x9, x11, x9 ; CHECK-SD-NEXT: lsl x9, x11, x9
; CHECK-NEXT: orr x0, x9, x8 ; CHECK-SD-NEXT: orr x0, x9, x8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i37:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #37 // =0x25
; CHECK-GI-NEXT: and x9, x2, #0x1fffffffff
; CHECK-GI-NEXT: and x11, x1, #0x1fffffffff
; CHECK-GI-NEXT: udiv x10, x9, x8
; CHECK-GI-NEXT: msub x8, x10, x8, x9
; CHECK-GI-NEXT: mov w9, #36 // =0x24
; CHECK-GI-NEXT: lsl x10, x0, #1
; CHECK-GI-NEXT: sub x9, x9, x8
; CHECK-GI-NEXT: and x8, x8, #0x1fffffffff
; CHECK-GI-NEXT: and x9, x9, #0x1fffffffff
; CHECK-GI-NEXT: lsr x8, x11, x8
; CHECK-GI-NEXT: lsl x9, x10, x9
; CHECK-GI-NEXT: orr x0, x9, x8
; CHECK-GI-NEXT: ret
%f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z) %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)
ret i37 %f ret i37 %f
} }
; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111 ; extract(concat(0b1110000, 0b1111111) >> 2) = 0b0011111
declare i7 @llvm.fshr.i7(i7, i7, i7) declare i7 @llvm.fshr.i7(i7, i7, i7)
define i7 @fshr_i7_const_fold() { define i7 @fshr_i7_const_fold() {
; CHECK-LABEL: fshr_i7_const_fold: ; CHECK-LABEL: fshr_i7_const_fold:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w0, #31 ; CHECK-NEXT: mov w0, #31 // =0x1f
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2) %f = call i7 @llvm.fshr.i7(i7 112, i7 127, i7 2)
ret i7 %f ret i7 %f
} }
define i8 @fshr_i8_const_fold_overshift_1() { define i8 @fshr_i8_const_fold_overshift_1() {
; CHECK-LABEL: fshr_i8_const_fold_overshift_1: ; CHECK-SD-LABEL: fshr_i8_const_fold_overshift_1:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #254 ; CHECK-SD-NEXT: mov w0, #254 // =0xfe
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i8_const_fold_overshift_1:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w0, #-2 // =0xfffffffe
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15) %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 15)
ret i8 %f ret i8 %f
} }
define i8 @fshr_i8_const_fold_overshift_2() { define i8 @fshr_i8_const_fold_overshift_2() {
; CHECK-LABEL: fshr_i8_const_fold_overshift_2: ; CHECK-SD-LABEL: fshr_i8_const_fold_overshift_2:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #225 ; CHECK-SD-NEXT: mov w0, #225 // =0xe1
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i8_const_fold_overshift_2:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #15 // =0xf
; CHECK-GI-NEXT: lsl w9, w8, #5
; CHECK-GI-NEXT: orr w0, w9, w8, lsr #3
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11) %f = call i8 @llvm.fshr.i8(i8 15, i8 15, i8 11)
ret i8 %f ret i8 %f
} }
define i8 @fshr_i8_const_fold_overshift_3() { define i8 @fshr_i8_const_fold_overshift_3() {
; CHECK-LABEL: fshr_i8_const_fold_overshift_3: ; CHECK-SD-LABEL: fshr_i8_const_fold_overshift_3:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #255 ; CHECK-SD-NEXT: mov w0, #255 // =0xff
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i8_const_fold_overshift_3:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w0, #-1 // =0xffffffff
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8) %f = call i8 @llvm.fshr.i8(i8 0, i8 255, i8 8)
ret i8 %f ret i8 %f
} }
; With constant shift amount, this is 'extr'. ; With constant shift amount, this is 'extr'.
define i32 @fshr_i32_const_shift(i32 %x, i32 %y) { define i32 @fshr_i32_const_shift(i32 %x, i32 %y) {
; CHECK-LABEL: fshr_i32_const_shift: ; CHECK-LABEL: fshr_i32_const_shift:
Show All 24 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105) %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 105)
ret i64 %f ret i64 %f
} }
; This should work without any node-specific logic. ; This should work without any node-specific logic.
define i8 @fshr_i8_const_fold() { define i8 @fshr_i8_const_fold() {
; CHECK-LABEL: fshr_i8_const_fold: ; CHECK-SD-LABEL: fshr_i8_const_fold:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w0, #254 ; CHECK-SD-NEXT: mov w0, #254 // =0xfe
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: fshr_i8_const_fold:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w0, #-2 // =0xfffffffe
; CHECK-GI-NEXT: ret
%f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7) %f = call i8 @llvm.fshr.i8(i8 255, i8 0, i8 7)
ret i8 %f ret i8 %f
} }
define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) { define i32 @fshl_i32_shift_by_bitwidth(i32 %x, i32 %y) {
; CHECK-LABEL: fshl_i32_shift_by_bitwidth: ; CHECK-LABEL: fshl_i32_shift_by_bitwidth:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ret ; CHECK-NEXT: ret
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; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>) %f = call <4 x i32> @llvm.fshr.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 32, i32 32, i32 32, i32 32>)
ret <4 x i32> %f ret <4 x i32> %f
} }
define i32 @or_shl_fshl(i32 %x, i32 %y, i32 %s) { define i32 @or_shl_fshl(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_shl_fshl: ; CHECK-SD-LABEL: or_shl_fshl:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w8, w2 ; CHECK-SD-NEXT: mov w8, w2
; CHECK-NEXT: mvn w9, w2 ; CHECK-SD-NEXT: mvn w9, w2
; CHECK-NEXT: lsr w10, w1, #1 ; CHECK-SD-NEXT: lsr w10, w1, #1
; CHECK-NEXT: lsr w9, w10, w9 ; CHECK-SD-NEXT: lsr w9, w10, w9
; CHECK-NEXT: lsl w8, w0, w8 ; CHECK-SD-NEXT: lsl w8, w0, w8
; CHECK-NEXT: lsl w10, w1, w2 ; CHECK-SD-NEXT: lsl w10, w1, w2
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-SD-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w0, w8, w10 ; CHECK-SD-NEXT: orr w0, w8, w10
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_shl_fshl:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsl w10, w1, w2
; CHECK-GI-NEXT: lsr w11, w1, #1
; CHECK-GI-NEXT: lsl w9, w0, w9
; CHECK-GI-NEXT: lsr w8, w11, w8
; CHECK-GI-NEXT: orr w9, w9, w10
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%shy = shl i32 %y, %s %shy = shl i32 %y, %s
%fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s) %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)
%or = or i32 %fun, %shy %or = or i32 %fun, %shy
ret i32 %or ret i32 %or
} }
define i32 @or_shl_rotl(i32 %x, i32 %y, i32 %s) { define i32 @or_shl_rotl(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_shl_rotl: ; CHECK-LABEL: or_shl_rotl:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w2 ; CHECK-NEXT: neg w8, w2
; CHECK-NEXT: lsl w9, w0, w2 ; CHECK-NEXT: lsl w9, w0, w2
; CHECK-NEXT: ror w8, w1, w8 ; CHECK-NEXT: ror w8, w1, w8
; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shx = shl i32 %x, %s %shx = shl i32 %x, %s
%rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s) %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
%or = or i32 %rot, %shx %or = or i32 %rot, %shx
ret i32 %or ret i32 %or
} }
define i32 @or_shl_fshl_commute(i32 %x, i32 %y, i32 %s) { define i32 @or_shl_fshl_commute(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_shl_fshl_commute: ; CHECK-SD-LABEL: or_shl_fshl_commute:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w8, w2 ; CHECK-SD-NEXT: mov w8, w2
; CHECK-NEXT: mvn w9, w2 ; CHECK-SD-NEXT: mvn w9, w2
; CHECK-NEXT: lsr w10, w1, #1 ; CHECK-SD-NEXT: lsr w10, w1, #1
; CHECK-NEXT: lsr w9, w10, w9 ; CHECK-SD-NEXT: lsr w9, w10, w9
; CHECK-NEXT: lsl w8, w0, w8 ; CHECK-SD-NEXT: lsl w8, w0, w8
; CHECK-NEXT: lsl w10, w1, w2 ; CHECK-SD-NEXT: lsl w10, w1, w2
; CHECK-NEXT: orr w8, w8, w9 ; CHECK-SD-NEXT: orr w8, w8, w9
; CHECK-NEXT: orr w0, w10, w8 ; CHECK-SD-NEXT: orr w0, w10, w8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_shl_fshl_commute:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsl w10, w1, w2
; CHECK-GI-NEXT: lsr w11, w1, #1
; CHECK-GI-NEXT: lsl w9, w0, w9
; CHECK-GI-NEXT: lsr w8, w11, w8
; CHECK-GI-NEXT: orr w9, w10, w9
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%shy = shl i32 %y, %s %shy = shl i32 %y, %s
%fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s) %fun = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %s)
%or = or i32 %shy, %fun %or = or i32 %shy, %fun
ret i32 %or ret i32 %or
} }
define i32 @or_shl_rotl_commute(i32 %x, i32 %y, i32 %s) { define i32 @or_shl_rotl_commute(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_shl_rotl_commute: ; CHECK-LABEL: or_shl_rotl_commute:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: neg w8, w2 ; CHECK-NEXT: neg w8, w2
; CHECK-NEXT: lsl w9, w0, w2 ; CHECK-NEXT: lsl w9, w0, w2
; CHECK-NEXT: ror w8, w1, w8 ; CHECK-NEXT: ror w8, w1, w8
; CHECK-NEXT: orr w0, w9, w8 ; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shx = shl i32 %x, %s %shx = shl i32 %x, %s
%rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s) %rot = call i32 @llvm.fshl.i32(i32 %y, i32 %y, i32 %s)
%or = or i32 %shx, %rot %or = or i32 %shx, %rot
ret i32 %or ret i32 %or
} }
define i32 @or_lshr_fshr(i32 %x, i32 %y, i32 %s) { define i32 @or_lshr_fshr(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_lshr_fshr: ; CHECK-SD-LABEL: or_lshr_fshr:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w8, w2 ; CHECK-SD-NEXT: mov w8, w2
; CHECK-NEXT: mvn w9, w2 ; CHECK-SD-NEXT: mvn w9, w2
; CHECK-NEXT: lsl w10, w1, #1 ; CHECK-SD-NEXT: lsl w10, w1, #1
; CHECK-NEXT: lsr w8, w0, w8 ; CHECK-SD-NEXT: lsr w8, w0, w8
; CHECK-NEXT: lsl w9, w10, w9 ; CHECK-SD-NEXT: lsl w9, w10, w9
; CHECK-NEXT: lsr w10, w1, w2 ; CHECK-SD-NEXT: lsr w10, w1, w2
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-SD-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w0, w8, w10 ; CHECK-SD-NEXT: orr w0, w8, w10
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_lshr_fshr:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsr w10, w1, w2
; CHECK-GI-NEXT: lsl w11, w1, #1
; CHECK-GI-NEXT: lsr w9, w0, w9
; CHECK-GI-NEXT: lsl w8, w11, w8
; CHECK-GI-NEXT: orr w9, w9, w10
; CHECK-GI-NEXT: orr w0, w8, w9
; CHECK-GI-NEXT: ret
%shy = lshr i32 %y, %s %shy = lshr i32 %y, %s
%fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s) %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)
%or = or i32 %fun, %shy %or = or i32 %fun, %shy
ret i32 %or ret i32 %or
} }
define i32 @or_lshr_rotr(i32 %x, i32 %y, i32 %s) { define i32 @or_lshr_rotr(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_lshr_rotr: ; CHECK-LABEL: or_lshr_rotr:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, w2 ; CHECK-NEXT: lsr w8, w0, w2
; CHECK-NEXT: ror w9, w1, w2 ; CHECK-NEXT: ror w9, w1, w2
; CHECK-NEXT: orr w0, w9, w8 ; CHECK-NEXT: orr w0, w9, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shx = lshr i32 %x, %s %shx = lshr i32 %x, %s
%rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s) %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
%or = or i32 %rot, %shx %or = or i32 %rot, %shx
ret i32 %or ret i32 %or
} }
define i32 @or_lshr_fshr_commute(i32 %x, i32 %y, i32 %s) { define i32 @or_lshr_fshr_commute(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_lshr_fshr_commute: ; CHECK-SD-LABEL: or_lshr_fshr_commute:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: mov w8, w2 ; CHECK-SD-NEXT: mov w8, w2
; CHECK-NEXT: mvn w9, w2 ; CHECK-SD-NEXT: mvn w9, w2
; CHECK-NEXT: lsl w10, w1, #1 ; CHECK-SD-NEXT: lsl w10, w1, #1
; CHECK-NEXT: lsr w8, w0, w8 ; CHECK-SD-NEXT: lsr w8, w0, w8
; CHECK-NEXT: lsl w9, w10, w9 ; CHECK-SD-NEXT: lsl w9, w10, w9
; CHECK-NEXT: lsr w10, w1, w2 ; CHECK-SD-NEXT: lsr w10, w1, w2
; CHECK-NEXT: orr w8, w9, w8 ; CHECK-SD-NEXT: orr w8, w9, w8
; CHECK-NEXT: orr w0, w10, w8 ; CHECK-SD-NEXT: orr w0, w10, w8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_lshr_fshr_commute:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsr w10, w1, w2
; CHECK-GI-NEXT: lsl w11, w1, #1
; CHECK-GI-NEXT: lsr w9, w0, w9
; CHECK-GI-NEXT: lsl w8, w11, w8
; CHECK-GI-NEXT: orr w9, w10, w9
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%shy = lshr i32 %y, %s %shy = lshr i32 %y, %s
%fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s) %fun = call i32 @llvm.fshr.i32(i32 %y, i32 %x, i32 %s)
%or = or i32 %shy, %fun %or = or i32 %shy, %fun
ret i32 %or ret i32 %or
} }
define i32 @or_lshr_rotr_commute(i32 %x, i32 %y, i32 %s) { define i32 @or_lshr_rotr_commute(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_lshr_rotr_commute: ; CHECK-LABEL: or_lshr_rotr_commute:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: lsr w8, w0, w2 ; CHECK-NEXT: lsr w8, w0, w2
; CHECK-NEXT: ror w9, w1, w2 ; CHECK-NEXT: ror w9, w1, w2
; CHECK-NEXT: orr w0, w8, w9 ; CHECK-NEXT: orr w0, w8, w9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shx = lshr i32 %x, %s %shx = lshr i32 %x, %s
%rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s) %rot = call i32 @llvm.fshr.i32(i32 %y, i32 %y, i32 %s)
%or = or i32 %shx, %rot %or = or i32 %shx, %rot
ret i32 %or ret i32 %or
} }
define i32 @or_shl_fshl_simplify(i32 %x, i32 %y, i32 %s) { define i32 @or_shl_fshl_simplify(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_shl_fshl_simplify: ; CHECK-SD-LABEL: or_shl_fshl_simplify:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsr w9, w0, #1 ; CHECK-SD-NEXT: lsr w9, w0, #1
; CHECK-NEXT: lsl w10, w1, w2 ; CHECK-SD-NEXT: lsl w10, w1, w2
; CHECK-NEXT: lsr w8, w9, w8 ; CHECK-SD-NEXT: lsr w8, w9, w8
; CHECK-NEXT: orr w0, w10, w8 ; CHECK-SD-NEXT: orr w0, w10, w8
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_shl_fshl_simplify:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsl w10, w1, w2
; CHECK-GI-NEXT: lsr w11, w0, #1
; CHECK-GI-NEXT: lsl w9, w1, w9
; CHECK-GI-NEXT: lsr w8, w11, w8
; CHECK-GI-NEXT: orr w9, w9, w10
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%shy = shl i32 %y, %s %shy = shl i32 %y, %s
%fun = call i32 @llvm.fshl.i32(i32 %y, i32 %x, i32 %s) %fun = call i32 @llvm.fshl.i32(i32 %y, i32 %x, i32 %s)
%or = or i32 %fun, %shy %or = or i32 %fun, %shy
ret i32 %or ret i32 %or
} }
define i32 @or_lshr_fshr_simplify(i32 %x, i32 %y, i32 %s) { define i32 @or_lshr_fshr_simplify(i32 %x, i32 %y, i32 %s) {
; CHECK-LABEL: or_lshr_fshr_simplify: ; CHECK-SD-LABEL: or_lshr_fshr_simplify:
; CHECK: // %bb.0: ; CHECK-SD: // %bb.0:
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2 ; CHECK-SD-NEXT: // kill: def $w2 killed $w2 def $x2
; CHECK-NEXT: mvn w8, w2 ; CHECK-SD-NEXT: mvn w8, w2
; CHECK-NEXT: lsl w9, w0, #1 ; CHECK-SD-NEXT: lsl w9, w0, #1
; CHECK-NEXT: lsr w10, w1, w2 ; CHECK-SD-NEXT: lsr w10, w1, w2
; CHECK-NEXT: lsl w8, w9, w8 ; CHECK-SD-NEXT: lsl w8, w9, w8
; CHECK-NEXT: orr w0, w8, w10 ; CHECK-SD-NEXT: orr w0, w8, w10
; CHECK-NEXT: ret ; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_lshr_fshr_simplify:
; CHECK-GI: // %bb.0:
; CHECK-GI-NEXT: mov w8, #31 // =0x1f
; CHECK-GI-NEXT: and w9, w2, #0x1f
; CHECK-GI-NEXT: bic w8, w8, w2
; CHECK-GI-NEXT: lsr w10, w1, w2
; CHECK-GI-NEXT: lsl w11, w0, #1
; CHECK-GI-NEXT: lsr w9, w1, w9
; CHECK-GI-NEXT: lsl w8, w11, w8
; CHECK-GI-NEXT: orr w9, w10, w9
; CHECK-GI-NEXT: orr w0, w9, w8
; CHECK-GI-NEXT: ret
%shy = lshr i32 %y, %s %shy = lshr i32 %y, %s
%fun = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %s) %fun = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %s)
%or = or i32 %shy, %fun %or = or i32 %shy, %fun
ret i32 %or ret i32 %or
} }

llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,784 Lines • ▼ Show 20 Lines; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
ret i32 %result ret i32 %result
} }
define amdgpu_ps i32 @s_fshl_i32_5(i32 inreg %lhs, i32 inreg %rhs) { define amdgpu_ps i32 @s_fshl_i32_5(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_fshl_i32_5: ; GFX6-LABEL: s_fshl_i32_5:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s1
; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, -5 ; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 27
; GFX6-NEXT: v_readfirstlane_b32 s0, v0 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshl_i32_5: ; GFX8-LABEL: s_fshl_i32_5:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, -5 ; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 27
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshl_i32_5: ; GFX9-LABEL: s_fshl_i32_5:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, -5 ; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 27
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshl_i32_5: ; GFX10-LABEL: s_fshl_i32_5:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, -5 ; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 27
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshl_i32_5: ; GFX11-LABEL: s_fshl_i32_5:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, -5 ; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 27
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5)
ret i32 %result ret i32 %result
} }
define amdgpu_ps i32 @s_fshl_i32_8(i32 inreg %lhs, i32 inreg %rhs) { define amdgpu_ps i32 @s_fshl_i32_8(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_fshl_i32_8: ; GFX6-LABEL: s_fshl_i32_8:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v0, s1 ; GFX6-NEXT: v_mov_b32_e32 v0, s1
; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, -8 ; GFX6-NEXT: v_alignbit_b32 v0, s0, v0, 24
; GFX6-NEXT: v_readfirstlane_b32 s0, v0 ; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: ; return to shader part epilog ; GFX6-NEXT: ; return to shader part epilog
; ;
; GFX8-LABEL: s_fshl_i32_8: ; GFX8-LABEL: s_fshl_i32_8:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v0, s1 ; GFX8-NEXT: v_mov_b32_e32 v0, s1
; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, -8 ; GFX8-NEXT: v_alignbit_b32 v0, s0, v0, 24
; GFX8-NEXT: v_readfirstlane_b32 s0, v0 ; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: ; return to shader part epilog ; GFX8-NEXT: ; return to shader part epilog
; ;
; GFX9-LABEL: s_fshl_i32_8: ; GFX9-LABEL: s_fshl_i32_8:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v0, s1 ; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, -8 ; GFX9-NEXT: v_alignbit_b32 v0, s0, v0, 24
; GFX9-NEXT: v_readfirstlane_b32 s0, v0 ; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog ; GFX9-NEXT: ; return to shader part epilog
; ;
; GFX10-LABEL: s_fshl_i32_8: ; GFX10-LABEL: s_fshl_i32_8:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, -8 ; GFX10-NEXT: v_alignbit_b32 v0, s0, s1, 24
; GFX10-NEXT: v_readfirstlane_b32 s0, v0 ; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog ; GFX10-NEXT: ; return to shader part epilog
; ;
; GFX11-LABEL: s_fshl_i32_8: ; GFX11-LABEL: s_fshl_i32_8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, -8 ; GFX11-NEXT: v_alignbit_b32 v0, s0, s1, 24
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-NEXT: ; return to shader part epilog ; GFX11-NEXT: ; return to shader part epilog
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8)
ret i32 %result ret i32 %result
} }
define i32 @v_fshl_i32(i32 %lhs, i32 %rhs, i32 %amt) { define i32 @v_fshl_i32(i32 %lhs, i32 %rhs, i32 %amt) {
Show All 18 Lines; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 %amt)
ret i32 %result ret i32 %result
} }
define i32 @v_fshl_i32_5(i32 %lhs, i32 %rhs) { define i32 @v_fshl_i32_5(i32 %lhs, i32 %rhs) {
; GCN-LABEL: v_fshl_i32_5: ; GCN-LABEL: v_fshl_i32_5:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_alignbit_b32 v0, v0, v1, -5 ; GCN-NEXT: v_alignbit_b32 v0, v0, v1, 27
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_i32_5: ; GFX11-LABEL: v_fshl_i32_5:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, -5 ; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, 27
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 5)
ret i32 %result ret i32 %result
} }
define i32 @v_fshl_i32_8(i32 %lhs, i32 %rhs) { define i32 @v_fshl_i32_8(i32 %lhs, i32 %rhs) {
; GCN-LABEL: v_fshl_i32_8: ; GCN-LABEL: v_fshl_i32_8:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: v_alignbit_b32 v0, v0, v1, -8 ; GCN-NEXT: v_alignbit_b32 v0, v0, v1, 24
; GCN-NEXT: s_setpc_b64 s[30:31] ; GCN-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX11-LABEL: v_fshl_i32_8: ; GFX11-LABEL: v_fshl_i32_8:
; GFX11: ; %bb.0: ; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, -8 ; GFX11-NEXT: v_alignbit_b32 v0, v0, v1, 24
; GFX11-NEXT: s_setpc_b64 s[30:31] ; GFX11-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8) %result = call i32 @llvm.fshl.i32(i32 %lhs, i32 %rhs, i32 8)
ret i32 %result ret i32 %result
} }
define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) { define amdgpu_ps float @v_fshl_i32_ssv(i32 inreg %lhs, i32 inreg %rhs, i32 %amt) {
; GFX6-LABEL: v_fshl_i32_ssv: ; GFX6-LABEL: v_fshl_i32_ssv:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
▲ Show 20 Lines • Show All 5,262 Lines • Show Last 20 Lines