[JITLink][PowerPC] Add relocations included in rtdyld but missing from jitlink

[lkail]

Summary

RuntimeDyld has implemented more relocations than JITLink for ppc64. This patch adds relocations missing from JITLink for ppc64.

[lhames]

LGTM. Thanks very much for adding these @lkail!

llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h

 #include "llvm/Support/Endian.h"
 
 namespace llvm::jitlink::ppc64 {
 
 /// Represents ppc64 fixups and other ppc64-specific edge kinds.
 enum EdgeKind_ppc64 : Edge::Kind {
   Pointer64 = Edge::FirstRelocation,
   Pointer32,
+  Pointer16,
+  Pointer16DS,
+  Pointer16HA,
+  Pointer16HI,
+  Pointer16HIGH,
+  Pointer16HIGHA,
+  Pointer16HIGHER,
+  Pointer16HIGHERA,
+  Pointer16HIGHEST,
+  Pointer16HIGHESTA,
+  Pointer16LO,
+  Pointer16LODS,
+  Pointer14,
   Delta64,
   Delta34,
   Delta32,
   NegDelta32,
   Delta16,
   Delta16HA,
+  Delta16HI,
   Delta16LO,
+  TOC,
+  TOCDelta16,
+  TOCDelta16DS,
   TOCDelta16HA,
+  TOCDelta16HI,
   TOCDelta16LO,
-  TOCDelta16DS,
   TOCDelta16LODS,
   CallBranchDelta,
   // Need to restore r2 after the bl, suggesting the bl is followed by a nop.
   CallBranchDeltaRestoreTOC,
   // Request calling function with TOC.
   RequestCall,
   // Request calling function without TOC.
   RequestCallNoTOC,
private:
   Section *PLTSection = nullptr;
   PLTCallStubKind StubKind;
 };
 
 /// Returns a string name for the given ppc64 edge. For debugging purposes
 /// only.
 const char *getEdgeKindName(Edge::Kind K);
 
-inline static uint16_t ha16(uint64_t x) { return (x + 0x8000) >> 16; }
-
-inline static uint16_t lo16(uint64_t x) { return x & 0xffff; }
+inline static uint16_t ha(uint64_t x) { return (x + 0x8000) >> 16; }
+inline static uint64_t lo(uint64_t x) { return x & 0xffff; }
+inline static uint16_t hi(uint64_t x) { return x >> 16; }
+inline static uint64_t high(uint64_t x) { return (x >> 16) & 0xffff; }
+inline static uint64_t higha(uint64_t x) {
+  return ((x + 0x8000) >> 16) & 0xffff;
+}
+inline static uint64_t higher(uint64_t x) { return (x >> 32) & 0xffff; }
+inline static uint64_t highera(uint64_t x) {
+  return ((x + 0x8000) >> 32) & 0xffff;
+}
+inline static uint16_t highest(uint64_t x) { return x >> 48; }
+inline static uint16_t highesta(uint64_t x) { return (x + 0x8000) >> 48; }
 
 // Prefixed instruction introduced in ISAv3.1 consists of two 32-bit words,
 // prefix word and suffix word, i.e., prefixed_instruction = concat(prefix_word,
 // suffix_word). That's to say, for a prefixed instruction encoded in uint64_t,
 // the most significant 32 bits belong to the prefix word. The prefix word is at
 // low address for both big/little endian. Byte order in each word still follows
 // its endian.
 template <support::endianness Endianness>
 inline static uint64_t readPrefixedInstruction(const char *Loc) {
   constexpr bool isLE = Endianness == support::endianness::little;
   uint64_t Inst = support::endian::read64<Endianness>(Loc);
   return isLE ? (Inst << 32) | (Inst >> 32) : Inst;
 }
 
 template <support::endianness Endianness>
 inline static void writePrefixedInstruction(char *Loc, uint64_t Inst) {
   constexpr bool isLE = Endianness == support::endianness::little;
   Inst = isLE ? (Inst << 32) | (Inst >> 32) : Inst;
   support::endian::write64<Endianness>(Loc, Inst);
 }
 
+template <support::endianness Endianness>
+inline Error relocateHalf16(char *FixupPtr, int64_t Value, Edge::Kind K) {
+  switch (K) {
+  case Delta16:
+  case Pointer16:
+  case TOCDelta16:
+    support::endian::write16<Endianness>(FixupPtr, Value);
+    break;
+  case Pointer16DS:
+  case TOCDelta16DS:
+    support::endian::write16<Endianness>(FixupPtr, Value & ~3);
+    break;
+  case Delta16HA:
+  case Pointer16HA:
+  case TOCDelta16HA:
+    support::endian::write16<Endianness>(FixupPtr, ha(Value));
+    break;
+  case Delta16HI:
+  case Pointer16HI:
+  case TOCDelta16HI:
+    support::endian::write16<Endianness>(FixupPtr, hi(Value));
+    break;
+  case Pointer16HIGH:
+    support::endian::write16<Endianness>(FixupPtr, high(Value));
+    break;
+  case Pointer16HIGHA:
+    support::endian::write16<Endianness>(FixupPtr, higha(Value));
+    break;
+  case Pointer16HIGHER:
+    support::endian::write16<Endianness>(FixupPtr, higher(Value));
+    break;
+  case Pointer16HIGHERA:
+    support::endian::write16<Endianness>(FixupPtr, highera(Value));
+    break;
+  case Pointer16HIGHEST:
+    support::endian::write16<Endianness>(FixupPtr, highest(Value));
+    break;
+  case Pointer16HIGHESTA:
+    support::endian::write16<Endianness>(FixupPtr, highesta(Value));
+    break;
+  case Delta16LO:
+  case Pointer16LO:
+  case TOCDelta16LO:
+    support::endian::write16<Endianness>(FixupPtr, lo(Value));
+    break;
+  case Pointer16LODS:
+  case TOCDelta16LODS:
+    support::endian::write16<Endianness>(FixupPtr, lo(Value) & ~3);
+    break;
+  default:
+    return make_error<JITLinkError>(
+        StringRef(getEdgeKindName(K)) +
+        " relocation does not write at half16 field");
+  }
+  return Error::success();
+}
+
 /// Apply fixup expression for edge to block content.
 template <support::endianness Endianness>
 inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E,
                         const Symbol *TOCSymbol) {
   char *BlockWorkingMem = B.getAlreadyMutableContent().data();
   char *FixupPtr = BlockWorkingMem + E.getOffset();
   orc::ExecutorAddr FixupAddress = B.getAddress() + E.getOffset();
   int64_t S = E.getTarget().getAddress().getValue();
inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E,
   });
 
   switch (K) {
   case Pointer64: {
     uint64_t Value = S + A;
     support::endian::write64<Endianness>(FixupPtr, Value);
     break;
   }
+  case Delta16:
   case Delta16HA:
+  case Delta16HI:
   case Delta16LO: {
     int64_t Value = S + A - P;
     if (LLVM_UNLIKELY(!isInt<32>(Value))) {
       return makeTargetOutOfRangeError(G, B, E);
     }
-    if (K == Delta16LO)
-      support::endian::write16<Endianness>(FixupPtr, lo16(Value));
-    else
-      support::endian::write16<Endianness>(FixupPtr, ha16(Value));
-    break;
+    return relocateHalf16<Endianness>(FixupPtr, Value, K);
   }
-  case TOCDelta16HA:
-  case TOCDelta16LO: {
-    int64_t Value = S + A - TOCBase;
+  case TOC:
+    support::endian::write64<Endianness>(FixupPtr, TOCBase);
+    break;
+  case Pointer16:
+  case Pointer16DS:
+  case Pointer16HA:
+  case Pointer16HI:
+  case Pointer16HIGH:
+  case Pointer16HIGHA:
+  case Pointer16HIGHER:
+  case Pointer16HIGHERA:
+  case Pointer16HIGHEST:
+  case Pointer16HIGHESTA:
+  case Pointer16LO:
+  case Pointer16LODS: {
+    uint64_t Value = S + A;
     if (LLVM_UNLIKELY(!isInt<32>(Value))) {
       return makeTargetOutOfRangeError(G, B, E);
     }
-    if (K == TOCDelta16LO)
-      support::endian::write16<Endianness>(FixupPtr, lo16(Value));
-    else
-      support::endian::write16<Endianness>(FixupPtr, ha16(Value));
+    return relocateHalf16<Endianness>(FixupPtr, Value, K);
+  }
+  case Pointer14: {
+    static const uint32_t Low14Mask = 0xfffc;
+    uint64_t Value = S + A;
+    assert((Value & 3) == 0 && "Pointer14 requires 4-byte alignment");
+    if (LLVM_UNLIKELY(!isInt<16>(Value))) {
+      return makeTargetOutOfRangeError(G, B, E);
+    }
+    uint32_t Inst = support::endian::read32<Endianness>(FixupPtr);
+    support::endian::write32<Endianness>(FixupPtr, (Inst & ~Low14Mask) |
+                                                       (Value & Low14Mask));
     break;
   }
+  case TOCDelta16:
   case TOCDelta16DS:
+  case TOCDelta16HA:
+  case TOCDelta16HI:
+  case TOCDelta16LO:
   case TOCDelta16LODS: {
     int64_t Value = S + A - TOCBase;
     if (LLVM_UNLIKELY(!isInt<32>(Value))) {
       return makeTargetOutOfRangeError(G, B, E);
     }
-    if (K == TOCDelta16LODS)
-      support::endian::write16<Endianness>(FixupPtr, lo16(Value) & ~3);
-    else
-      support::endian::write16<Endianness>(FixupPtr, Value & ~3);
-    break;
+    return relocateHalf16<Endianness>(FixupPtr, Value, K);
   }
   case CallBranchDeltaRestoreTOC:
   case CallBranchDelta: {
     int64_t Value = S + A - P;
     if (LLVM_UNLIKELY(!isInt<26>(Value))) {
       return makeTargetOutOfRangeError(G, B, E);
     }
     uint32_t Inst = support::endian::read32<Endianness>(FixupPtr);

llvm/lib/ExecutionEngine/JITLink/ELF_ppc64.cpp

default:
           "In " + G->getName() + ": Unsupported ppc64 relocation type " +
           object::getELFRelocationTypeName(ELF::EM_PPC64, ELFReloc));
     case ELF::R_PPC64_ADDR64:
       Kind = ppc64::Pointer64;
       break;
     case ELF::R_PPC64_ADDR32:
       Kind = ppc64::Pointer32;
       break;
+    case ELF::R_PPC64_ADDR16:
+      Kind = ppc64::Pointer16;
+      break;
+    case ELF::R_PPC64_ADDR16_DS:
+      Kind = ppc64::Pointer16DS;
+      break;
+    case ELF::R_PPC64_ADDR16_HA:
+      Kind = ppc64::Pointer16HA;
+      break;
+    case ELF::R_PPC64_ADDR16_HI:
+      Kind = ppc64::Pointer16HI;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGH:
+      Kind = ppc64::Pointer16HIGH;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGHA:
+      Kind = ppc64::Pointer16HIGHA;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGHER:
+      Kind = ppc64::Pointer16HIGHER;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGHERA:
+      Kind = ppc64::Pointer16HIGHERA;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGHEST:
+      Kind = ppc64::Pointer16HIGHEST;
+      break;
+    case ELF::R_PPC64_ADDR16_HIGHESTA:
+      Kind = ppc64::Pointer16HIGHESTA;
+      break;
+    case ELF::R_PPC64_ADDR16_LO:
+      Kind = ppc64::Pointer16LO;
+      break;
+    case ELF::R_PPC64_ADDR16_LO_DS:
+      Kind = ppc64::Pointer16LODS;
+      break;
+    case ELF::R_PPC64_ADDR14:
+      Kind = ppc64::Pointer14;
+      break;
+    case ELF::R_PPC64_TOC:
+      Kind = ppc64::TOC;
+      break;
+    case ELF::R_PPC64_TOC16:
+      Kind = ppc64::TOCDelta16;
+      break;
     case ELF::R_PPC64_TOC16_HA:
       Kind = ppc64::TOCDelta16HA;
       break;
+    case ELF::R_PPC64_TOC16_HI:
+      Kind = ppc64::TOCDelta16HI;
+      break;
     case ELF::R_PPC64_TOC16_DS:
       Kind = ppc64::TOCDelta16DS;
       break;
     case ELF::R_PPC64_TOC16_LO:
       Kind = ppc64::TOCDelta16LO;
       break;
     case ELF::R_PPC64_TOC16_LO_DS:
       Kind = ppc64::TOCDelta16LODS;
       break;
     case ELF::R_PPC64_REL16:
       Kind = ppc64::Delta16;
       break;
     case ELF::R_PPC64_REL16_HA:
       Kind = ppc64::Delta16HA;
       break;
+    case ELF::R_PPC64_REL16_HI:
+      Kind = ppc64::Delta16HI;
+      break;
     case ELF::R_PPC64_REL16_LO:
       Kind = ppc64::Delta16LO;
       break;
     case ELF::R_PPC64_REL32:
       Kind = ppc64::Delta32;
       break;
     case ELF::R_PPC64_REL24_NOTOC:
       Kind = ppc64::RequestCallNoTOC;

llvm/lib/ExecutionEngine/JITLink/ppc64.cpp

 };
 
 const char *getEdgeKindName(Edge::Kind K) {
   switch (K) {
   case Pointer64:
     return "Pointer64";
   case Pointer32:
     return "Pointer32";
+  case Pointer16:
+    return "Pointer16";
+  case Pointer16DS:
+    return "Pointer16DS";
+  case Pointer16HA:
+    return "Pointer16HA";
+  case Pointer16HI:
+    return "Pointer16HI";
+  case Pointer16HIGH:
+    return "Pointer16HIGH";
+  case Pointer16HIGHA:
+    return "Pointer16HIGHA";
+  case Pointer16HIGHER:
+    return "Pointer16HIGHER";
+  case Pointer16HIGHERA:
+    return "Pointer16HIGHERA";
+  case Pointer16HIGHEST:
+    return "Pointer16HIGHEST";
+  case Pointer16HIGHESTA:
+    return "Pointer16HIGHESTA";
+  case Pointer16LO:
+    return "Pointer16LO";
+  case Pointer16LODS:
+    return "Pointer16LODS";
+  case Pointer14:
+    return "Pointer14";
   case Delta64:
     return "Delta64";
   case Delta34:
     return "Delta34";
   case Delta32:
     return "Delta32";
   case NegDelta32:
     return "NegDelta32";
   case Delta16:
     return "Delta16";
   case Delta16HA:
     return "Delta16HA";
+  case Delta16HI:
+    return "Delta16HI";
   case Delta16LO:
     return "Delta16LO";
+  case TOC:
+    return "TOC";
+  case TOCDelta16:
+    return "TOCDelta16";
+  case TOCDelta16DS:
+    return "TOCDelta16DS";
   case TOCDelta16HA:
     return "TOCDelta16HA";
+  case TOCDelta16HI:
+    return "TOCDelta16HI";
   case TOCDelta16LO:
     return "TOCDelta16LO";
-  case TOCDelta16DS:
-    return "TOCDelta16DS";
   case TOCDelta16LODS:
     return "TOCDelta16LODS";
   case CallBranchDelta:
     return "CallBranchDelta";
   case CallBranchDeltaRestoreTOC:
     return "CallBranchDeltaRestoreTOC";
   case RequestCall:
     return "RequestCall";

llvm/test/ExecutionEngine/JITLink/ppc64/ppc64-relocs.s

 # RUN: llvm-mc -triple=powerpc64le-unknown-linux-gnu -filetype=obj -o %t %s
 # RUN: llvm-jitlink -abs external_var=0xffff0000 -abs puts=0xffff6400 -abs \
-# RUN:   foo=0xffff8800 -noexec %t
+# RUN:   foo=0xffff8800 -abs low_addr=0x0320 -noexec %t
 # RUN: llvm-mc -triple=powerpc64-unknown-linux-gnu -filetype=obj -o %t %s
 # RUN: llvm-jitlink -abs external_var=0xffff0000 -abs puts=0xffff6400 -abs \
-# RUN:   foo=0xffff8800 -noexec %t
+# RUN:   foo=0xffff8800 -abs low_addr=0x0320 -noexec %t
 #
 # Check typical relocations involving external function call, external variable
 # reference, local function call and referencing global variable defined in the
 # same CU. This test serves as smoke test, `llvm-jitlink -check` is not used.
 
   .text
   .abiversion 2
   .file "ppc64-relocs.c"

 foobar:
 .Lfunc_begin8:
   .localentry foobar, 1
   paddi 3, 0, .L.str@PCREL, 1
   blr
 .Lfunc_end8:
   .size foobar, .Lfunc_end8-.Lfunc_begin8
 
+  .global reloc_addr14
+  .p2align 4
+  .type reloc_addr14,@function
+reloc_addr14:
+.Lfunc_begin9:
+  bca 21, 30, low_addr
+.Lfunc_end9:
+  .size reloc_addr14, .Lfunc_end9-.Lfunc_begin9
+
+  .global reloc_half16
+  .p2align 4
+  .type reloc_half16,@function
+reloc_half16:
+.Lfunc_begin10:
+  li 3, 0
+  .reloc .Lfunc_begin10, R_PPC64_ADDR16_DS, low_addr
+  li 3, 0
+  .reloc .Lfunc_begin10+4, R_PPC64_ADDR16_LO, low_addr
+  li 3, 0
+  .reloc .Lfunc_begin10+8, R_PPC64_ADDR16_LO_DS, low_addr
+  li 3, 0
+  .reloc .Lfunc_begin10+12, R_PPC64_ADDR16, low_addr
+  li 3, 0
+  .reloc .Lfunc_begin10+16, R_PPC64_ADDR16_HI, low_addr
+  li 3, low_addr@ha
+  li 3, low_addr@high
+  li 3, low_addr@higha
+  li 3, low_addr@higher
+  li 3, low_addr@highera
+  li 3, low_addr@highest
+  li 3, low_addr@highesta
+.Ldelta16:
+  li 3, 0
+  .reloc .Ldelta16, R_PPC64_REL16, reloc_half16
+  li 3, 0
+  .reloc .Ldelta16+4, R_PPC64_REL16_HI, reloc_half16
+  li 3, 0
+  .reloc .Ldelta16+8, R_PPC64_REL16_HA, reloc_half16
+  li 3, 0
+  .reloc .Ldelta16+12, R_PPC64_REL16_LO, reloc_half16
+.Ltocdetal16:
+  li 3, 0
+  .reloc .Ltocdetal16, R_PPC64_TOC16, .L.str
+  li 3, 0
+  .reloc .Ltocdetal16+4, R_PPC64_TOC16_HI, .L.str
+  li 3, 0
+  .reloc .Ltocdetal16+8, R_PPC64_TOC16_DS, .L.str
+  li 3, 0
+  .reloc .Ltocdetal16+12, R_PPC64_TOC16_HA, .L.str
+  li 3, 0
+  .reloc .Ltocdetal16+16, R_PPC64_TOC16_LO, .L.str
+  li 3, 0
+  .reloc .Ltocdetal16+20, R_PPC64_TOC16_LO_DS, .L.str
+  blr
+.Lfunc_end10:
+  .size reloc_half16, .Lfunc_end10-.Lfunc_begin10
+
   .type local_var,@object
   .section  .bss,"aw",@nobits
   .globl  local_var
   .p2align  2, 0x0
 local_var:
   .long 0
   .size local_var, 4