[RISCV] Handle subregs when folding vmerge into vops

[luke]

Summary

A vmerge/vmv.v.v can sometimes be inserting a smaller vector into a larger one,
in which case the underlying vop is obscured underneath COPY_TO_REGCLASS and
INSERT_SUBREG nodes:

t22: nxv4i32 = PseudoVMV_V_V_M2 t42, t38, ...
t38: nxv4i32 = INSERT_SUBREG IMPLICIT_DEF:nxv4i32, t40, TargetConstant:i32<4>

t40: v2i32 = COPY_TO_REGCLASS t41, TargetConstant:i64<22>
  t41: nxv1i32,ch = PseudoVLE32_V_MF2 ...

This patch extends the fold peephole to handles this case by peeling off these
extra nodes, and then adding back the necessary insert_subreg/extract_subregs:

t48: nxv4i32 = INSERT_SUBREG t42, t47, TargetConstant:i32<4>
t47: nxv1i32,ch = PseudoVLE32_V_MF2_MASK t46, ...

t46: nxv1i32 = EXTRACT_SUBREG t42, TargetConstant:i32<4>

The subregister being inserted into needs to be the bottom subregister, i.e.
index 0.

[reames]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3354

I'm looking at this, and am trying to understand why we get the COPY_TO_REGCLASS here. If I'm reading this right, we should be generating this only when doing a insert_subreg between two equally LMUL-sized register groups. Given that, I think we must have had two insert_subregs originally, and shouldn't one of have been combined away?

[luke]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3354

IIUC we generate COPY_TO_REGCLASSes when doing either an or insert_subvector extract_subvector between two equally LMUL-sized register groups.
The input graph before isel seems to have both an insert_subvector and extract_subvector, is that the bit that you're saying should be combined?

t0: ch,glue = EntryToken
    t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
          t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
          t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
          t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
        t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
      t25: v4i32 = extract_subvector t24, Constant:i64<0>
    t26: nxv4i32 = insert_subvector undef:nxv4i32, t25, Constant:i64<0>
    t28: nxv4i1 = RISCVISD::VMSET_VL Constant:i64<8>
  t30: nxv4i32 = RISCVISD::VSLIDEUP_VL t2, t26, Constant:i64<4>, t28, Constant:i64<8>, TargetConstant:i64<1>
t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
t19: ch = RISCVISD::RET_GLUE t18, Register:nxv4i32 $v8m2, t18:1

The insert_subvector gets selected as an INSERT_SUBREG:

t0: ch,glue = EntryToken
    t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
          t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
          t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
          t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
        t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
      t25: v4i32 = extract_subvector t24, Constant:i64<0>
    t36: nxv4i32 = INSERT_SUBREG undef:nxv4i32, t25, TargetConstant:i32<4>
  t30: nxv4i32 = PseudoVSLIDEUP_VI_M2 t2, t36, TargetConstant:i64<4>, TargetConstant:i64<8>, TargetConstant:i64<5>, TargetConstant:i64<1>
t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
t37: i64 = TargetConstant<20>
t19: ch = PseudoRET Register:nxv4i32 $v8m2, t18, t18:1

And then the extract_subvector gets selected as a COPY_TO_REGCLASS

t0: ch,glue = EntryToken
    t2: nxv4i32,ch = CopyFromReg t0, Register:nxv4i32 %0
          t6: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %1
          t9: nxv2i32,ch = CopyFromReg t0, Register:nxv2i32 %2
          t23: nxv2i1 = RISCVISD::VMSET_VL Constant:i64<4>
        t24: nxv2i32 = RISCVISD::ADD_VL t6, t9, undef:nxv2i32, t23, Constant:i64<4>
      t38: v4i32 = COPY_TO_REGCLASS t24, TargetConstant:i64<20>
    t36: nxv4i32 = INSERT_SUBREG undef:nxv4i32, t38, TargetConstant:i32<4>
  t30: nxv4i32 = PseudoVSLIDEUP_VI_M2 t2, t36, TargetConstant:i64<4>, TargetConstant:i64<8>, TargetConstant:i64<5>, TargetConstant:i64<1>
t18: ch,glue = CopyToReg t0, Register:nxv4i32 $v8m2, t30
t19: ch = PseudoRET Register:nxv4i32 $v8m2, t18, t18:1

[luke]

Remove extraneous dumpr and rebase

[reames]

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

3354

https://reviews.llvm.org/D158201 should improve this. Not sure it entirely resolves the need for the COPY_TO_REGCLASS, but it at least picks up the redundant pair.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
   // We require that either merge and false are the same, or that merge
   // is undefined.
   if (Merge != False && !isImplicitDef(Merge))
     return false;
 
   assert(True.getResNo() == 0 &&
          "Expect True is the first output of an instruction.");
 
+  // True and False may not be the same vector type because of bitcasts, but
+  // they should always be the same size.
+  assert(True.getSimpleValueType().getSizeInBits() ==
+         False.getSimpleValueType().getSizeInBits());
+
+  // We want to be able to handle vmerges and vmv.v.vs where True is a subreg,
+  // e.g:
+  //
+  // t22: nxv4i32 = PseudoVMV_V_V_M2 t42, t38, ...
+  // t38: nxv4i32 = INSERT_SUBREG IMPLICIT_DEF:nxv4i32, t40,
+  // TargetConstant:i32<4>
+  //   t40: v2i32 = COPY_TO_REGCLASS t41, TargetConstant:i64<22>
+  //     t41: nxv1i32,ch = PseudoVLE32_V_MF2 ...
+  //
+  // If we're inserting into the bottom subregister of an implicit_def, then we
+  // can unwrap True (t38) down to the underlying operation, in this case
+  // PseudoVLE32. We just need to make sure to match up the types in False and
+  // Result, and then we end up with something like this:
+  //
+  // t48: nxv4i32 = INSERT_SUBREG t42, t47, TargetConstant:i32<4>
+  // t47: nxv1i32,ch = PseudoVLE32_V_MF2_MASK t46, ...
+  //   t46: nxv1i32 = EXTRACT_SUBREG t42, TargetConstant:i32<4>
+  std::optional<unsigned> SubRegIdx;
+
+  auto UnwrapSubReg = [this, &SubRegIdx](SDValue V) {
+    if (!V->isMachineOpcode())
+      return SDValue();
+    if (V->getMachineOpcode() == TargetOpcode::COPY_TO_REGCLASS)
+      return V->getOperand(0);
+    // If we're inserting into the bottom subreg of a vector register, unwrap
+    // it.
+    if (V->getMachineOpcode() == TargetOpcode::INSERT_SUBREG &&
+        isImplicitDef(V->getOperand(0))) {
+      MVT SubVecVT = V->getOperand(1).getSimpleValueType();
+      if (SubVecVT.isFixedLengthVector())
+        SubVecVT =
+            Subtarget->getTargetLowering()->getContainerForFixedLengthVector(
+                SubVecVT);
+      unsigned LeftoverIdx;
+      std::tie(SubRegIdx, LeftoverIdx) =
+          RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(
+              V->getSimpleValueType(0), SubVecVT, 0,
+              Subtarget->getRegisterInfo());
+      if (SubRegIdx == V->getConstantOperandVal(2) && LeftoverIdx == 0)
+        return V->getOperand(1);
+    }
+    return SDValue();
+  };
+
+  while (SDValue SubRegTrue = UnwrapSubReg(True)) {
+    if (True->use_empty() || !True->use_begin()->isOnlyUserOf(True.getNode()))
+      return false;
+    True = SubRegTrue;
+  }
+
   // Need N is the exactly one using True.
   if (!True.hasOneUse())
     return false;
 
   if (!True.isMachineOpcode())
     return false;
 
   unsigned TrueOpc = True.getMachineOpcode();
assert(MaskedMCID.getOperandConstraint(MaskedMCID.getNumDefs(),
                                          MCOI::TIED_TO) == 0 &&
          "Expected instructions with mask have a tied dest.");
 #endif
 
   uint64_t Policy = isImplicitDef(Merge) ? RISCVII::TAIL_AGNOSTIC : /*TUMU*/ 0;
   SDValue PolicyOp =
     CurDAG->getTargetConstant(Policy, DL, Subtarget->getXLenVT());
 
-
   SmallVector<SDValue, 8> Ops;
+  // If True is operating on a subreg, then we need to extract out a subreg of
+  // False so the types match.
+  if (SubRegIdx)
+    Ops.push_back(CurDAG->getTargetExtractSubreg(
+        *SubRegIdx, DL, True->getSimpleValueType(0), False));
+  else
     Ops.push_back(False);
 
   const bool HasRoundingMode = RISCVII::hasRoundModeOp(TrueTSFlags);
   const unsigned NormalOpsEnd = TrueVLIndex - IsMasked - HasRoundingMode;
   assert(!IsMasked || NormalOpsEnd == Info->MaskOpIdx);
   Ops.append(True->op_begin() + HasTiedDest, True->op_begin() + NormalOpsEnd);
 
   Ops.push_back(Mask);
 
#endif
   MachineSDNode *Result =
       CurDAG->getMachineNode(MaskedOpc, DL, True->getVTList(), Ops);
   Result->setFlags(True->getFlags());
 
   if (!cast<MachineSDNode>(True)->memoperands_empty())
     CurDAG->setNodeMemRefs(Result, cast<MachineSDNode>(True)->memoperands());
 
   // Replace vmerge.vvm node by Result.
+  if (SubRegIdx) {
+    // If True was operating on a subreg, then we need to insert the subreg back
+    // into the full size False.
+    MVT MergeVT = N->getSimpleValueType(0);
+    SDValue Insert = CurDAG->getTargetInsertSubreg(*SubRegIdx, DL, MergeVT,
+                                                   False, SDValue(Result, 0));
+    Insert->dumpr(CurDAG);
+    ReplaceUses(SDValue(N, 0), Insert);
+  } else {
     ReplaceUses(SDValue(N, 0), SDValue(Result, 0));
+  }
 
   // Replace another value of True. E.g. chain and VL.
   for (unsigned Idx = 1; Idx < True->getNumValues(); ++Idx)
     ReplaceUses(True.getValue(Idx), SDValue(Result, Idx));
 
   // Try to transform Result to unmasked intrinsic.
   doPeepholeMaskedRVV(Result);
   return true;

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll

; CHECK-NEXT:    ret
   %v3 = call <4 x i32> @llvm.vp.add.v4i32(<4 x i32> %v2, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, <4 x i1> %mask, i32 4)
   %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v4
 }
 
 define <4 x i32> @insert_subvector_load_v4i32_v2i32(<4 x i32> %v1, ptr %p) {
 ; CHECK-LABEL: insert_subvector_load_v4i32_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vle32.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %v2 = load <2 x i32>, ptr %p
   %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
   %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v4
 }
 
 declare <2 x i32> @llvm.vp.load.v2i32(ptr, <2 x i1>, i32)
 define <4 x i32> @insert_subvector_vp_load_v4i32_v2i32(<4 x i32> %v1, ptr %p, <2 x i1> %mask) {
 ; CHECK-LABEL: insert_subvector_vp_load_v4i32_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vle32.v v9, (a0), v0.t
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, mu
+; CHECK-NEXT:    vle32.v v8, (a0), v0.t
 ; CHECK-NEXT:    ret
   %v2 = call <2 x i32> @llvm.vp.load.v2i32(ptr %p, <2 x i1> %mask, i32 2)
   %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
   %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v4
 }
 
 define <4 x i32> @insert_subvector_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2) {
 ; CHECK-LABEL: insert_subvector_add_v4i32_v2i32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
 ; CHECK-NEXT:    vid.v v10
-; CHECK-NEXT:    vadd.vv v9, v9, v10
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetvli zero, zero, e32, mf2, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %v3 = add <2 x i32> %v2, <i32 0, i32 1>
   %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
   %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v5
 }
 
 declare <2 x i32> @llvm.vp.add.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
 define <4 x i32> @insert_subvector_vp_add_v4i32_v2i32(<4 x i32> %v1, <2 x i32> %v2, <2 x i1> %mask) {
 ; CHECK-LABEL: insert_subvector_vp_add_v4i32_v2i32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vadd.vi v9, v9, 1, v0.t
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, mu
+; CHECK-NEXT:    vadd.vi v8, v9, 1, v0.t
 ; CHECK-NEXT:    ret
   %v3 = call <2 x i32> @llvm.vp.add.v2i32(<2 x i32> %v2, <2 x i32> <i32 1, i32 1>, <2 x i1> %mask, i32 2)
   %v4 = shufflevector <2 x i32> %v3, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
   %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v5
 }
 
 define <4 x i32> @insert_subvector_load_v4i32_v8i32(<4 x i32> %v1, ptr %p) {
; CHECK-NEXT:    ret
   %v4 = shufflevector <8 x i32> %v3, <8 x i32> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
   %v5 = shufflevector <4 x i32> %v4, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v5
 }
 
 define <4 x i8> @insert_subvector_add_mf8(<4 x i8> %v1, <2 x i8> %a, <2 x i8> %b) {
 ; CHECK-LABEL: insert_subvector_add_mf8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, ta, ma
-; CHECK-NEXT:    vadd.vv v9, v9, v10
-; CHECK-NEXT:    vsetivli zero, 2, e8, mf4, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e8, mf8, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %v2 = add <2 x i8> %a, %b
   %v3 = shufflevector <2 x i8> %v2, <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %v4 = shufflevector <4 x i8> %v3, <4 x i8> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i8> %v4
 }
 
 define <4 x i16> @insert_subvector_add_mf4(<4 x i16> %v1, <2 x i16> %a, <2 x i16> %b) {
 ; CHECK-LABEL: insert_subvector_add_mf4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT:    vadd.vv v9, v9, v10
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %v2 = add <2 x i16> %a, %b
   %v3 = shufflevector <2 x i16> %v2, <2 x i16> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %v4 = shufflevector <4 x i16> %v3, <4 x i16> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i16> %v4
 }
 
 define <4 x i32> @insert_subvector_add_mf2(<4 x i32> %v1, <2 x i32> %a, <2 x i32> %b) {
 ; CHECK-LABEL: insert_subvector_add_mf2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vadd.vv v9, v9, v10
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v9, v10
 ; CHECK-NEXT:    ret
   %v2 = add <2 x i32> %a, %b
   %v3 = shufflevector <2 x i32> %v2, <2 x i32> poison, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
   %v4 = shufflevector <4 x i32> %v3, <4 x i32> %v1, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
   ret <4 x i32> %v4
 }
 
 define <8 x i32> @insert_subvector_add_m1(<8 x i32> %v1, <4 x i32> %a, <4 x i32> %b) {
 ; CHECK-LABEL: insert_subvector_add_m1:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vadd.vv v10, v10, v11
-; CHECK-NEXT:    vsetivli zero, 4, e32, m2, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v10
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v10, v11
 ; CHECK-NEXT:    ret
   %v2 = add <4 x i32> %a, %b
   %v3 = shufflevector <4 x i32> %v2, <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef>
   %v4 = shufflevector <8 x i32> %v3, <8 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 12, i32 13, i32 14, i32 15>
   ret <8 x i32> %v4
 }
 
 define <16 x i32> @insert_subvector_add_m2(<16 x i32> %v1, <8 x i32> %a, <8 x i32> %b) {
 ; CHECK-LABEL: insert_subvector_add_m2:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; CHECK-NEXT:    vadd.vv v12, v12, v14
-; CHECK-NEXT:    vsetivli zero, 8, e32, m4, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    vsetivli zero, 8, e32, m2, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v12, v14
 ; CHECK-NEXT:    ret
   %v2 = add <8 x i32> %a, %b
   %v3 = shufflevector <8 x i32> %v2, <8 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %v4 = shufflevector <16 x i32> %v3, <16 x i32> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
   ret <16 x i32> %v4
 }
 
 define <32 x i32> @insert_subvector_add_m4(<32 x i32> %v1, <16 x i32> %a, <16 x i32> %b) {
 ; CHECK-LABEL: insert_subvector_add_m4:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 16, e32, m4, ta, ma
-; CHECK-NEXT:    vadd.vv v16, v16, v20
-; CHECK-NEXT:    vsetivli zero, 16, e32, m8, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v16
+; CHECK-NEXT:    vsetivli zero, 16, e32, m4, tu, ma
+; CHECK-NEXT:    vadd.vv v8, v16, v20
 ; CHECK-NEXT:    ret
   %v2 = add <16 x i32> %a, %b
   %v3 = shufflevector <16 x i32> %v2, <16 x i32> poison, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %v4 = shufflevector <32 x i32> %v3, <32 x i32> %v1, <32 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 48, i32 49, i32 50, i32 51, i32 52, i32 53, i32 54, i32 55, i32 56, i32 57, i32 58, i32 59, i32 60, i32 61, i32 62, i32 63>
   ret <32 x i32> %v4
 }
 
 ; %v2 depends on the chain of %v1, so make sure the peephole optimisation

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
 
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX2
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32,LMULMAX1
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=2 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX2
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+v --riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 -early-live-intervals -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64,LMULMAX1
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_0(<vscale x 8 x i32> %vec, ptr %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vle32.v v12, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e32, m4, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v12
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; CHECK-NEXT:    vle32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, ptr %svp
   %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 0)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_v2i32_2(<vscale x 8 x i32> %vec, ptr %svp) {
 ; CHECK-LABEL: insert_nxv8i32_v2i32_2:
; CHECK-NEXT:    ret
   %sv = load <2 x i32>, ptr %svp
   %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> %vec, <2 x i32> %sv, i64 6)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_v8i32_0(<vscale x 8 x i32> %vec, ptr %svp) {
 ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_0:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vle32.v v12, (a0)
-; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m4, tu, ma
-; LMULMAX2-NEXT:    vmv.v.v v8, v12
+; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, tu, ma
+; LMULMAX2-NEXT:    vle32.v v8, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_nxv8i32_v8i32_0:
 ; LMULMAX1:       # %bb.0:
+; LMULMAX1-NEXT:    addi a1, a0, 16
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1-NEXT:    vle32.v v12, (a0)
-; LMULMAX1-NEXT:    addi a0, a0, 16
-; LMULMAX1-NEXT:    vle32.v v16, (a0)
-; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m4, tu, ma
-; LMULMAX1-NEXT:    vmv.v.v v8, v12
+; LMULMAX1-NEXT:    vle32.v v12, (a1)
+; LMULMAX1-NEXT:    vsetvli zero, zero, e32, m1, tu, ma
+; LMULMAX1-NEXT:    vle32.v v8, (a0)
 ; LMULMAX1-NEXT:    vsetivli zero, 8, e32, m4, tu, ma
-; LMULMAX1-NEXT:    vslideup.vi v8, v16, 4
+; LMULMAX1-NEXT:    vslideup.vi v8, v12, 4
 ; LMULMAX1-NEXT:    ret
   %sv = load <8 x i32>, ptr %svp
   %v = call <vscale x 8 x i32> @llvm.vector.insert.v8i32.nxv8i32(<vscale x 8 x i32> %vec, <8 x i32> %sv, i64 0)
   ret <vscale x 8 x i32> %v
 }
 
 define <vscale x 8 x i32> @insert_nxv8i32_v8i32_8(<vscale x 8 x i32> %vec, ptr %svp) {
 ; LMULMAX2-LABEL: insert_nxv8i32_v8i32_8:
; CHECK-NEXT:    ret
   %sv = load <2 x i32>, ptr %svp
   %v = call <vscale x 8 x i32> @llvm.vector.insert.v2i32.nxv8i32(<vscale x 8 x i32> undef, <2 x i32> %sv, i64 0)
   ret <vscale x 8 x i32> %v
 }
 
 define void @insert_v4i32_v2i32_0(ptr %vp, ptr %svp) {
 ; CHECK-LABEL: insert_v4i32_v2i32_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; CHECK-NEXT:    vle32.v v8, (a1)
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vle32.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT:    vmv.v.v v9, v8
+; CHECK-NEXT:    vle32.v v8, (a0)
+; CHECK-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; CHECK-NEXT:    vle32.v v8, (a1)
 ; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; CHECK-NEXT:    vse32.v v9, (a0)
+; CHECK-NEXT:    vse32.v v8, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i32>, ptr %svp
   %vec = load <4 x i32>, ptr %vp
   %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> %vec, <2 x i32> %sv, i64 0)
   store <4 x i32> %v, ptr %vp
   ret void
 }
 
; CHECK-NEXT:    ret
   %v = call <4 x i32> @llvm.vector.insert.v2i32.v4i32(<4 x i32> undef, <2 x i32> %sv, i64 0)
   store <4 x i32> %v, ptr %vp
   ret void
 }
 
 define void @insert_v8i32_v2i32_0(ptr %vp, ptr %svp) {
 ; LMULMAX2-LABEL: insert_v8i32_v2i32_0:
 ; LMULMAX2:       # %bb.0:
-; LMULMAX2-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX2-NEXT:    vle32.v v8, (a1)
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vle32.v v10, (a0)
-; LMULMAX2-NEXT:    vsetivli zero, 2, e32, m2, tu, ma
-; LMULMAX2-NEXT:    vmv.v.v v10, v8
+; LMULMAX2-NEXT:    vle32.v v8, (a0)
+; LMULMAX2-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; LMULMAX2-NEXT:    vle32.v v8, (a1)
 ; LMULMAX2-NEXT:    vsetivli zero, 8, e32, m2, ta, ma
-; LMULMAX2-NEXT:    vse32.v v10, (a0)
+; LMULMAX2-NEXT:    vse32.v v8, (a0)
 ; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-LABEL: insert_v8i32_v2i32_0:
 ; LMULMAX1:       # %bb.0:
-; LMULMAX1-NEXT:    vsetivli zero, 2, e32, mf2, ta, ma
-; LMULMAX1-NEXT:    vle32.v v8, (a1)
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1-NEXT:    vle32.v v9, (a0)
-; LMULMAX1-NEXT:    vsetivli zero, 2, e32, m1, tu, ma
-; LMULMAX1-NEXT:    vmv.v.v v9, v8
+; LMULMAX1-NEXT:    vle32.v v8, (a0)
+; LMULMAX1-NEXT:    vsetivli zero, 2, e32, mf2, tu, ma
+; LMULMAX1-NEXT:    vle32.v v8, (a1)
 ; LMULMAX1-NEXT:    vsetivli zero, 4, e32, m1, ta, ma
-; LMULMAX1-NEXT:    vse32.v v9, (a0)
+; LMULMAX1-NEXT:    vse32.v v8, (a0)
 ; LMULMAX1-NEXT:    ret
   %sv = load <2 x i32>, ptr %svp
   %vec = load <8 x i32>, ptr %vp
   %v = call <8 x i32> @llvm.vector.insert.v2i32.v8i32(<8 x i32> %vec, <2 x i32> %sv, i64 0)
   store <8 x i32> %v, ptr %vp
   ret void
 }
 
; LMULMAX1-NEXT:    ret
   ret void
 }
 
 define void @insert_v4i16_v2i16_0(ptr %vp, ptr %svp) {
 ; CHECK-LABEL: insert_v4i16_v2i16_0:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; CHECK-NEXT:    vle16.v v8, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT:    vle16.v v9, (a1)
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, tu, ma
+; CHECK-NEXT:    vle16.v v8, (a1)
 ; CHECK-NEXT:    vsetivli zero, 4, e16, mf2, ta, ma
 ; CHECK-NEXT:    vse16.v v8, (a0)
 ; CHECK-NEXT:    ret
   %v = load <4 x i16>, ptr %vp
   %sv = load <2 x i16>, ptr %svp
   %c = call <4 x i16> @llvm.vector.insert.v2i16.v4i16(<4 x i16> %v, <2 x i16> %sv, i64 0)
   store <4 x i16> %c, ptr %vp
   ret void
; CHECK-NEXT:    ret
   %c = call <8 x i1> @llvm.vector.insert.v4i1.v8i1(<8 x i1> %v, <4 x i1> %sv, i64 4)
   store <8 x i1> %c, ptr %vp
   ret void
 }
 
 define <vscale x 2 x i16> @insert_nxv2i16_v2i16_0(<vscale x 2 x i16> %v, ptr %svp) {
 ; CHECK-LABEL: insert_nxv2i16_v2i16_0:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT:    vle16.v v9, (a0)
-; CHECK-NEXT:    vsetivli zero, 2, e16, mf2, tu, ma
-; CHECK-NEXT:    vmv.v.v v8, v9
+; CHECK-NEXT:    vsetivli zero, 2, e16, mf4, tu, ma
+; CHECK-NEXT:    vle16.v v8, (a0)
 ; CHECK-NEXT:    ret
   %sv = load <2 x i16>, ptr %svp
   %c = call <vscale x 2 x i16> @llvm.vector.insert.v2i16.nxv2i16(<vscale x 2 x i16> %v, <2 x i16> %sv, i64 0)
   ret <vscale x 2 x i16> %c
 }
 
 define <vscale x 2 x i16> @insert_nxv2i16_v2i16_2(<vscale x 2 x i16> %v, ptr %svp) {
 ; CHECK-LABEL: insert_nxv2i16_v2i16_2: