[RISCV] Add a common base class for RVInstR variations. NFC

[craig.topper]

Summary

We have multiple variations of InstrFormatR that pack different
fields into the upper 7 bits. The other 25 bits are all the same.

Add base class to capture this commonality and allow subclasses to
explicitly define Inst{31-25}.

[asb]

LGTM

llvm/lib/Target/RISCV/RISCVInstrFormats.td

class PseudoStore<string opcodestr, RegisterClass rsty = GPR>
   let hasSideEffects = 0;
   let mayLoad = 0;
   let mayStore = 1;
   let isCodeGenOnly = 0;
   let isAsmParserOnly = 1;
 }
 
 // Instruction formats are listed in the order they appear in the RISC-V
-// instruction set manual (R, I, S, B, U, J) with sub-formats (e.g. RVInstR4,
-// RVInstRAtomic) sorted alphabetically.
+// instruction set manual (R, R4, I, S, B, U, J).
 
-class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+// Common base class for R format instructions. Bits {31-25} should be set by
+// the subclasses.
+class RVInstRBase<bits<3> funct3, RISCVOpcode opcode, dag outs,
                   dag ins, string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
-               dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
-  bits<5> rs3;
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
+class RVInstR<bits<7> funct7, bits<3> funct3, RISCVOpcode opcode, dag outs,
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  let Inst{31-25} = funct7;
+}
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = funct2;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
+class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
+                    RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
+                    string argstr>
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  let Inst{31-27} = funct5;
+  let Inst{26} = aq;
+  let Inst{25} = rl;
 }
 
-class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
-                  string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
-  bits<5> rs3;
+class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
-  let Inst{31-27} = rs3;
-  let Inst{26-25} = funct2;
+  let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstRAtomic<bits<5> funct5, bit aq, bit rl, bits<3> funct3,
-                    RISCVOpcode opcode, dag outs, dag ins, string opcodestr,
-                    string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+class RVInstR4<bits<2> funct2, bits<3> funct3, RISCVOpcode opcode, dag outs,
+               dag ins, string opcodestr, string argstr>
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
+  bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-27} = funct5;
-  let Inst{26} = aq;
-  let Inst{25} = rl;
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
+class RVInstR4Frm<bits<2> funct2, RISCVOpcode opcode, dag outs, dag ins,
                   string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR4> {
+  bits<5> rs3;
   bits<5> rs2;
   bits<5> rs1;
   bits<3> frm;
   bits<5> rd;
 
-  let Inst{31-25} = funct7;
+  let Inst{31-27} = rs3;
+  let Inst{26-25} = funct2;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
 // Common base class for I format instructions. Bits {31-20} should be set by

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

class CVInstMac<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1,
               (outs GPR:$rd_wb), (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
               opcodestr, "$rd, $rs1, $rs2"> {
   let DecoderNamespace = "XCVmac";
 }
 
 class CVInstMacMulN<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                     string opcodestr>
-    : RVInst<outs, ins, opcodestr, "$rd, $rs1, $rs2, $imm5",
-             [], InstFormatOther> {
+    : RVInstRBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr,
+                  "$rd, $rs1, $rs2, $imm5"> {
   bits<5> imm5;
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-30} = funct2;
   let Inst{29-25} = imm5;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = OPC_CUSTOM_2.Value;
   let DecoderNamespace = "XCVmac";
 }
 
 class CVInstMacN<bits<2> funct2, bits<3> funct3, string opcodestr>
     : CVInstMacMulN<funct2, funct3, (outs GPR:$rd_wb),
                     (ins GPR:$rd, GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr>;
 
 class CVInstMulN<bits<2> funct2, bits<3> funct3, string opcodestr>
let Predicates = [HasVendorXCVmac, IsRV32] in {
   def : InstAlias<"cv.mulu $rd1, $rs1, $rs2",
                   (CV_MULUN GPR:$rd1,   GPR:$rs1, GPR:$rs2, 0)>;
   def : InstAlias<"cv.mulhhu $rd1, $rs1, $rs2",
                   (CV_MULHHUN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0)>;
 } // Predicates = [HasVendorXCVmac, IsRV32]
 
 let DecoderNamespace = "XCValu" in {
   class CVInstAluRRI<bits<2> funct2, bits<3> funct3, string opcodestr>
-      : RVInst<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5),
-                opcodestr, "$rd, $rs1, $rs2, $imm5", [], InstFormatOther> {
+      : RVInstRBase<funct3, OPC_CUSTOM_2, (outs GPR:$rd),
+                    (ins GPR:$rs1, GPR:$rs2, uimm5:$imm5), opcodestr,
+                    "$rd, $rs1, $rs2, $imm5"> {
     bits<5> imm5;
-    bits<5> rs2;
-    bits<5> rs1;
-    bits<5> rd;
 
     let Inst{31-30} = funct2;
     let Inst{29-25} = imm5;
-    let Inst{24-20} = rs2;
-    let Inst{19-15} = rs1;
-    let Inst{14-12} = funct3;
-    let Inst{11-7} = rd;
-    let Inst{6-0} = OPC_CUSTOM_2.Value;
   }
 
   class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
               (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),

 } // Predicates = [HasVendorXCValu],
   //   hasSideEffects = 0, mayLoad = 0, mayStore = 0,
   //   Constraints = "$rd = $rd_wb"
 
 
 class CVInstSIMDRR<bits<5> funct5, bit F, bit funct1, bits<3> funct3,
                    RISCVOpcode opcode, dag outs,
                    dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
-  bits<5> rs2;
-  bits<5> rs1;
-  bits<5> rd;
-
+    : RVInstRBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   let Inst{31-27} = funct5;
   let Inst{26} = F;
   let Inst{25} = funct1;
-  let Inst{24-20} = rs2;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
   let DecoderNamespace = "XCVsimd";
 }
 
 class CVInstSIMDRI<bits<5> funct5, bit F, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
     : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<6> imm6;
 

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

class THVdotALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
     : THInstVdotVX<funct6, opv, (outs VR:$vd),
                    (ins GPR:$rs1, VR:$vs2, VMaskOp:$vm),
                    opcodestr, "$vd, $rs1, $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
 let Predicates = [HasVendorXTHeadBa], DecoderNamespace = "XTHeadBa",
     hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class THShiftALU_rri<bits<3> funct3, string opcodestr>
-    : RVInstR<0, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+    : RVInstRBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
                   (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
                   opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
   let Inst{31-27} = 0;
   let Inst{26-25} = uimm2;
 }
 
 let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "XTHeadBb",
     hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
: RVInstR<funct7, 0b001, OPC_CUSTOM_0, (outs GPR:$rd_wb),
               (ins GPR:$rd, GPR:$rs1, GPR:$rs2),
               opcodestr, "$rd, $rs1, $rs2"> {
   let Constraints = "$rd_wb = $rd";
 }
 
 let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
     hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
 class THLoadPair<bits<5> funct5, string opcodestr>
-  : RVInstR<!shl(funct5, 2), 0b100, OPC_CUSTOM_0,
+  : RVInstRBase<0b100, OPC_CUSTOM_0,
                 (outs GPR:$rd, GPR:$rs2),
                 (ins GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
                  opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
   let DecoderMethod = "decodeXTHeadMemPair";
   let Constraints = "@earlyclobber $rd,@earlyclobber $rs2";
 }
 
 let Predicates = [HasVendorXTHeadMemPair], DecoderNamespace = "XTHeadMemPair",
     hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
 class THStorePair<bits<5> funct5, string opcodestr>
-  : RVInstR<!shl(funct5, 2), 0b101, OPC_CUSTOM_0,
-            (outs),
+  : RVInstRBase<0b101, OPC_CUSTOM_0, (outs),
               (ins GPR:$rd, GPR:$rs2, GPR:$rs1, uimm2:$uimm2, uimm7:$const3or4),
               opcodestr, "$rd, $rs2, (${rs1}), $uimm2, $const3or4"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
   let DecoderMethod = "decodeXTHeadMemPair";
 }
 
 let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
 class THCacheInst_r<bits<5> funct5, string opcodestr>
     : RVInstR<0b0000001, 0, OPC_CUSTOM_0, (outs), (ins GPR:$rs1),
               opcodestr, "$rs1"> {
class THCacheInst_void<bits<5> funct5, string opcodestr>
     : RVInstR<0b0000000, 0, OPC_CUSTOM_0, (outs), (ins), opcodestr, ""> {
   let rd = 0;
   let rs1 = 0;
   let rs2 = funct5;
 }
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
 class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
-    : RVInstR<!shl(funct5, 2), !if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
+    : RVInstRBase<!if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
                   (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
                   opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
 }
 
 class THLoadUpdate<bits<5> funct5, string opcodestr>
     : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
                   (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
                   opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;
   bits<2> uimm2;
   let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
   let Inst{24-20} = simm5;
   let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";
 }
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>
-    : RVInstR<!shl(funct5, 2), !if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
+    : RVInstRBase<!if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
                   (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
                   opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
+  let Inst{31-27} = funct5;
   let Inst{26-25} = uimm2;
 }
 
 class THStoreUpdate<bits<5> funct5, string opcodestr>
     : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
                   (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
                   opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;