[RISCV] Add a common base class for RVInstI variations. NFC

[craig.topper]

Summary

We have multiple variations of InstrFormatI that pack different
fields into the upper 12 bits. The other 20 bits are all the same.

Add base class to capture this commonality and allow subclasses to
explicitly define Inst{31-20}.

[jrtc27]

llvm/lib/Target/RISCV/RISCVInstrFormats.td

404–406

[craig.topper]

Fix typo

[craig.topper]

Use RVInstIBase in another place

[craig.topper]

Address review comment

[asb]

Thanks, I think this is overall better. I'd thought that having other top-level classes with explicit Inst{...} assignments might be easier to follow, but this patch demonstrates how that incentivises people to inherit from RVInstI and assign imm12 which isn't particularly easy to review.

llvm/lib/Target/RISCV/RISCVInstrFormats.td

class RVInstRFrm<bits<7> funct7, RISCVOpcode opcode, dag outs, dag ins,
   let Inst{31-25} = funct7;
   let Inst{24-20} = rs2;
   let Inst{19-15} = rs1;
   let Inst{14-12} = frm;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
-class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+// Common base class for instructions I format instructions. Bits {31-20}
+// should be set by the subclasses.
+class RVInstIBase<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
                   string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
-  bits<12> imm12;
   bits<5> rs1;
   bits<5> rd;
 
-  let Inst{31-20} = imm12;
   let Inst{19-15} = rs1;
   let Inst{14-12} = funct3;
   let Inst{11-7} = rd;
   let Inst{6-0} = opcode.Value;
 }
 
+class RVInstI<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
+              string opcodestr, string argstr>
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
+  bits<12> imm12;
+
+  let Inst{31-20} = imm12;
+}
+
 class RVInstIShift<bits<5> imm11_7, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<6> shamt;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-27} = imm11_7;
   let Inst{26} = 0;
   let Inst{25-20} = shamt;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIShiftW<bits<7> imm11_5, bits<3> funct3, RISCVOpcode opcode,
                     dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<5> shamt;
-  bits<5> rs1;
-  bits<5> rd;
 
   let Inst{31-25} = imm11_5;
   let Inst{24-20} = shamt;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstIUnary<bits<12> imm12, bits<3> funct3, RISCVOpcode opcode,
                    dag outs, dag ins, string opcodestr, string argstr>
-    : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
-  bits<5> rs1;
+    : RVInstIBase<funct3, opcode, outs, ins, opcodestr, argstr> {
   bits<5> rd;
 
   let Inst{31-20} = imm12;
-  let Inst{19-15} = rs1;
-  let Inst{14-12} = funct3;
-  let Inst{11-7} = rd;
-  let Inst{6-0} = opcode.Value;
 }
 
 class RVInstS<bits<3> funct3, RISCVOpcode opcode, dag outs, dag ins,
               string opcodestr, string argstr>
     : RVInst<outs, ins, opcodestr, argstr, [], InstFormatS> {
   bits<12> imm12;
   bits<5> rs2;
   bits<5> rs1;

llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td

 //===-- RISCVInstrInfoXCV.td - CORE-V instructions ---------*- tablegen -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the vendor extensions defined by Core-V extensions.
 //
 //===----------------------------------------------------------------------===//
 
 let DecoderNamespace = "XCVbitmanip" in {
   class CVInstBitManipRII<bits<2> funct2, bits<3> funct3, dag outs, dag ins,
                       string opcodestr, string argstr>
-      : RVInstI<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
+      : RVInstIBase<funct3, OPC_CUSTOM_2, outs, ins, opcodestr, argstr> {
     bits<5> is3;
     bits<5> is2;
-    let imm12 = {funct2, is3, is2};
+    let Inst{31-30} = funct2;
+    let Inst{29-25} = is3;
+    let Inst{24-20} = is2;
   }
 
   class CVBitManipRII<bits<2> funct2, bits<3> funct3, string opcodestr,
                       Operand i3type = uimm5>
       : CVInstBitManipRII<funct2, funct3, (outs GPR:$rd),
                           (ins GPR:$rs1, i3type:$is3, uimm5:$is2),
                           opcodestr, "$rd, $rs1, $is3, $is2">;
 
class CVInstAluRR<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd),
               (ins GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVInstAluRRNR<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd_wb),
               (ins GPR:$rd, GPR:$rs1, GPR:$rs2), opcodestr, "$rd, $rs1, $rs2">;
 
   class CVInstAluRI<bits<7> funct7, bits<3> funct3, string opcodestr>
-      : RVInst<(outs GPR:$rd), (ins GPR:$rs1, uimm5:$imm5), opcodestr,
-                "$rd, $rs1, $imm5", [], InstFormatOther> {
+      : RVInstIBase<funct3, OPC_CUSTOM_1, (outs GPR:$rd),
+                    (ins GPR:$rs1, uimm5:$imm5), opcodestr,
+                    "$rd, $rs1, $imm5"> {
     bits<5> imm5;
-    bits<5> rs1;
-    bits<5> rd;
 
     let Inst{31-25} = funct7;
     let Inst{24-20} = imm5;
-    let Inst{19-15} = rs1;
-    let Inst{14-12} = funct3;
-    let Inst{11-7} = rd;
-    let Inst{6-0} = OPC_CUSTOM_1.Value;
   }
 
   class CVInstAluR<bits<7> funct7, bits<3> funct3, string opcodestr>
     : RVInstR<funct7, funct3, OPC_CUSTOM_1, (outs GPR:$rd), (ins GPR:$rs1),
               opcodestr, "$rd, $rs1"> {
      let rs2 = 0b00000;
   }
 

llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td

 let Predicates = [HasVendorXTHeadBb], DecoderNamespace = "THeadBb",
   hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 class THShift_ri<bits<5> funct5, bits<3> funct3, string opcodestr>
     : RVInstIShift<funct5, funct3, OPC_CUSTOM_0, (outs GPR:$rd),
                    (ins GPR:$rs1, uimmlog2xlen:$shamt),
                    opcodestr, "$rd, $rs1, $shamt">;
 
 class THBitfieldExtract_rii<bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
+    : RVInstIBase<funct3, OPC_CUSTOM_0, (outs GPR:$rd),
                   (ins GPR:$rs1, uimmlog2xlen:$msb, uimmlog2xlen:$lsb),
                   opcodestr, "$rd, $rs1, $msb, $lsb"> {
   bits<6> msb;
   bits<6> lsb;
   let Inst{31-26} = msb;
   let Inst{25-20} = lsb;
 }
 
 class THRev_r<bits<5> funct5, bits<2> funct2, string opcodestr>
     : RVInstIUnary<{funct5, funct2, 0b00000}, 0b001, OPC_CUSTOM_0,
class THLoadIndexed<RegisterClass Ty, bits<5> funct5, string opcodestr>
     : RVInstR<!shl(funct5, 2), !if(!eq(Ty, GPR), 0b100, 0b110), OPC_CUSTOM_0,
               (outs Ty:$rd), (ins GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
               opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
   let Inst{26-25} = uimm2;
 }
 
 class THLoadUpdate<bits<5> funct5, string opcodestr>
-    : RVInstI<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
+    : RVInstIBase<0b100, OPC_CUSTOM_0, (outs GPR:$rd, GPR:$rs1_wb),
                   (ins GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
                   opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;
   bits<2> uimm2;
-  let imm12{11-7} = funct5;
-  let imm12{6-5} = uimm2;
-  let imm12{4-0} = simm5;
+  let Inst{31-27} = funct5;
+  let Inst{26-25} = uimm2;
+  let Inst{24-20} = simm5;
   let Constraints = "@earlyclobber $rd, $rs1_wb = $rs1";
 }
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 class THStoreIndexed<RegisterClass StTy, bits<5> funct5, string opcodestr>
     : RVInstR<!shl(funct5, 2), !if(!eq(StTy, GPR), 0b101, 0b111), OPC_CUSTOM_0,
               (outs), (ins StTy:$rd, GPR:$rs1, GPR:$rs2, uimm2:$uimm2),
               opcodestr, "$rd, $rs1, $rs2, $uimm2"> {
   bits<2> uimm2;
   let Inst{26-25} = uimm2;
 }
 
 class THStoreUpdate<bits<5> funct5, string opcodestr>
-    : RVInstI<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
+    : RVInstIBase<0b101, OPC_CUSTOM_0, (outs GPR:$rs1_up),
                   (ins GPR:$rd, GPR:$rs1, simm5:$simm5, uimm2:$uimm2),
                   opcodestr, "$rd, (${rs1}), $simm5, $uimm2"> {
   bits<5> simm5;
   bits<2> uimm2;
-  let imm12{11-7} = funct5;
-  let imm12{6-5} = uimm2;
-  let imm12{4-0} = simm5;
+  let Inst{31-27} = funct5;
+  let Inst{26-25} = uimm2;
+  let Inst{24-20} = simm5;
   let Constraints = "$rs1_up = $rs1";
 }
 }
 
 //===----------------------------------------------------------------------===//
 // Combination of instruction classes.
 // Use these multiclasses to define instructions more easily.
 //===----------------------------------------------------------------------===//

llvm/lib/Target/RISCV/RISCVInstrInfoZk.td

: RVInstR<{0b00, funct5}, 0b000, OPC_OP, (outs GPR:$rd),
               (ins GPR:$rs1, GPR:$rs2, byteselect:$bs),
               opcodestr, "$rd, $rs1, $rs2, $bs">{
   bits<2> bs;
   let Inst{31-30} = bs;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVKUnary_rnum<bits<7> funct7, bits<3> funct3, string opcodestr>
-    : RVInstI<funct3, OPC_OP_IMM, (outs GPR:$rd), (ins GPR:$rs1, rnum:$rnum),
-              opcodestr, "$rd, $rs1, $rnum">{
+    : RVInstIBase<funct3, OPC_OP_IMM, (outs GPR:$rd),
+                  (ins GPR:$rs1, rnum:$rnum), opcodestr, "$rd, $rs1, $rnum"> {
   bits<4> rnum;
-  let imm12{11-5} = funct7;
-  let imm12{4} = 0b1;
-  let imm12{3-0} = rnum;
+  let Inst{31-25} = funct7;
+  let Inst{24} = 0b1;
+  let Inst{23-20} = rnum;
 }
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 let Predicates = [HasStdExtZknd, IsRV32] in {
 def AES32DSI  : RVKByteSelect<0b10101, "aes32dsi">;
 def AES32DSMI : RVKByteSelect<0b10111, "aes32dsmi">;