Lower to the strided/contiguous addressing mode of
ld1/ldnt1 instructions depending on register allocation.
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| Differential D156311
[AArch64][SME2][SVE2p1] Choose strided or contiguous loads ClosedPublic Authored by MattDevereau on Jul 26 2023, 4:17 AM.
Details Summary Lower to the strided/contiguous addressing mode of
Diff Detail
Unit TestsFailed Event TimelineThis revision is now accepted and ready to land.Aug 7 2023, 5:22 AM This revision was landed with ongoing or failed builds.Aug 8 2023, 4:51 AM Closed by commit rGe8efe7f9d1e9: [AArch64][SME2][SVE2p1] Choose strided or contiguous loads (authored by MattDevereau). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 544296 llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sme2-intrinsics-ld1.ll
llvm/test/CodeGen/AArch64/sme2-intrinsics-ldnt1.ll
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