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[AArch64][SME2][SVE2p1] Choose strided or contiguous loads
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Authored by MattDevereau on Jul 26 2023, 4:17 AM.

Details

Summary

Lower to the strided/contiguous addressing mode of
ld1/ldnt1 instructions depending on register allocation.

Diff Detail

Event Timeline

MattDevereau created this revision.Jul 26 2023, 4:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 4:17 AM
MattDevereau requested review of this revision.Jul 26 2023, 4:17 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 26 2023, 4:17 AM
Matt added a subscriber: Matt.Aug 1 2023, 2:29 PM
This revision is now accepted and ready to land.Aug 7 2023, 5:22 AM
This revision was landed with ongoing or failed builds.Aug 8 2023, 4:51 AM
This revision was automatically updated to reflect the committed changes.
llvm/lib/Target/AArch64/SVEInstrFormats.td