[RISCV] Implement ifunc selector

[BeMg]

Summary

Here is proposal https://github.com/riscv-non-isa/riscv-c-api-doc/pull/48.

During the Function multi-version dispatch the function, we need a method to retrieve the RISC-V hardware environment to make sure all extension must be available.

[jrtc27]

This series is all highly Linux-specific and needs gating accordingly

[BeMg]

Guard with linux

[craig.topper]

compiler-rt/lib/builtins/riscv/ifunc_select.c

9

This is bzero rather than memset. memset doesn't write 0.

26

this is memcpy not strncpy. strncpy stops when it encounters the null terminator.

40

efficient*

192

init*

[kito-cheng]

All linux specific stuffs should guarded with __linux__ too, like those syscall stuffs and read /proc/cpuinfo

compiler-rt/lib/builtins/riscv/ifunc_select.c

116

Define 1024 as something like BUFLEN?

188

Try to define those magic number into something __NR_riscv_hwprobe?

[BeMg]

1. Guard more code with linux
2. Update function name
3. Define some marco for system call number and buffer size

[BeMg]

Rebase

compiler-rt/lib/builtins/CMakeLists.txt

set(powerpc64_SOURCES
     ppc/fixtfti.c
     ppc/fixunstfti.c
     ${powerpc64_SOURCES}
   )
 endif()
 set(powerpc64le_SOURCES ${powerpc64_SOURCES})
 
 set(riscv_SOURCES
+  riscv/ifunc_select.c
   riscv/fp_mode.c
   riscv/save.S
   riscv/restore.S
   ${GENERIC_SOURCES}
   ${GENERIC_TF_SOURCES}
 )
 set(riscv32_SOURCES
   riscv/mulsi3.S

compiler-rt/lib/builtins/riscv/ifunc_select.c

+//=== ifunc_select.c - Check environment hardware feature -*- C -*-===========//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+static void __riscv_memset(char *s, unsigned size) {
+  for (int i = 0; i < size; i++)
+    s[i] = '\0';
+}
+
+static unsigned __riscv_strcmp(char *a, char *b) {
+  while (*a != '\0' && *b != '\0') {
+    if (*a != *b)
+      return 0;
+    a++;
+    b++;
+  }
+  if (*a == *b)
+    return 1;
+  return 0;
+}
+
+static void __riscv_strncpy(char *a, char *b, unsigned len) {
+  for (unsigned i = 0; i < len; i++)
+    a[i] = b[i];
+}
+
+static unsigned __riscv_strlen(char *s) {
+  int len = 0;
+  while (*s != '\0') {
+    len++;
+    s++;
+  }
+  return len;
+}
+
+// TODO: Replace with more efficiency algorithm
+static unsigned __riscv_isPatternInSrc(char *src, char *pattern) {
+  char buf[1024];
+  int lenOfSrc = __riscv_strlen(src);
+  int lenOfPattern = __riscv_strlen(pattern);
+  for (int i = 0; i + lenOfPattern < lenOfSrc; i++) {
+    __riscv_memset(buf, 1024);
+    __riscv_strncpy(buf, src + i, lenOfPattern);
+    if (__riscv_strcmp(buf, pattern))
+      return 1;
+  }
+  return 0;
+}
+
+static char *__riscv_tokenize(char *src, char *rst, char delim) {
+  while (*src != '\0' && *src != delim) {
+    *rst = *src;
+    src++;
+    rst++;
+  }
+  if (*src == delim)
+    src++;
+  return src;
+}
+
+long syscall_impl_3_args(long number, long arg1, long arg2, long arg3) {
+  register long a7 __asm__("a7") = number;
+  register long a0 __asm__("a0") = arg1;
+  register long a1 __asm__("a1") = arg2;
+  register long a2 __asm__("a2") = arg3;
+  __asm__ __volatile__("ecall\n\t"
+                       : "=r"(a0)
+                       : "r"(a7), "r"(a0), "r"(a1), "r"(a2)
+                       : "memory");
+  return a0;
+}
+
+long syscall_impl_5_args(long number, long arg1, long arg2, long arg3,
+                         long arg4, long arg5) {
+  register long a7 __asm__("a7") = number;
+  register long a0 __asm__("a0") = arg1;
+  register long a1 __asm__("a1") = arg2;
+  register long a2 __asm__("a2") = arg3;
+  register long a3 __asm__("a3") = arg4;
+  register long a4 __asm__("a4") = arg5;
+  __asm__ __volatile__("ecall\n\t"
+                       : "=r"(a0)
+                       : "r"(a7), "r"(a0), "r"(a1), "r"(a2), "r"(a3), "r"(a4)
+                       : "memory");
+  return a0;
+}
+
+static unsigned write(int fd, const void *buf, unsigned count) {
+  return syscall_impl_3_args(64, fd, (long)buf, count);
+}
+
+static unsigned read(int fd, const void *buf, unsigned count) {
+  return syscall_impl_3_args(63, fd, (long)buf, count);
+}
+
+static int openat(int dirfd, const char *pathname, int flags) {
+  return syscall_impl_3_args(56, (long)dirfd, (long)pathname, flags);
+}
+
+void __riscv_print(char *s) { write(0, s, __riscv_strlen(s)); }
+
+void readUntilNextLine(int fd, char *rst, int len) {
+  char buf = '\0';
+  while (buf != '\n' && read(fd, &buf, 1) != 0 && len > 0) {
+    *rst = buf;
+    rst++;
+    len--;
+  }
+}
+
+void __riscv_cpuinfo(char *FeatStr) {
+  char buf[1024];
+  int fd = openat(0, "/proc/cpuinfo", 2);
+  do {
+    __riscv_memset(buf, 1024);
+    readUntilNextLine(fd, buf, 1024);
+    if (__riscv_isPatternInSrc(buf, "isa")) {
+      __riscv_strncpy(FeatStr, buf, 1024);
+      return;
+    }
+  } while (__riscv_strlen(buf) != 0);
+}
+
+void getBasicExtFromHwFeatStr(char *rst, char *src) {
+  while (*src != 'r') {
+    src++;
+  }
+
+  while (*src != '_' && *src != '\0') {
+    *rst = *src;
+    rst++;
+    src++;
+  }
+}
+
+unsigned checkFeatStrInHwFeatStr(char *FeatStr, char *HwFeatStr) {
+  if (__riscv_strlen(FeatStr) == 1) {
+    char BasicExt[1024];
+    __riscv_memset(BasicExt, 1024);
+    getBasicExtFromHwFeatStr(BasicExt, HwFeatStr);
+    return __riscv_isPatternInSrc(BasicExt, FeatStr);
+  }
+  return __riscv_isPatternInSrc(HwFeatStr, FeatStr);
+}
+
+struct riscv_hwprobe {
+  long long key;
+  unsigned long long value;
+};
+
+#define RISCV_HWPROBE_MAX_KEY 5
+#define RISCV_HWPROBE_KEY_MVENDORID 0
+#define RISCV_HWPROBE_KEY_MARCHID 1
+#define RISCV_HWPROBE_KEY_MIMPID 2
+#define RISCV_HWPROBE_KEY_BASE_BEHAVIOR 3
+#define RISCV_HWPROBE_BASE_BEHAVIOR_IMA (1 << 0)
+#define RISCV_HWPROBE_KEY_IMA_EXT_0 4
+#define RISCV_HWPROBE_IMA_FD (1 << 0)
+#define RISCV_HWPROBE_IMA_C (1 << 1)
+#define RISCV_HWPROBE_IMA_V (1 << 2)
+#define RISCV_HWPROBE_EXT_ZBA (1 << 3)
+#define RISCV_HWPROBE_EXT_ZBB (1 << 4)
+#define RISCV_HWPROBE_EXT_ZBS (1 << 5)
+#define RISCV_HWPROBE_KEY_CPUPERF_0 5
+#define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0)
+#define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0)
+#define RISCV_HWPROBE_MISALIGNED_SLOW (2 << 0)
+#define RISCV_HWPROBE_MISALIGNED_FAST (3 << 0)
+#define RISCV_HWPROBE_MISALIGNED_UNSUPPORTED (4 << 0)
+#define RISCV_HWPROBE_MISALIGNED_MASK (7 << 0)
+
+/* Size definition for CPU sets.  */
+#define __CPU_SETSIZE 1024
+#define __NCPUBITS (8 * sizeof(unsigned long int))
+
+/* Data structure to describe CPU mask.  */
+typedef struct {
+  unsigned long int __bits[__CPU_SETSIZE / __NCPUBITS];
+} cpu_set_t;
+
+long sys_riscv_hwprobe(struct riscv_hwprobe *pairs, unsigned pair_count,
+                       unsigned cpu_count, cpu_set_t *cpus,
+                       unsigned int flags) {
+  return syscall_impl_5_args(258, (long)pairs, pair_count, cpu_count,
+                             (long)cpus, flags);
+}
+
+void intiHwProbe(struct riscv_hwprobe *Hwprobes, int len) {
+  sys_riscv_hwprobe(Hwprobes, len, 0, 0, 0);
+}
+
+unsigned checkFeatStrInHwProbe(char *FeatStr, struct riscv_hwprobe Hwprobe) {
+  if (Hwprobe.key == -1)
+    return 0;
+
+  if (__riscv_strcmp(FeatStr, "i"))
+    return Hwprobe.value & RISCV_HWPROBE_KEY_IMA_EXT_0;
+  if (__riscv_strcmp(FeatStr, "m"))
+    return Hwprobe.value & RISCV_HWPROBE_KEY_IMA_EXT_0;
+  if (__riscv_strcmp(FeatStr, "a"))
+    return Hwprobe.value & RISCV_HWPROBE_KEY_IMA_EXT_0;
+  if (__riscv_strcmp(FeatStr, "f"))
+    return Hwprobe.value & RISCV_HWPROBE_IMA_FD;
+  if (__riscv_strcmp(FeatStr, "d"))
+    return Hwprobe.value & RISCV_HWPROBE_IMA_FD;
+  if (__riscv_strcmp(FeatStr, "c"))
+    return Hwprobe.value & RISCV_HWPROBE_IMA_C;
+  if (__riscv_strcmp(FeatStr, "v"))
+    return Hwprobe.value & RISCV_HWPROBE_IMA_V;
+  if (__riscv_strcmp(FeatStr, "zba"))
+    return Hwprobe.value & RISCV_HWPROBE_EXT_ZBA;
+  if (__riscv_strcmp(FeatStr, "zbb"))
+    return Hwprobe.value & RISCV_HWPROBE_EXT_ZBB;
+  if (__riscv_strcmp(FeatStr, "zbs"))
+    return Hwprobe.value & RISCV_HWPROBE_EXT_ZBS;
+
+  return 0;
+}
+
+// FeatStr format is like <Feature1>;<Feature2>...<FeatureN>.
+unsigned __riscv_ifunc_select(char *FeatStrs) {
+#if defined(__linux__)
+  // Init Hwprobe
+  struct riscv_hwprobe pairs[] = {
+      {RISCV_HWPROBE_KEY_IMA_EXT_0, 0},
+  };
+  intiHwProbe(pairs, 1);
+
+  // Init from cpuinfo
+  char HwFeatStr[1024];
+  __riscv_memset(HwFeatStr, 1024);
+  __riscv_cpuinfo(HwFeatStr);
+
+  // Check each extension whether available
+  char FeatStr[1024];
+  while (*FeatStrs != '\0') {
+    __riscv_memset(FeatStr, 1024);
+    FeatStrs = __riscv_tokenize(FeatStrs, FeatStr, ';');
+    if (checkFeatStrInHwProbe(FeatStr, pairs[0]))
+      continue;
+    if (!checkFeatStrInHwFeatStr(FeatStr, HwFeatStr))
+      return 0;
+  }
+
+  return 1;
+#else
+  // If other platform support IFUNC, need to implement its
+  // __riscv_ifunc_select.
+  return 0;
+#endif
+}