[JITLink][PowerPC] Support R_PPC64_PCREL34

[lkail]

Summary

PC-relative instructions are added in ISA-3.1 implemented by pwr10. This patch adds basic pc-relative relocation.

[lhames]

llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h

222–234

Could you add a comment to these?

It looks like they read/write 64-bits, masking out the high 32-bits iff little-endian?

[lkail]

Add comment to explain how prefixed instruction is formed.

llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h

222–234

When it's little-endian, swap the high 32 bits and the low 32 bits. I've added the comment, please let me know if it's still a puzzle.

[lhames]

LGTM. Thanks @lkail!

llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h

222–234

Yep -- I misread the expression. The comment explains things nicely, thanks!

llvm/include/llvm/ExecutionEngine/JITLink/ppc64.h

 
 namespace llvm::jitlink::ppc64 {
 
 /// Represents ppc64 fixups and other ppc64-specific edge kinds.
 enum EdgeKind_ppc64 : Edge::Kind {
   Pointer64 = Edge::FirstRelocation,
   Pointer32,
   Delta64,
+  Delta34,
   Delta32,
   NegDelta32,
   Delta16,
   Delta16HA,
   Delta16LO,
   TOCDelta16HA,
   TOCDelta16LO,
   TOCDelta16DS,

 /// Returns a string name for the given ppc64 edge. For debugging purposes
 /// only.
 const char *getEdgeKindName(Edge::Kind K);
 
 inline static uint16_t ha16(uint64_t x) { return (x + 0x8000) >> 16; }
 
 inline static uint16_t lo16(uint64_t x) { return x & 0xffff; }
 
+// Prefixed instruction introduced in ISAv3.1 consists of two 32-bit words,
+// prefix word and suffix word, i.e., prefixed_instruction = concat(prefix_word,
+// suffix_word). That's to say, for a prefixed instruction encoded in uint64_t,
+// the most significant 32 bits belong to the prefix word. The prefix word is at
+// low address for both big/little endian. Byte order in each word still follows
+// its endian.
+template <support::endianness Endianness>
+inline static uint64_t readPrefixedInstruction(const char *Loc) {
+  constexpr bool isLE = Endianness == support::endianness::little;
+  uint64_t Inst = support::endian::read64<Endianness>(Loc);
+  return isLE ? (Inst << 32) | (Inst >> 32) : Inst;
+}
+
+template <support::endianness Endianness>
+inline static void writePrefixedInstruction(char *Loc, uint64_t Inst) {
+  constexpr bool isLE = Endianness == support::endianness::little;
+  Inst = isLE ? (Inst << 32) | (Inst >> 32) : Inst;
+  support::endian::write64<Endianness>(Loc, Inst);
+}
+
 /// Apply fixup expression for edge to block content.
 template <support::endianness Endianness>
 inline Error applyFixup(LinkGraph &G, Block &B, const Edge &E,
                         const Symbol *TOCSymbol) {
   char *BlockWorkingMem = B.getAlreadyMutableContent().data();
   char *FixupPtr = BlockWorkingMem + E.getOffset();
   orc::ExecutorAddr FixupAddress = B.getAddress() + E.getOffset();
   int64_t S = E.getTarget().getAddress().getValue();
case CallBranchDelta: {
     }
     break;
   }
   case Delta64: {
     int64_t Value = S + A - P;
     support::endian::write64<Endianness>(FixupPtr, Value);
     break;
   }
+  case Delta34: {
+    int64_t Value = S + A - P;
+    if (!LLVM_UNLIKELY(isInt<34>(Value)))
+      return makeTargetOutOfRangeError(G, B, E);
+    static const uint64_t SI0Mask = 0x00000003ffff0000;
+    static const uint64_t SI1Mask = 0x000000000000ffff;
+    static const uint64_t FullMask = 0x0003ffff0000ffff;
+    uint64_t Inst = readPrefixedInstruction<Endianness>(FixupPtr) & ~FullMask;
+    writePrefixedInstruction<Endianness>(
+        FixupPtr, Inst | ((Value & SI0Mask) << 16) | (Value & SI1Mask));
+    break;
+  }
   case Delta32: {
     int64_t Value = S + A - P;
     if (LLVM_UNLIKELY(!isInt<32>(Value))) {
       return makeTargetOutOfRangeError(G, B, E);
     }
     support::endian::write32<Endianness>(FixupPtr, Value);
     break;
   }

llvm/lib/ExecutionEngine/JITLink/ELF_ppc64.cpp

case ELF::R_PPC64_REL24: {
         Kind = ELFReloc == ELF::R_PPC64_REL24 ? ppc64::RequestPLTCallStubSaveTOC
                                               : ppc64::RequestPLTCallStubNoTOC;
       }
       break;
     }
     case ELF::R_PPC64_REL64:
       Kind = ppc64::Delta64;
       break;
+    case ELF::R_PPC64_PCREL34:
+      Kind = ppc64::Delta34;
+      break;
     }
 
     Edge GE(Kind, Offset, *GraphSymbol, Addend);
     BlockToFix.addEdge(std::move(GE));
     return Error::success();
   }
 
 public:

llvm/lib/ExecutionEngine/JITLink/ppc64.cpp

 const char *getEdgeKindName(Edge::Kind K) {
   switch (K) {
   case Pointer64:
     return "Pointer64";
   case Pointer32:
     return "Pointer32";
   case Delta64:
     return "Delta64";
+  case Delta34:
+    return "Delta34";
   case Delta32:
     return "Delta32";
   case NegDelta32:
     return "NegDelta32";
   case Delta16:
     return "Delta16";
   case Delta16HA:
     return "Delta16HA";

llvm/test/ExecutionEngine/JITLink/ppc64/ELF_ppc64le_relocations.s

# jitlink-check:   ((got_addr(elf_reloc.o, external_func_notoc) - stub_addr(elf_reloc.o, external_func_notoc)) - 8) & 0xffff
   .global test_external_call_notoc
   .p2align 4
   .type test_external_call_notoc,@function
 test_external_call_notoc:
   bl external_func_notoc@notoc
   blr
   .size test_external_call_notoc, .-test_external_call_notoc
 
+# Check R_PPC64_PCREL34
+# jitlink-check: (section_addr(elf_reloc.o, .rodata.str1.1) - test_pcrel34)[33:0] = \
+# jitlink-check:   ((((*{4}(test_pcrel34)) & 0x3ffff) << 16) | ((*{4}(test_pcrel34 + 4)) & 0xffff))[33:0]
+  .global test_pcrel34
+  .p2align 4
+  .type test_pcrel34,@function
+test_pcrel34:
+  paddi 3, 0, .L.str@PCREL, 1
+  blr
+  .size test_pcrel34, .-test_pcrel34
+
+  .type .L.str,@object
+  .section  .rodata.str1.1,"aMS",@progbits,1
+.L.str:
+  .asciz  "Hey!"
+  .size .L.str, 5
+
  .section .toc,"aw",@progbits
 .LC0:
   .tc external_data[TC],external_data

llvm/test/ExecutionEngine/JITLink/ppc64/ppc64le-relocs.s

.Lfunc_begin7:
   .localentry bar, 1
   b foo@notoc
   #TC_RETURNd8 foo@notoc 0
   .long 0
   .quad 0
 .Lfunc_end7:
   .size bar, .Lfunc_end7-.Lfunc_begin7
 
+  .global foobar
+  .p2align
+  .type foobar,@function
+foobar:
+.Lfunc_begin8:
+  .localentry foobar, 1
+  paddi 3, 0, .L.str@PCREL, 1
+  blr
+.Lfunc_end8:
+  .size foobar, .Lfunc_end8-.Lfunc_end8
+
   .type local_var,@object
   .section  .bss,"aw",@nobits
   .globl  local_var
   .p2align  2, 0x0
 local_var:
   .long 0
   .size local_var, 4