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Differential D155697

[RISCV] Add tests for vnsr[l,a].wx patterns that could be matched
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Authored by luke on Jul 19 2023, 6:23 AM.

Details

Reviewers
craig.topper
reames
frasercrmck
kito-cheng
Jimerlife
Commits
rG418e678ba3b4: [RISCV] Add tests for vnsr[l,a].wx patterns that could be matched
Summary

These patterns of ([l,a]shr v, ([s,z]ext splat)) only pick up the cases where
the scalar has the same type as the vector element. However since only the low
log2(SEW) bits of the scalar are read, we could use any scalar type that has
been extended.

Diff Detail

Event Timeline

luke created this revision.Jul 19 2023, 6:23 AM
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luke requested review of this revision.Jul 19 2023, 6:23 AM
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luke added a child revision: D155698: [RISCV] Add patterns for vnsr[a,l].wx where shift amount has different type than vector element.Jul 19 2023, 6:24 AM
Harbormaster completed remote builds in B246531: Diff 541989.Jul 19 2023, 8:17 AM
craig.topper accepted this revision.Jul 19 2023, 7:06 PM

LGTM

This revision is now accepted and ready to land.Jul 19 2023, 7:06 PM
Closed by commit rG418e678ba3b4: [RISCV] Add tests for vnsr[l,a].wx patterns that could be matched (authored by luke). · Explain WhyJul 21 2023, 2:13 AM
This revision was automatically updated to reflect the committed changes.
luke added a commit: rG418e678ba3b4: [RISCV] Add tests for vnsr[l,a].wx patterns that could be matched.

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
364 lines
364 lines

Diff 542816

llvm/test/CodeGen/RISCV/rvv/vnsra-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsra_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsra_wx_i64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsra.vx v8, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%x = ashr <vscale x 1 x i64> %va, %splat
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 2 x i32> @vnsra_wx_i64_nxv2i32(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsra_wx_i64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vsra.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%x = ashr <vscale x 2 x i64> %va, %splat
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 4 x i32> @vnsra_wx_i64_nxv4i32(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsra_wx_i64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vsra.vx v12, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%x = ashr <vscale x 4 x i64> %va, %splat
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 8 x i32> @vnsra_wx_i64_nxv8i32(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsra_wx_i64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vsra.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = ashr <vscale x 8 x i64> %va, %splat
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) { define <vscale x 1 x i32> @vnsra_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsra_wv_nxv1i32_sext: ; CHECK-LABEL: vnsra_wv_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsra.wv v8, v8, v9 ; CHECK-NEXT: vnsra.wv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64> %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vc %x = ashr <vscale x 1 x i64> %va, %vc
Show All 10 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64> %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb %x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y ret <vscale x 1 x i32> %y
} }
define <vscale x 1 x i32> @vnsra_wx_i16_nxv1i32_sext(<vscale x 1 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv1i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf4 v10, v9
; CHECK-NEXT: vsra.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsra_wx_i8_nxv1i32_sext(<vscale x 1 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv1i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf8 v10, v9
; CHECK-NEXT: vsra.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) { define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv1i32_sext: ; CHECK-LABEL: vnsra_wi_i32_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
Show All 26 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64> %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb %x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y ret <vscale x 2 x i32> %y
} }
define <vscale x 2 x i32> @vnsra_wx_i16_nxv2i32_sext(<vscale x 2 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv2i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsext.vf4 v12, v10
; CHECK-NEXT: vsra.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsra_wx_i8_nxv2i32_sext(<vscale x 2 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv2i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsext.vf8 v12, v10
; CHECK-NEXT: vsra.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) { define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv2i32_sext: ; CHECK-LABEL: vnsra_wi_i32_nxv2i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64> %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb %x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y ret <vscale x 4 x i32> %y
} }
define <vscale x 4 x i32> @vnsra_wx_i16_nxv4i32_sext(<vscale x 4 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv4i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsext.vf4 v16, v12
; CHECK-NEXT: vsra.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsra_wx_i8_nxv4i32_sext(<vscale x 4 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv4i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsext.vf8 v16, v12
; CHECK-NEXT: vsra.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) { define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv4i32_sext: ; CHECK-LABEL: vnsra_wi_i32_nxv4i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb %x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 8 x i32> @vnsra_wx_i16_nxv8i32_sext(<vscale x 8 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv8i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf4 v24, v16
; CHECK-NEXT: vsra.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsra_wx_i8_nxv8i32_sext(<vscale x 8 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv8i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf8 v24, v16
; CHECK-NEXT: vsra.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) { define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv8i32_sext: ; CHECK-LABEL: vnsra_wi_i32_nxv8i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
Show All 25 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64> %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb %x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y ret <vscale x 1 x i32> %y
} }
define <vscale x 1 x i32> @vnsra_wx_i16_nxv1i32_zext(<vscale x 1 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv1i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsra.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsra_wx_i8_nxv1i32_zext(<vscale x 1 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv1i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsra.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
%x = ashr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) { define <vscale x 1 x i32> @vnsra_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv1i32_zext: ; CHECK-LABEL: vnsra_wi_i32_nxv1i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
Show All 26 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64> %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb %x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y ret <vscale x 2 x i32> %y
} }
define <vscale x 2 x i32> @vnsra_wx_i16_nxv2i32_zext(<vscale x 2 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv2i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf4 v12, v10
; CHECK-NEXT: vsra.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsra_wx_i8_nxv2i32_zext(<vscale x 2 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv2i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf8 v12, v10
; CHECK-NEXT: vsra.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
%x = ashr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) { define <vscale x 2 x i32> @vnsra_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv2i32_zext: ; CHECK-LABEL: vnsra_wi_i32_nxv2i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64> %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb %x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y ret <vscale x 4 x i32> %y
} }
define <vscale x 4 x i32> @vnsra_wx_i16_nxv4i32_zext(<vscale x 4 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv4i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vzext.vf4 v16, v12
; CHECK-NEXT: vsra.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsra_wx_i8_nxv4i32_zext(<vscale x 4 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv4i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vzext.vf8 v16, v12
; CHECK-NEXT: vsra.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
%x = ashr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) { define <vscale x 4 x i32> @vnsra_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv4i32_zext: ; CHECK-LABEL: vnsra_wi_i32_nxv4i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb %x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 8 x i32> @vnsra_wx_i16_nxv8i32_zext(<vscale x 8 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsra_wx_i16_nxv8i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vzext.vf4 v24, v16
; CHECK-NEXT: vsra.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsra_wx_i8_nxv8i32_zext(<vscale x 8 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsra_wx_i8_nxv8i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vzext.vf8 v24, v16
; CHECK-NEXT: vsra.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) { define <vscale x 8 x i32> @vnsra_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsra_wi_i32_nxv8i32_zext: ; CHECK-LABEL: vnsra_wi_i32_nxv8i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = ashr <vscale x 8 x i64> %va, %vb %x = ashr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }

llvm/test/CodeGen/RISCV/rvv/vnsrl-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \ ; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \ ; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i32> @vnsrl_wx_i64_nxv1i32(<vscale x 1 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma
; CHECK-NEXT: vsrl.vx v8, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 1 x i64> %head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
%x = lshr <vscale x 1 x i64> %va, %splat
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 2 x i32> @vnsrl_wx_i64_nxv2i32(<vscale x 2 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma
; CHECK-NEXT: vsrl.vx v10, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 2 x i64> %head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
%x = lshr <vscale x 2 x i64> %va, %splat
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 4 x i32> @vnsrl_wx_i64_nxv4i32(<vscale x 4 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma
; CHECK-NEXT: vsrl.vx v12, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 4 x i64> %head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
%x = lshr <vscale x 4 x i64> %va, %splat
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 8 x i32> @vnsrl_wx_i64_nxv8i32(<vscale x 8 x i64> %va, i64 %b) {
; CHECK-LABEL: vnsrl_wx_i64_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; CHECK-NEXT: vsrl.vx v16, v8, a0
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
%splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
%x = lshr <vscale x 8 x i64> %va, %splat
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) { define <vscale x 1 x i32> @vnsrl_wv_nxv1i32_sext(<vscale x 1 x i64> %va, <vscale x 1 x i32> %vb) {
; CHECK-LABEL: vnsrl_wv_nxv1i32_sext: ; CHECK-LABEL: vnsrl_wv_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wv v8, v8, v9 ; CHECK-NEXT: vnsrl.wv v8, v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64> %vc = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vc %x = lshr <vscale x 1 x i64> %va, %vc
Show All 10 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64> %vb = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb %x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y ret <vscale x 1 x i32> %y
} }
define <vscale x 1 x i32> @vnsrl_wx_i16_nxv1i32_sext(<vscale x 1 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv1i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf4 v10, v9
; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsrl_wx_i8_nxv1i32_sext(<vscale x 1 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv1i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf8 v10, v9
; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) { define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_sext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_sext: ; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
Show All 26 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64> %vb = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb %x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y ret <vscale x 2 x i32> %y
} }
define <vscale x 2 x i32> @vnsrl_wx_i16_nxv2i32_sext(<vscale x 2 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv2i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsext.vf4 v12, v10
; CHECK-NEXT: vsrl.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsrl_wx_i8_nxv2i32_sext(<vscale x 2 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv2i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsext.vf8 v12, v10
; CHECK-NEXT: vsrl.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) { define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_sext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_sext: ; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64> %vb = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb %x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y ret <vscale x 4 x i32> %y
} }
define <vscale x 4 x i32> @vnsrl_wx_i16_nxv4i32_sext(<vscale x 4 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv4i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsext.vf4 v16, v12
; CHECK-NEXT: vsrl.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsrl_wx_i8_nxv4i32_sext(<vscale x 4 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv4i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsext.vf8 v16, v12
; CHECK-NEXT: vsrl.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) { define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_sext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_sext: ; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb %x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 8 x i32> @vnsrl_wx_i16_nxv8i32_sext(<vscale x 8 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv8i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf4 v24, v16
; CHECK-NEXT: vsrl.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsrl_wx_i8_nxv8i32_sext(<vscale x 8 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv8i32_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf8 v24, v16
; CHECK-NEXT: vsrl.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) { define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_sext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_sext: ; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_sext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
Show All 25 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64> %vb = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb %x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32> %y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y ret <vscale x 1 x i32> %y
} }
define <vscale x 1 x i32> @vnsrl_wx_i16_nxv1i32_zext(<vscale x 1 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv1i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 1 x i16> %head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
%vb = zext <vscale x 1 x i16> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsrl_wx_i8_nxv1i32_zext(<vscale x 1 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv1i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v9, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma
; CHECK-NEXT: vsext.vf8 v10, v9
; CHECK-NEXT: vsrl.vv v8, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 1 x i8> %head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
%vb = sext <vscale x 1 x i8> %splat to <vscale x 1 x i64>
%x = lshr <vscale x 1 x i64> %va, %vb
%y = trunc <vscale x 1 x i64> %x to <vscale x 1 x i32>
ret <vscale x 1 x i32> %y
}
define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) { define <vscale x 1 x i32> @vnsrl_wi_i32_nxv1i32_zext(<vscale x 1 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_zext: ; CHECK-LABEL: vnsrl_wi_i32_nxv1i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v8, 15 ; CHECK-NEXT: vnsrl.wi v8, v8, 15
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 1 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
Show All 26 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64> %vb = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb %x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32> %y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y ret <vscale x 2 x i32> %y
} }
define <vscale x 2 x i32> @vnsrl_wx_i16_nxv2i32_zext(<vscale x 2 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv2i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vzext.vf4 v12, v10
; CHECK-NEXT: vsrl.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 2 x i16> %head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
%vb = zext <vscale x 2 x i16> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsrl_wx_i8_nxv2i32_zext(<vscale x 2 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv2i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma
; CHECK-NEXT: vsext.vf8 v12, v10
; CHECK-NEXT: vsrl.vv v10, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v10, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 2 x i8> %head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
%vb = sext <vscale x 2 x i8> %splat to <vscale x 2 x i64>
%x = lshr <vscale x 2 x i64> %va, %vb
%y = trunc <vscale x 2 x i64> %x to <vscale x 2 x i32>
ret <vscale x 2 x i32> %y
}
define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) { define <vscale x 2 x i32> @vnsrl_wi_i32_nxv2i32_zext(<vscale x 2 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_zext: ; CHECK-LABEL: vnsrl_wi_i32_nxv2i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
; CHECK-NEXT: vnsrl.wi v10, v8, 15 ; CHECK-NEXT: vnsrl.wi v10, v8, 15
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 2 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64> %vb = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb %x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32> %y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y ret <vscale x 4 x i32> %y
} }
define <vscale x 4 x i32> @vnsrl_wx_i16_nxv4i32_zext(<vscale x 4 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv4i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vzext.vf4 v16, v12
; CHECK-NEXT: vsrl.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 4 x i16> %head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
%vb = zext <vscale x 4 x i16> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsrl_wx_i8_nxv4i32_zext(<vscale x 4 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv4i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.x v12, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; CHECK-NEXT: vsext.vf8 v16, v12
; CHECK-NEXT: vsrl.vv v12, v8, v16
; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v12, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 4 x i8> %head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
%vb = sext <vscale x 4 x i8> %splat to <vscale x 4 x i64>
%x = lshr <vscale x 4 x i64> %va, %vb
%y = trunc <vscale x 4 x i64> %x to <vscale x 4 x i32>
ret <vscale x 4 x i32> %y
}
define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) { define <vscale x 4 x i32> @vnsrl_wi_i32_nxv4i32_zext(<vscale x 4 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_zext: ; CHECK-LABEL: vnsrl_wi_i32_nxv4i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vnsrl.wi v12, v8, 15 ; CHECK-NEXT: vnsrl.wi v12, v8, 15
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 4 x i32> poison, i32 15, i32 0
Show All 27 Lines; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb %x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }
define <vscale x 8 x i32> @vnsrl_wx_i16_nxv8i32_zext(<vscale x 8 x i64> %va, i16 %b) {
; CHECK-LABEL: vnsrl_wx_i16_nxv8i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vzext.vf4 v24, v16
; CHECK-NEXT: vsrl.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
%splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i16> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsrl_wx_i8_nxv8i32_zext(<vscale x 8 x i64> %va, i8 %b) {
; CHECK-LABEL: vnsrl_wx_i8_nxv8i32_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v16, a0
; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma
; CHECK-NEXT: vsext.vf8 v24, v16
; CHECK-NEXT: vsrl.vv v16, v8, v24
; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v16, 0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
%splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
%vb = sext <vscale x 8 x i8> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y
}
define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) { define <vscale x 8 x i32> @vnsrl_wi_i32_nxv8i32_zext(<vscale x 8 x i64> %va) {
; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_zext: ; CHECK-LABEL: vnsrl_wi_i32_nxv8i32_zext:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v16, v8, 15 ; CHECK-NEXT: vnsrl.wi v16, v8, 15
; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: vmv.v.v v8, v16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
%splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
%vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64> %vb = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
%x = lshr <vscale x 8 x i64> %va, %vb %x = lshr <vscale x 8 x i64> %va, %vb
%y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32> %y = trunc <vscale x 8 x i64> %x to <vscale x 8 x i32>
ret <vscale x 8 x i32> %y ret <vscale x 8 x i32> %y
} }