DAG: Implement soften float for ffrexp

[arsenm]

Summary

Fixes #63661

[alexfh]

Thanks for the quick fix! However, I'm not convinced this is a trivial fix for https://github.com/llvm/llvm-project/issues/63661, thus it may introduce other problems and make reverting to a known good state even more complex. As I mentioned on https://reviews.llvm.org/rG003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d#1223579, I'd prefer a revert to green before this fix gets tested and the commits starting from 003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d are recommitted.

[raj.khem]

In D154555#4475661, @alexfh wrote:

Thanks for the quick fix! However, I'm not convinced this is a trivial fix for https://github.com/llvm/llvm-project/issues/63661, thus it may introduce other problems and make reverting to a known good state even more complex. As I mentioned on https://reviews.llvm.org/rG003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d#1223579, I'd prefer a revert to green before this fix gets tested and the commits starting from 003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d are recommitted.

Wanted to note that this fixed boost issue on rv64 btw.

[arsenm]

In D154555#4475661, @alexfh wrote:

Thanks for the quick fix! However, I'm not convinced this is a trivial fix for https://github.com/llvm/llvm-project/issues/63661, thus it may introduce other problems and make reverting to a known good state even more complex. As I mentioned on https://reviews.llvm.org/rG003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d#1223579, I'd prefer a revert to green before this fix gets tested and the commits starting from 003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d are recommitted.

This is a trivial patch extending new functionality to just another case. The revert will be highly disruptive to my downstream uses that already exist and I will not be doing it. There is absolutely no reason to revert 003b58f65bdd5d9c7d0c1b355566c9ef430c0e7d. You could make an argument for reverting b15bf305ca3e9ce63aaef7247d32fb3a75174531, but that's more trouble than it's worth given here is the patch

[alexfh]

FWIW, the clang crash is gone with this patch. I'm trying to verify the other problem (https://reviews.llvm.org/rGb15bf305ca3e9ce63aaef7247d32fb3a75174531#1223188).

[alexfh]

In D154555#4475690, @alexfh wrote:

FWIW, the clang crash is gone with this patch. I'm trying to verify the other problem (https://reviews.llvm.org/rGb15bf305ca3e9ce63aaef7247d32fb3a75174531#1223188).

And unfortunately, this patch doesn't fix the problem @bgraur mentioned in https://reviews.llvm.org/rGb15bf305ca3e9ce63aaef7247d32fb3a75174531#1223188.

[alexfh]

LG based on my previous comment and the assertion that this is a "trivial fix".

[arsenm]

e8ed6e35bdea7f8e54f0018309bc3d0181f01ab5

llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp

#endif
     case ISD::FP16_TO_FP:  R = SoftenFloatRes_FP16_TO_FP(N); break;
     case ISD::BF16_TO_FP:  R = SoftenFloatRes_BF16_TO_FP(N); break;
     case ISD::STRICT_FPOW:
     case ISD::FPOW:        R = SoftenFloatRes_FPOW(N); break;
     case ISD::STRICT_FPOWI:
     case ISD::FPOWI:
     case ISD::FLDEXP:
     case ISD::STRICT_FLDEXP: R = SoftenFloatRes_ExpOp(N); break;
+    case ISD::FFREXP:
+      R = SoftenFloatRes_FFREXP(N);
+      break;
     case ISD::STRICT_FREM:
     case ISD::FREM:        R = SoftenFloatRes_FREM(N); break;
     case ISD::STRICT_FRINT:
     case ISD::FRINT:       R = SoftenFloatRes_FRINT(N); break;
     case ISD::STRICT_FROUND:
     case ISD::FROUND:      R = SoftenFloatRes_FROUND(N); break;
     case ISD::STRICT_FROUNDEVEN:
     case ISD::FROUNDEVEN:  R = SoftenFloatRes_FROUNDEVEN(N); break;
SDValue DAGTypeLegalizer::SoftenFloatRes_ExpOp(SDNode *N) {
   std::pair<SDValue, SDValue> Tmp = TLI.makeLibCall(DAG, LC, NVT, Ops,
                                                     CallOptions, SDLoc(N),
                                                     Chain);
   if (IsStrict)
     ReplaceValueWith(SDValue(N, 1), Tmp.second);
   return Tmp.first;
 }
 
+SDValue DAGTypeLegalizer::SoftenFloatRes_FFREXP(SDNode *N) {
+  assert(!N->isStrictFPOpcode() && "strictfp not implemented for frexp");
+  EVT VT0 = N->getValueType(0);
+  EVT VT1 = N->getValueType(1);
+  RTLIB::Libcall LC = RTLIB::getFREXP(VT0);
+
+  if (DAG.getLibInfo().getIntSize() != VT1.getSizeInBits()) {
+    // If the exponent does not match with sizeof(int) a libcall would use the
+    // wrong type for the argument.
+    // TODO: Should be able to handle mismatches.
+    DAG.getContext()->emitError("ffrexp exponent does not match sizeof(int)");
+    return DAG.getUNDEF(N->getValueType(0));
+  }
+
+  EVT NVT0 = TLI.getTypeToTransformTo(*DAG.getContext(), VT0);
+  SDValue StackSlot = DAG.CreateStackTemporary(VT1);
+
+  SDLoc DL(N);
+
+  TargetLowering::MakeLibCallOptions CallOptions;
+  SDValue Ops[2] = {GetSoftenedFloat(N->getOperand(0)), StackSlot};
+  EVT OpsVT[2] = {VT0, StackSlot.getValueType()};
+
+  // TODO: setTypeListBeforeSoften can't properly express multiple return types,
+  // but we only really need to handle the 0th one for softening anyway.
+  CallOptions.setTypeListBeforeSoften({OpsVT}, VT0, true);
+
+  auto [ReturnVal, Chain] = TLI.makeLibCall(DAG, LC, NVT0, Ops, CallOptions, DL,
+                                            /*Chain=*/SDValue());
+  int FrameIdx = cast<FrameIndexSDNode>(StackSlot)->getIndex();
+  auto PtrInfo =
+      MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
+
+  SDValue LoadExp = DAG.getLoad(VT1, DL, Chain, StackSlot, PtrInfo);
+
+  ReplaceValueWith(SDValue(N, 1), LoadExp);
+  return ReturnVal;
+}
+
 SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
   return SoftenFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
                                                RTLIB::REM_F32,
                                                RTLIB::REM_F64,
                                                RTLIB::REM_F80,
                                                RTLIB::REM_F128,
                                                RTLIB::REM_PPCF128));
 }

llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

private:
   SDValue SoftenFloatRes_FNEARBYINT(SDNode *N);
   SDValue SoftenFloatRes_FNEG(SDNode *N);
   SDValue SoftenFloatRes_FP_EXTEND(SDNode *N);
   SDValue SoftenFloatRes_FP16_TO_FP(SDNode *N);
   SDValue SoftenFloatRes_BF16_TO_FP(SDNode *N);
   SDValue SoftenFloatRes_FP_ROUND(SDNode *N);
   SDValue SoftenFloatRes_FPOW(SDNode *N);
   SDValue SoftenFloatRes_ExpOp(SDNode *N);
+  SDValue SoftenFloatRes_FFREXP(SDNode *N);
   SDValue SoftenFloatRes_FREEZE(SDNode *N);
   SDValue SoftenFloatRes_FREM(SDNode *N);
   SDValue SoftenFloatRes_FRINT(SDNode *N);
   SDValue SoftenFloatRes_FROUND(SDNode *N);
   SDValue SoftenFloatRes_FROUNDEVEN(SDNode *N);
   SDValue SoftenFloatRes_FSIN(SDNode *N);
   SDValue SoftenFloatRes_FSQRT(SDNode *N);
   SDValue SoftenFloatRes_FSUB(SDNode *N);

llvm/test/CodeGen/RISCV/llvm.frexp.ll

 ; }
 
 ; define <2 x i32> @test_frexp_v2f64_v2i32_only_use_exp(<2 x double> %a) nounwind {
 ;   %result = call { <2 x double>, <2 x i32> } @llvm.frexp.v2f64.v2i32(<2 x double> %a)
 ;   %result.1 = extractvalue { <2 x double>, <2 x i32> } %result, 1
 ;   ret <2 x i32> %result.1
 ; }
 
-; FIXME: fp128 softening crashes
-; define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
-;   %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
-;   ret { fp128, i32 } %result
-; }
+define { fp128, i32 } @test_frexp_f128_i32(fp128 %a) nounwind {
+; RV32IFD-LABEL: test_frexp_f128_i32:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -48
+; RV32IFD-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    lw a3, 0(a1)
+; RV32IFD-NEXT:    lw a2, 4(a1)
+; RV32IFD-NEXT:    lw a4, 8(a1)
+; RV32IFD-NEXT:    lw a1, 12(a1)
+; RV32IFD-NEXT:    mv s0, a0
+; RV32IFD-NEXT:    sw a1, 12(sp)
+; RV32IFD-NEXT:    sw a4, 8(sp)
+; RV32IFD-NEXT:    sw a2, 4(sp)
+; RV32IFD-NEXT:    addi a0, sp, 16
+; RV32IFD-NEXT:    mv a1, sp
+; RV32IFD-NEXT:    addi a2, sp, 36
+; RV32IFD-NEXT:    sw a3, 0(sp)
+; RV32IFD-NEXT:    call frexpl@plt
+; RV32IFD-NEXT:    lw a0, 36(sp)
+; RV32IFD-NEXT:    lw a1, 28(sp)
+; RV32IFD-NEXT:    lw a2, 24(sp)
+; RV32IFD-NEXT:    lw a3, 20(sp)
+; RV32IFD-NEXT:    lw a4, 16(sp)
+; RV32IFD-NEXT:    sw a1, 12(s0)
+; RV32IFD-NEXT:    sw a2, 8(s0)
+; RV32IFD-NEXT:    sw a3, 4(s0)
+; RV32IFD-NEXT:    sw a4, 0(s0)
+; RV32IFD-NEXT:    sw a0, 16(s0)
+; RV32IFD-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 48
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: test_frexp_f128_i32:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    addi sp, sp, -32
+; RV64IFD-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT:    mv a3, a2
+; RV64IFD-NEXT:    mv s0, a0
+; RV64IFD-NEXT:    addi a2, sp, 12
+; RV64IFD-NEXT:    mv a0, a1
+; RV64IFD-NEXT:    mv a1, a3
+; RV64IFD-NEXT:    call frexpl@plt
+; RV64IFD-NEXT:    lw a2, 12(sp)
+; RV64IFD-NEXT:    sd a1, 8(s0)
+; RV64IFD-NEXT:    sd a0, 0(s0)
+; RV64IFD-NEXT:    sw a2, 16(s0)
+; RV64IFD-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT:    addi sp, sp, 32
+; RV64IFD-NEXT:    ret
+;
+; RV32IZFINXZDINX-LABEL: test_frexp_f128_i32:
+; RV32IZFINXZDINX:       # %bb.0:
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, -48
+; RV32IZFINXZDINX-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    lw a3, 0(a1)
+; RV32IZFINXZDINX-NEXT:    lw a2, 4(a1)
+; RV32IZFINXZDINX-NEXT:    lw a4, 8(a1)
+; RV32IZFINXZDINX-NEXT:    lw a1, 12(a1)
+; RV32IZFINXZDINX-NEXT:    mv s0, a0
+; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT:    sw a4, 8(sp)
+; RV32IZFINXZDINX-NEXT:    sw a2, 4(sp)
+; RV32IZFINXZDINX-NEXT:    addi a0, sp, 16
+; RV32IZFINXZDINX-NEXT:    mv a1, sp
+; RV32IZFINXZDINX-NEXT:    addi a2, sp, 36
+; RV32IZFINXZDINX-NEXT:    sw a3, 0(sp)
+; RV32IZFINXZDINX-NEXT:    call frexpl@plt
+; RV32IZFINXZDINX-NEXT:    lw a0, 36(sp)
+; RV32IZFINXZDINX-NEXT:    lw a1, 28(sp)
+; RV32IZFINXZDINX-NEXT:    lw a2, 24(sp)
+; RV32IZFINXZDINX-NEXT:    lw a3, 20(sp)
+; RV32IZFINXZDINX-NEXT:    lw a4, 16(sp)
+; RV32IZFINXZDINX-NEXT:    sw a1, 12(s0)
+; RV32IZFINXZDINX-NEXT:    sw a2, 8(s0)
+; RV32IZFINXZDINX-NEXT:    sw a3, 4(s0)
+; RV32IZFINXZDINX-NEXT:    sw a4, 0(s0)
+; RV32IZFINXZDINX-NEXT:    sw a0, 16(s0)
+; RV32IZFINXZDINX-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, 48
+; RV32IZFINXZDINX-NEXT:    ret
+;
+; RV64IZFINXZDINX-LABEL: test_frexp_f128_i32:
+; RV64IZFINXZDINX:       # %bb.0:
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, -32
+; RV64IZFINXZDINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZFINXZDINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZFINXZDINX-NEXT:    mv a3, a2
+; RV64IZFINXZDINX-NEXT:    mv s0, a0
+; RV64IZFINXZDINX-NEXT:    addi a2, sp, 12
+; RV64IZFINXZDINX-NEXT:    mv a0, a1
+; RV64IZFINXZDINX-NEXT:    mv a1, a3
+; RV64IZFINXZDINX-NEXT:    call frexpl@plt
+; RV64IZFINXZDINX-NEXT:    lw a2, 12(sp)
+; RV64IZFINXZDINX-NEXT:    sd a1, 8(s0)
+; RV64IZFINXZDINX-NEXT:    sd a0, 0(s0)
+; RV64IZFINXZDINX-NEXT:    sw a2, 16(s0)
+; RV64IZFINXZDINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZFINXZDINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, 32
+; RV64IZFINXZDINX-NEXT:    ret
+  %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
+  ret { fp128, i32 } %result
+}
 
-; define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind {
-;   %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
-;   %result.0 = extractvalue { fp128, i32 } %result, 0
-;   ret fp128 %result.0
-; }
+define fp128 @test_frexp_f128_i32_only_use_fract(fp128 %a) nounwind {
+; RV32IFD-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -48
+; RV32IFD-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    lw a3, 0(a1)
+; RV32IFD-NEXT:    lw a2, 4(a1)
+; RV32IFD-NEXT:    lw a4, 8(a1)
+; RV32IFD-NEXT:    lw a1, 12(a1)
+; RV32IFD-NEXT:    mv s0, a0
+; RV32IFD-NEXT:    sw a1, 12(sp)
+; RV32IFD-NEXT:    sw a4, 8(sp)
+; RV32IFD-NEXT:    sw a2, 4(sp)
+; RV32IFD-NEXT:    addi a0, sp, 16
+; RV32IFD-NEXT:    mv a1, sp
+; RV32IFD-NEXT:    addi a2, sp, 36
+; RV32IFD-NEXT:    sw a3, 0(sp)
+; RV32IFD-NEXT:    call frexpl@plt
+; RV32IFD-NEXT:    lw a0, 28(sp)
+; RV32IFD-NEXT:    lw a1, 24(sp)
+; RV32IFD-NEXT:    lw a2, 20(sp)
+; RV32IFD-NEXT:    lw a3, 16(sp)
+; RV32IFD-NEXT:    sw a0, 12(s0)
+; RV32IFD-NEXT:    sw a1, 8(s0)
+; RV32IFD-NEXT:    sw a2, 4(s0)
+; RV32IFD-NEXT:    sw a3, 0(s0)
+; RV32IFD-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 48
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    addi sp, sp, -16
+; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT:    addi a2, sp, 4
+; RV64IFD-NEXT:    call frexpl@plt
+; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT:    addi sp, sp, 16
+; RV64IFD-NEXT:    ret
+;
+; RV32IZFINXZDINX-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV32IZFINXZDINX:       # %bb.0:
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, -48
+; RV32IZFINXZDINX-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    sw s0, 40(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    lw a3, 0(a1)
+; RV32IZFINXZDINX-NEXT:    lw a2, 4(a1)
+; RV32IZFINXZDINX-NEXT:    lw a4, 8(a1)
+; RV32IZFINXZDINX-NEXT:    lw a1, 12(a1)
+; RV32IZFINXZDINX-NEXT:    mv s0, a0
+; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT:    sw a4, 8(sp)
+; RV32IZFINXZDINX-NEXT:    sw a2, 4(sp)
+; RV32IZFINXZDINX-NEXT:    addi a0, sp, 16
+; RV32IZFINXZDINX-NEXT:    mv a1, sp
+; RV32IZFINXZDINX-NEXT:    addi a2, sp, 36
+; RV32IZFINXZDINX-NEXT:    sw a3, 0(sp)
+; RV32IZFINXZDINX-NEXT:    call frexpl@plt
+; RV32IZFINXZDINX-NEXT:    lw a0, 28(sp)
+; RV32IZFINXZDINX-NEXT:    lw a1, 24(sp)
+; RV32IZFINXZDINX-NEXT:    lw a2, 20(sp)
+; RV32IZFINXZDINX-NEXT:    lw a3, 16(sp)
+; RV32IZFINXZDINX-NEXT:    sw a0, 12(s0)
+; RV32IZFINXZDINX-NEXT:    sw a1, 8(s0)
+; RV32IZFINXZDINX-NEXT:    sw a2, 4(s0)
+; RV32IZFINXZDINX-NEXT:    sw a3, 0(s0)
+; RV32IZFINXZDINX-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT:    lw s0, 40(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, 48
+; RV32IZFINXZDINX-NEXT:    ret
+;
+; RV64IZFINXZDINX-LABEL: test_frexp_f128_i32_only_use_fract:
+; RV64IZFINXZDINX:       # %bb.0:
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
+; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINXZDINX-NEXT:    addi a2, sp, 4
+; RV64IZFINXZDINX-NEXT:    call frexpl@plt
+; RV64IZFINXZDINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, 16
+; RV64IZFINXZDINX-NEXT:    ret
+  %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
+  %result.0 = extractvalue { fp128, i32 } %result, 0
+  ret fp128 %result.0
+}
 
-; define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind {
-;   %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
-;   %result.0 = extractvalue { fp128, i32 } %result, 1
-;   ret i32 %result.0
-; }
+define i32 @test_frexp_f128_i32_only_use_exp(fp128 %a) nounwind {
+; RV32IFD-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV32IFD:       # %bb.0:
+; RV32IFD-NEXT:    addi sp, sp, -48
+; RV32IFD-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IFD-NEXT:    lw a3, 0(a0)
+; RV32IFD-NEXT:    lw a1, 4(a0)
+; RV32IFD-NEXT:    lw a2, 8(a0)
+; RV32IFD-NEXT:    lw a0, 12(a0)
+; RV32IFD-NEXT:    sw a0, 20(sp)
+; RV32IFD-NEXT:    sw a2, 16(sp)
+; RV32IFD-NEXT:    sw a1, 12(sp)
+; RV32IFD-NEXT:    addi a0, sp, 24
+; RV32IFD-NEXT:    addi a1, sp, 8
+; RV32IFD-NEXT:    addi a2, sp, 40
+; RV32IFD-NEXT:    sw a3, 8(sp)
+; RV32IFD-NEXT:    call frexpl@plt
+; RV32IFD-NEXT:    lw a0, 40(sp)
+; RV32IFD-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IFD-NEXT:    addi sp, sp, 48
+; RV32IFD-NEXT:    ret
+;
+; RV64IFD-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV64IFD:       # %bb.0:
+; RV64IFD-NEXT:    addi sp, sp, -16
+; RV64IFD-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IFD-NEXT:    addi a2, sp, 4
+; RV64IFD-NEXT:    call frexpl@plt
+; RV64IFD-NEXT:    lw a0, 4(sp)
+; RV64IFD-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IFD-NEXT:    addi sp, sp, 16
+; RV64IFD-NEXT:    ret
+;
+; RV32IZFINXZDINX-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV32IZFINXZDINX:       # %bb.0:
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, -48
+; RV32IZFINXZDINX-NEXT:    sw ra, 44(sp) # 4-byte Folded Spill
+; RV32IZFINXZDINX-NEXT:    lw a3, 0(a0)
+; RV32IZFINXZDINX-NEXT:    lw a1, 4(a0)
+; RV32IZFINXZDINX-NEXT:    lw a2, 8(a0)
+; RV32IZFINXZDINX-NEXT:    lw a0, 12(a0)
+; RV32IZFINXZDINX-NEXT:    sw a0, 20(sp)
+; RV32IZFINXZDINX-NEXT:    sw a2, 16(sp)
+; RV32IZFINXZDINX-NEXT:    sw a1, 12(sp)
+; RV32IZFINXZDINX-NEXT:    addi a0, sp, 24
+; RV32IZFINXZDINX-NEXT:    addi a1, sp, 8
+; RV32IZFINXZDINX-NEXT:    addi a2, sp, 40
+; RV32IZFINXZDINX-NEXT:    sw a3, 8(sp)
+; RV32IZFINXZDINX-NEXT:    call frexpl@plt
+; RV32IZFINXZDINX-NEXT:    lw a0, 40(sp)
+; RV32IZFINXZDINX-NEXT:    lw ra, 44(sp) # 4-byte Folded Reload
+; RV32IZFINXZDINX-NEXT:    addi sp, sp, 48
+; RV32IZFINXZDINX-NEXT:    ret
+;
+; RV64IZFINXZDINX-LABEL: test_frexp_f128_i32_only_use_exp:
+; RV64IZFINXZDINX:       # %bb.0:
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, -16
+; RV64IZFINXZDINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZFINXZDINX-NEXT:    addi a2, sp, 4
+; RV64IZFINXZDINX-NEXT:    call frexpl@plt
+; RV64IZFINXZDINX-NEXT:    lw a0, 4(sp)
+; RV64IZFINXZDINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZFINXZDINX-NEXT:    addi sp, sp, 16
+; RV64IZFINXZDINX-NEXT:    ret
+  %result = call { fp128, i32 } @llvm.frexp.f128.i32(fp128 %a)
+  %result.0 = extractvalue { fp128, i32 } %result, 1
+  ret i32 %result.0
+}
 
 declare { float, i32 } @llvm.frexp.f32.i32(float) #0
 declare { <2 x float>, <2 x i32> } @llvm.frexp.v2f32.v2i32(<2 x float>) #0
 declare { <4 x float>, <4 x i32> } @llvm.frexp.v4f32.v4i32(<4 x float>) #0
 
 declare { half, i32 } @llvm.frexp.f16.i32(half) #0
 declare { <2 x half>, <2 x i32> } @llvm.frexp.v2f16.v2i32(<2 x half>) #0