[AArch64] Replace OperandMatchResultTy with ParseStatus (NFC)

[barannikov88]

Summary

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:

return Error(L, "msg");

when with MatchOperandResultTy it had to be:

Error(L, "msg");
return MatchOperand_ParseFail;

It also has more appropriate name since parse* methods are not only for
parsing operands.

[barannikov88]

clang-format one line

[barannikov88]

Rebase

[david-arm]

LGTM! Looks like a nice cleanup and it has removed over a 100 lines of code. :)

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

 /// @name Auto-generated Match Functions
 /// {
 
 #define GET_ASSEMBLER_HEADER
 #include "AArch64GenAsmMatcher.inc"
 
   /// }
 
-  OperandMatchResultTy tryParseScalarRegister(MCRegister &Reg);
-  OperandMatchResultTy tryParseVectorRegister(MCRegister &Reg, StringRef &Kind,
-                                              RegKind MatchKind);
-  OperandMatchResultTy tryParseMatrixRegister(OperandVector &Operands);
-  OperandMatchResultTy tryParseSVCR(OperandVector &Operands);
-  OperandMatchResultTy tryParseOptionalShiftExtend(OperandVector &Operands);
-  OperandMatchResultTy tryParseBarrierOperand(OperandVector &Operands);
-  OperandMatchResultTy tryParseBarriernXSOperand(OperandVector &Operands);
-  OperandMatchResultTy tryParseSysReg(OperandVector &Operands);
-  OperandMatchResultTy tryParseSysCROperand(OperandVector &Operands);
+  ParseStatus tryParseScalarRegister(MCRegister &Reg);
+  ParseStatus tryParseVectorRegister(MCRegister &Reg, StringRef &Kind,
+  ParseStatus tryParseMatrixRegister(OperandVector &Operands);
+  ParseStatus tryParseSVCR(OperandVector &Operands);
+  ParseStatus tryParseOptionalShiftExtend(OperandVector &Operands);
+  ParseStatus tryParseBarrierOperand(OperandVector &Operands);
+  ParseStatus tryParseBarriernXSOperand(OperandVector &Operands);
+  ParseStatus tryParseSysReg(OperandVector &Operands);
+  ParseStatus tryParseSysCROperand(OperandVector &Operands);
   template <bool IsSVEPrefetch = false>
-  OperandMatchResultTy tryParsePrefetch(OperandVector &Operands);
-  OperandMatchResultTy tryParseRPRFMOperand(OperandVector &Operands);
-  OperandMatchResultTy tryParsePSBHint(OperandVector &Operands);
-  OperandMatchResultTy tryParseBTIHint(OperandVector &Operands);
-  OperandMatchResultTy tryParseAdrpLabel(OperandVector &Operands);
-  OperandMatchResultTy tryParseAdrLabel(OperandVector &Operands);
-  template<bool AddFPZeroAsLiteral>
-  OperandMatchResultTy tryParseFPImm(OperandVector &Operands);
-  OperandMatchResultTy tryParseImmWithOptionalShift(OperandVector &Operands);
-  OperandMatchResultTy tryParseGPR64sp0Operand(OperandVector &Operands);
+  ParseStatus tryParsePrefetch(OperandVector &Operands);
+  ParseStatus tryParseRPRFMOperand(OperandVector &Operands);
+  ParseStatus tryParsePSBHint(OperandVector &Operands);
+  ParseStatus tryParseBTIHint(OperandVector &Operands);
+  ParseStatus tryParseAdrpLabel(OperandVector &Operands);
+  ParseStatus tryParseAdrLabel(OperandVector &Operands);
+  template <bool AddFPZeroAsLiteral>
+  ParseStatus tryParseFPImm(OperandVector &Operands);
+  ParseStatus tryParseImmWithOptionalShift(OperandVector &Operands);
+  ParseStatus tryParseGPR64sp0Operand(OperandVector &Operands);
   bool tryParseNeonVectorRegister(OperandVector &Operands);
-  OperandMatchResultTy tryParseVectorIndex(OperandVector &Operands);
-  OperandMatchResultTy tryParseGPRSeqPair(OperandVector &Operands);
-  OperandMatchResultTy tryParseSyspXzrPair(OperandVector &Operands);
+  ParseStatus tryParseVectorIndex(OperandVector &Operands);
+  ParseStatus tryParseGPRSeqPair(OperandVector &Operands);
+  ParseStatus tryParseSyspXzrPair(OperandVector &Operands);
   template <bool ParseShiftExtend,
             RegConstraintEqualityTy EqTy = RegConstraintEqualityTy::EqualsReg>
-  OperandMatchResultTy tryParseGPROperand(OperandVector &Operands);
-  OperandMatchResultTy tryParseZTOperand(OperandVector &Operands);
+  ParseStatus tryParseGPROperand(OperandVector &Operands);
+  ParseStatus tryParseZTOperand(OperandVector &Operands);
   template <bool ParseShiftExtend, bool ParseSuffix>
-  OperandMatchResultTy tryParseSVEDataVector(OperandVector &Operands);
+  ParseStatus tryParseSVEDataVector(OperandVector &Operands);
   template <RegKind RK>
-  OperandMatchResultTy tryParseSVEPredicateVector(OperandVector &Operands);
+  ParseStatus tryParseSVEPredicateVector(OperandVector &Operands);
   template <RegKind VectorKind>
-  OperandMatchResultTy tryParseVectorList(OperandVector &Operands,
-                                          bool ExpectMatch = false);
-  OperandMatchResultTy tryParseMatrixTileList(OperandVector &Operands);
-  OperandMatchResultTy tryParseSVEPattern(OperandVector &Operands);
-  OperandMatchResultTy tryParseSVEVecLenSpecifier(OperandVector &Operands);
-  OperandMatchResultTy tryParseGPR64x8(OperandVector &Operands);
-  OperandMatchResultTy tryParseImmRange(OperandVector &Operands);
+  ParseStatus tryParseVectorList(OperandVector &Operands,
+  ParseStatus tryParseMatrixTileList(OperandVector &Operands);
+  ParseStatus tryParseSVEPattern(OperandVector &Operands);
+  ParseStatus tryParseSVEVecLenSpecifier(OperandVector &Operands);
+  ParseStatus tryParseGPR64x8(OperandVector &Operands);
+  ParseStatus tryParseImmRange(OperandVector &Operands);
 
 public:
   enum AArch64MatchResultTy {
     Match_InvalidSuffix = FIRST_TARGET_MATCH_RESULT_TY,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "AArch64GenAsmMatcher.inc"
   };
   bool IsILP32;
unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
   case RegKind::NeonVector:
   case RegKind::SVEDataVector:
     return 32;
   case RegKind::Matrix:
   case RegKind::SVEPredicateVector:
   case RegKind::SVEPredicateAsCounter:
     return 16;
   case RegKind::LookupTable:
     return 1;
   }
   llvm_unreachable("Unsupported RegKind");
 }
 
 /// tryParseScalarRegister - Try to parse a register name. The token must be an
 /// Identifier when called, and if it is a register name the token is eaten and
 /// the register is added to the operand list.
-OperandMatchResultTy
-AArch64AsmParser::tryParseScalarRegister(MCRegister &RegNum) {
+ParseStatus AArch64AsmParser::tryParseScalarRegister(MCRegister &RegNum) {
   const AsmToken &Tok = getTok();
   if (Tok.isNot(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   std::string lowerCase = Tok.getString().lower();
   unsigned Reg = matchRegisterNameAlias(lowerCase, RegKind::Scalar);
   if (Reg == 0)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   RegNum = Reg;
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseSysCROperand - Try to parse a system instruction CR operand name.
-OperandMatchResultTy
-AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) {
   SMLoc S = getLoc();
 
-  if (getTok().isNot(AsmToken::Identifier)) {
-    Error(S, "Expected cN operand where 0 <= N <= 15");
-    return MatchOperand_ParseFail;
-  }
+  if (getTok().isNot(AsmToken::Identifier))
+    return Error(S, "Expected cN operand where 0 <= N <= 15");
 
   StringRef Tok = getTok().getIdentifier();
-  if (Tok[0] != 'c' && Tok[0] != 'C') {
-    Error(S, "Expected cN operand where 0 <= N <= 15");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok[0] != 'c' && Tok[0] != 'C')
+    return Error(S, "Expected cN operand where 0 <= N <= 15");
 
   uint32_t CRNum;
   bool BadNum = Tok.drop_front().getAsInteger(10, CRNum);
-  if (BadNum || CRNum > 15) {
-    Error(S, "Expected cN operand where 0 <= N <= 15");
-    return MatchOperand_ParseFail;
-  }
+  if (BadNum || CRNum > 15)
+    return Error(S, "Expected cN operand where 0 <= N <= 15");
 
   Lex(); // Eat identifier token.
   Operands.push_back(
       AArch64Operand::CreateSysCR(CRNum, S, getLoc(), getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 // Either an identifier for named values or a 6-bit immediate.
-OperandMatchResultTy
-AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseRPRFMOperand(OperandVector &Operands) {
   SMLoc S = getLoc();
   const AsmToken &Tok = getTok();
 
   unsigned MaxVal = 63;
 
   // Immediate case, with optional leading hash:
   if (parseOptionalToken(AsmToken::Hash) ||
       Tok.is(AsmToken::Integer)) {
     const MCExpr *ImmVal;
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      TokError("immediate value expected for prefetch operand");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return TokError("immediate value expected for prefetch operand");
     unsigned prfop = MCE->getValue();
-    if (prfop > MaxVal) {
-      TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
+    if (prfop > MaxVal)
+      return TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
                       "] expected");
-      return MatchOperand_ParseFail;
-    }
 
     auto RPRFM = AArch64RPRFM::lookupRPRFMByEncoding(MCE->getValue());
     Operands.push_back(AArch64Operand::CreatePrefetch(
         prfop, RPRFM ? RPRFM->Name : "", S, getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("prefetch hint expected");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("prefetch hint expected");
 
   auto RPRFM = AArch64RPRFM::lookupRPRFMByName(Tok.getString());
-  if (!RPRFM) {
-    TokError("prefetch hint expected");
-    return MatchOperand_ParseFail;
-  }
+  if (!RPRFM)
+    return TokError("prefetch hint expected");
 
   Operands.push_back(AArch64Operand::CreatePrefetch(
       RPRFM->Encoding, Tok.getString(), S, getContext()));
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParsePrefetch - Try to parse a prefetch operand.
 template <bool IsSVEPrefetch>
-OperandMatchResultTy
-AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
   SMLoc S = getLoc();
   const AsmToken &Tok = getTok();
 
   auto LookupByName = [](StringRef N) {
     if (IsSVEPrefetch) {
       if (auto Res = AArch64SVEPRFM::lookupSVEPRFMByName(N))
         return std::optional<unsigned>(Res->Encoding);
     } else if (auto Res = AArch64PRFM::lookupPRFMByName(N))
ParseStatus AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) {
   unsigned MaxVal = IsSVEPrefetch ? 15 : 31;
 
   // Either an identifier for named values or a 5-bit immediate.
   // Eat optional hash.
   if (parseOptionalToken(AsmToken::Hash) ||
       Tok.is(AsmToken::Integer)) {
     const MCExpr *ImmVal;
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      TokError("immediate value expected for prefetch operand");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return TokError("immediate value expected for prefetch operand");
     unsigned prfop = MCE->getValue();
-    if (prfop > MaxVal) {
-      TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
+    if (prfop > MaxVal)
+      return TokError("prefetch operand out of range, [0," + utostr(MaxVal) +
                       "] expected");
-      return MatchOperand_ParseFail;
-    }
 
     auto PRFM = LookupByEncoding(MCE->getValue());
     Operands.push_back(AArch64Operand::CreatePrefetch(prfop, PRFM.value_or(""),
                                                       S, getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("prefetch hint expected");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("prefetch hint expected");
 
   auto PRFM = LookupByName(Tok.getString());
-  if (!PRFM) {
-    TokError("prefetch hint expected");
-    return MatchOperand_ParseFail;
-  }
+  if (!PRFM)
+    return TokError("prefetch hint expected");
 
   Operands.push_back(AArch64Operand::CreatePrefetch(
       *PRFM, Tok.getString(), S, getContext()));
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command
-OperandMatchResultTy
-AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) {
   SMLoc S = getLoc();
   const AsmToken &Tok = getTok();
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("invalid operand for instruction");
 
   auto PSB = AArch64PSBHint::lookupPSBByName(Tok.getString());
-  if (!PSB) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (!PSB)
+    return TokError("invalid operand for instruction");
 
   Operands.push_back(AArch64Operand::CreatePSBHint(
       PSB->Encoding, Tok.getString(), S, getContext()));
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseSyspXzrPair(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSyspXzrPair(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
 
   MCRegister RegNum;
 
   // The case where xzr, xzr is not present is handled by an InstAlias.
 
   auto RegTok = getTok(); // in case we need to backtrack
-  if (tryParseScalarRegister(RegNum) != MatchOperand_Success)
-    return MatchOperand_NoMatch;
+  if (!tryParseScalarRegister(RegNum).isSuccess())
+    return ParseStatus::NoMatch;
 
   if (RegNum != AArch64::XZR) {
     getLexer().UnLex(RegTok);
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
   }
 
   if (parseComma())
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
-  if (tryParseScalarRegister(RegNum) != MatchOperand_Success) {
-    TokError("expected register operand");
-    return MatchOperand_ParseFail;
-  }
+  if (!tryParseScalarRegister(RegNum).isSuccess())
+    return TokError("expected register operand");
 
-  if (RegNum != AArch64::XZR) {
-    TokError("xzr must be followed by xzr");
-    return MatchOperand_ParseFail;
-  }
+  if (RegNum != AArch64::XZR)
+    return TokError("xzr must be followed by xzr");
 
   // We need to push something, since we claim this is an operand in .td.
   // See also AArch64AsmParser::parseKeywordOperand.
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseBTIHint - Try to parse a BTI operand, mapped to Hint command
-OperandMatchResultTy
-AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseBTIHint(OperandVector &Operands) {
   SMLoc S = getLoc();
   const AsmToken &Tok = getTok();
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("invalid operand for instruction");
 
   auto BTI = AArch64BTIHint::lookupBTIByName(Tok.getString());
-  if (!BTI) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (!BTI)
+    return TokError("invalid operand for instruction");
 
   Operands.push_back(AArch64Operand::CreateBTIHint(
       BTI->Encoding, Tok.getString(), S, getContext()));
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseAdrpLabel - Parse and validate a source label for the ADRP
 /// instruction.
-OperandMatchResultTy
-AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Expr = nullptr;
 
   if (getTok().is(AsmToken::Hash)) {
     Lex(); // Eat hash token.
   }
 
   if (parseSymbolicImmVal(Expr))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   AArch64MCExpr::VariantKind ELFRefKind;
   MCSymbolRefExpr::VariantKind DarwinRefKind;
   int64_t Addend;
   if (classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
     if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
         ELFRefKind == AArch64MCExpr::VK_INVALID) {
       // No modifier was specified at all; this is the syntax for an ELF basic
       // ADRP relocation (unfortunately).
       Expr =
           AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS_PAGE, getContext());
     } else if ((DarwinRefKind == MCSymbolRefExpr::VK_GOTPAGE ||
                 DarwinRefKind == MCSymbolRefExpr::VK_TLVPPAGE) &&
                Addend != 0) {
-      Error(S, "gotpage label reference not allowed an addend");
-      return MatchOperand_ParseFail;
+      return Error(S, "gotpage label reference not allowed an addend");
     } else if (DarwinRefKind != MCSymbolRefExpr::VK_PAGE &&
                DarwinRefKind != MCSymbolRefExpr::VK_GOTPAGE &&
                DarwinRefKind != MCSymbolRefExpr::VK_TLVPPAGE &&
                ELFRefKind != AArch64MCExpr::VK_ABS_PAGE_NC &&
                ELFRefKind != AArch64MCExpr::VK_GOT_PAGE &&
                ELFRefKind != AArch64MCExpr::VK_GOT_PAGE_LO15 &&
                ELFRefKind != AArch64MCExpr::VK_GOTTPREL_PAGE &&
                ELFRefKind != AArch64MCExpr::VK_TLSDESC_PAGE) {
       // The operand must be an @page or @gotpage qualified symbolref.
-      Error(S, "page or gotpage label reference expected");
-      return MatchOperand_ParseFail;
+      return Error(S, "page or gotpage label reference expected");
     }
   }
 
   // We have either a label reference possibly with addend or an immediate. The
   // addend is a raw value here. The linker will adjust it to only reference the
   // page.
   SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
   Operands.push_back(AArch64Operand::CreateImm(Expr, S, E, getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseAdrLabel - Parse and validate a source label for the ADR
 /// instruction.
-OperandMatchResultTy
-AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) {
   SMLoc S = getLoc();
   const MCExpr *Expr = nullptr;
 
   // Leave anything with a bracket to the default for SVE
   if (getTok().is(AsmToken::LBrac))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   if (getTok().is(AsmToken::Hash))
     Lex(); // Eat hash token.
 
   if (parseSymbolicImmVal(Expr))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   AArch64MCExpr::VariantKind ELFRefKind;
   MCSymbolRefExpr::VariantKind DarwinRefKind;
   int64_t Addend;
   if (classifySymbolRef(Expr, ELFRefKind, DarwinRefKind, Addend)) {
     if (DarwinRefKind == MCSymbolRefExpr::VK_None &&
         ELFRefKind == AArch64MCExpr::VK_INVALID) {
       // No modifier was specified at all; this is the syntax for an ELF basic
       // ADR relocation (unfortunately).
       Expr = AArch64MCExpr::create(Expr, AArch64MCExpr::VK_ABS, getContext());
     } else {
-      Error(S, "unexpected adr label");
-      return MatchOperand_ParseFail;
+      return Error(S, "unexpected adr label");
     }
   }
 
   SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
   Operands.push_back(AArch64Operand::CreateImm(Expr, S, E, getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseFPImm - A floating point immediate expression operand.
-template<bool AddFPZeroAsLiteral>
-OperandMatchResultTy
-AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
+template <bool AddFPZeroAsLiteral>
+ParseStatus AArch64AsmParser::tryParseFPImm(OperandVector &Operands) {
   SMLoc S = getLoc();
 
   bool Hash = parseOptionalToken(AsmToken::Hash);
 
   // Handle negation, as that still comes through as a separate token.
   bool isNegative = parseOptionalToken(AsmToken::Minus);
 
   const AsmToken &Tok = getTok();
   if (!Tok.is(AsmToken::Real) && !Tok.is(AsmToken::Integer)) {
     if (!Hash)
-      return MatchOperand_NoMatch;
-    TokError("invalid floating point immediate");
-    return MatchOperand_ParseFail;
+      return ParseStatus::NoMatch;
+    return TokError("invalid floating point immediate");
   }
 
   // Parse hexadecimal representation.
   if (Tok.is(AsmToken::Integer) && Tok.getString().startswith("0x")) {
-    if (Tok.getIntVal() > 255 || isNegative) {
-      TokError("encoded floating point value out of range");
-      return MatchOperand_ParseFail;
-    }
+    if (Tok.getIntVal() > 255 || isNegative)
+      return TokError("encoded floating point value out of range");
 
     APFloat F((double)AArch64_AM::getFPImmFloat(Tok.getIntVal()));
     Operands.push_back(
         AArch64Operand::CreateFPImm(F, true, S, getContext()));
   } else {
     // Parse FP representation.
     APFloat RealVal(APFloat::IEEEdouble());
     auto StatusOrErr =
         RealVal.convertFromString(Tok.getString(), APFloat::rmTowardZero);
-    if (errorToBool(StatusOrErr.takeError())) {
-      TokError("invalid floating point representation");
-      return MatchOperand_ParseFail;
-    }
+    if (errorToBool(StatusOrErr.takeError()))
+      return TokError("invalid floating point representation");
 
     if (isNegative)
       RealVal.changeSign();
 
     if (AddFPZeroAsLiteral && RealVal.isPosZero()) {
       Operands.push_back(AArch64Operand::CreateToken("#0", S, getContext()));
       Operands.push_back(AArch64Operand::CreateToken(".0", S, getContext()));
     } else
       Operands.push_back(AArch64Operand::CreateFPImm(
           RealVal, *StatusOrErr == APFloat::opOK, S, getContext()));
   }
 
   Lex(); // Eat the token.
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseImmWithOptionalShift - Parse immediate operand, optionally with
 /// a shift suffix, for example '#1, lsl #12'.
-OperandMatchResultTy
+ParseStatus
 AArch64AsmParser::tryParseImmWithOptionalShift(OperandVector &Operands) {
   SMLoc S = getLoc();
 
   if (getTok().is(AsmToken::Hash))
     Lex(); // Eat '#'
   else if (getTok().isNot(AsmToken::Integer))
     // Operand should start from # or should be integer, emit error otherwise.
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   if (getTok().is(AsmToken::Integer) &&
       getLexer().peekTok().is(AsmToken::Colon))
     return tryParseImmRange(Operands);
 
   const MCExpr *Imm = nullptr;
   if (parseSymbolicImmVal(Imm))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
   else if (getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(
         AArch64Operand::CreateImm(Imm, S, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // Eat ','
   Lex();
   StringRef VecGroup;
   if (!parseOptionalVGOperand(Operands, VecGroup)) {
     Operands.push_back(
         AArch64Operand::CreateImm(Imm, S, getLoc(), getContext()));
     Operands.push_back(
         AArch64Operand::CreateToken(VecGroup, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // The optional operand must be "lsl #N" where N is non-negative.
   if (!getTok().is(AsmToken::Identifier) ||
-      !getTok().getIdentifier().equals_insensitive("lsl")) {
-    Error(getLoc(), "only 'lsl #+N' valid after immediate");
-    return MatchOperand_ParseFail;
-  }
+      !getTok().getIdentifier().equals_insensitive("lsl"))
+    return Error(getLoc(), "only 'lsl #+N' valid after immediate");
 
   // Eat 'lsl'
   Lex();
 
   parseOptionalToken(AsmToken::Hash);
 
-  if (getTok().isNot(AsmToken::Integer)) {
-    Error(getLoc(), "only 'lsl #+N' valid after immediate");
-    return MatchOperand_ParseFail;
-  }
+  if (getTok().isNot(AsmToken::Integer))
+    return Error(getLoc(), "only 'lsl #+N' valid after immediate");
 
   int64_t ShiftAmount = getTok().getIntVal();
 
-  if (ShiftAmount < 0) {
-    Error(getLoc(), "positive shift amount required");
-    return MatchOperand_ParseFail;
-  }
+  if (ShiftAmount < 0)
+    return Error(getLoc(), "positive shift amount required");
   Lex(); // Eat the number
 
   // Just in case the optional lsl #0 is used for immediates other than zero.
   if (ShiftAmount == 0 && Imm != nullptr) {
     Operands.push_back(
         AArch64Operand::CreateImm(Imm, S, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   Operands.push_back(AArch64Operand::CreateShiftedImm(Imm, ShiftAmount, S,
                                                       getLoc(), getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// parseCondCodeString - Parse a Condition Code string, optionally returning a
 /// suggestion to help common typos.
 AArch64CC::CondCode
 AArch64AsmParser::parseCondCodeString(StringRef Cond, std::string &Suggestion) {
   AArch64CC::CondCode CC = StringSwitch<AArch64CC::CondCode>(Cond.lower())
                     .Case("eq", AArch64CC::EQ)
if (invertCondCode) {
     CC = AArch64CC::getInvertedCondCode(AArch64CC::CondCode(CC));
   }
 
   Operands.push_back(
       AArch64Operand::CreateCondCode(CC, S, getLoc(), getContext()));
   return false;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSVCR(OperandVector &Operands) {
   const AsmToken &Tok = getTok();
   SMLoc S = getLoc();
 
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("invalid operand for instruction");
 
   unsigned PStateImm = -1;
   const auto *SVCR = AArch64SVCR::lookupSVCRByName(Tok.getString());
   if (!SVCR)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
   if (SVCR->haveFeatures(getSTI().getFeatureBits()))
     PStateImm = SVCR->Encoding;
 
   Operands.push_back(
       AArch64Operand::CreateSVCR(PStateImm, Tok.getString(), S, getContext()));
   Lex(); // Eat identifier token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseMatrixRegister(OperandVector &Operands) {
   const AsmToken &Tok = getTok();
   SMLoc S = getLoc();
 
   StringRef Name = Tok.getString();
 
   if (Name.equals_insensitive("za") || Name.starts_with_insensitive("za.")) {
     Lex(); // eat "za[.(b|h|s|d)]"
     unsigned ElementWidth = 0;
     auto DotPosition = Name.find('.');
     if (DotPosition != StringRef::npos) {
       const auto &KindRes =
           parseVectorKind(Name.drop_front(DotPosition), RegKind::Matrix);
-      if (!KindRes) {
-        TokError(
+      if (!KindRes)
+        return TokError(
             "Expected the register to be followed by element width suffix");
-        return MatchOperand_ParseFail;
-      }
       ElementWidth = KindRes->second;
     }
     Operands.push_back(AArch64Operand::CreateMatrixRegister(
         AArch64::ZA, ElementWidth, MatrixKind::Array, S, getLoc(),
         getContext()));
     if (getLexer().is(AsmToken::LBrac)) {
       // There's no comma after matrix operand, so we can parse the next operand
       // immediately.
       if (parseOperand(Operands, false, false))
-        return MatchOperand_NoMatch;
+        return ParseStatus::NoMatch;
     }
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // Try to parse matrix register.
   unsigned Reg = matchRegisterNameAlias(Name, RegKind::Matrix);
   if (!Reg)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   size_t DotPosition = Name.find('.');
   assert(DotPosition != StringRef::npos && "Unexpected register");
 
   StringRef Head = Name.take_front(DotPosition);
   StringRef Tail = Name.drop_front(DotPosition);
   StringRef RowOrColumn = Head.take_back();
 
   MatrixKind Kind = StringSwitch<MatrixKind>(RowOrColumn.lower())
                         .Case("h", MatrixKind::Row)
                         .Case("v", MatrixKind::Col)
                         .Default(MatrixKind::Tile);
 
   // Next up, parsing the suffix
   const auto &KindRes = parseVectorKind(Tail, RegKind::Matrix);
-  if (!KindRes) {
-    TokError("Expected the register to be followed by element width suffix");
-    return MatchOperand_ParseFail;
-  }
+  if (!KindRes)
+    return TokError(
+        "Expected the register to be followed by element width suffix");
   unsigned ElementWidth = KindRes->second;
 
   Lex();
 
   Operands.push_back(AArch64Operand::CreateMatrixRegister(
       Reg, ElementWidth, Kind, S, getLoc(), getContext()));
 
   if (getLexer().is(AsmToken::LBrac)) {
     // There's no comma after matrix operand, so we can parse the next operand
     // immediately.
     if (parseOperand(Operands, false, false))
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
   }
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseOptionalShift - Some operands take an optional shift argument. Parse
 /// them if present.
-OperandMatchResultTy
+ParseStatus
 AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) {
   const AsmToken &Tok = getTok();
   std::string LowerID = Tok.getString().lower();
   AArch64_AM::ShiftExtendType ShOp =
       StringSwitch<AArch64_AM::ShiftExtendType>(LowerID)
           .Case("lsl", AArch64_AM::LSL)
           .Case("lsr", AArch64_AM::LSR)
           .Case("asr", AArch64_AM::ASR)
           .Case("ror", AArch64_AM::ROR)
           .Case("msl", AArch64_AM::MSL)
           .Case("uxtb", AArch64_AM::UXTB)
           .Case("uxth", AArch64_AM::UXTH)
           .Case("uxtw", AArch64_AM::UXTW)
           .Case("uxtx", AArch64_AM::UXTX)
           .Case("sxtb", AArch64_AM::SXTB)
           .Case("sxth", AArch64_AM::SXTH)
           .Case("sxtw", AArch64_AM::SXTW)
           .Case("sxtx", AArch64_AM::SXTX)
           .Default(AArch64_AM::InvalidShiftExtend);
 
   if (ShOp == AArch64_AM::InvalidShiftExtend)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   SMLoc S = Tok.getLoc();
   Lex();
 
   bool Hash = parseOptionalToken(AsmToken::Hash);
 
   if (!Hash && getLexer().isNot(AsmToken::Integer)) {
     if (ShOp == AArch64_AM::LSL || ShOp == AArch64_AM::LSR ||
         ShOp == AArch64_AM::ASR || ShOp == AArch64_AM::ROR ||
         ShOp == AArch64_AM::MSL) {
       // We expect a number here.
-      TokError("expected #imm after shift specifier");
-      return MatchOperand_ParseFail;
+      return TokError("expected #imm after shift specifier");
     }
 
     // "extend" type operations don't need an immediate, #0 is implicit.
     SMLoc E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
     Operands.push_back(
         AArch64Operand::CreateShiftExtend(ShOp, 0, false, S, E, getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // Make sure we do actually have a number, identifier or a parenthesized
   // expression.
   SMLoc E = getLoc();
   if (!getTok().is(AsmToken::Integer) && !getTok().is(AsmToken::LParen) &&
-      !getTok().is(AsmToken::Identifier)) {
-    Error(E, "expected integer shift amount");
-    return MatchOperand_ParseFail;
-  }
+      !getTok().is(AsmToken::Identifier))
+    return Error(E, "expected integer shift amount");
 
   const MCExpr *ImmVal;
   if (getParser().parseExpression(ImmVal))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-  if (!MCE) {
-    Error(E, "expected constant '#imm' after shift specifier");
-    return MatchOperand_ParseFail;
-  }
+  if (!MCE)
+    return Error(E, "expected constant '#imm' after shift specifier");
 
   E = SMLoc::getFromPointer(getLoc().getPointer() - 1);
   Operands.push_back(AArch64Operand::CreateShiftExtend(
       ShOp, MCE->getValue(), true, S, E, getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 static const struct Extension {
   const char *Name;
   const FeatureBitset Features;
 } ExtensionMap[] = {
     {"crc", {AArch64::FeatureCRC}},
     {"sm4", {AArch64::FeatureSM4}},
bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
   Lex(); // Eat operand.
 
   if (parseComma())
     return true;
 
   if (Tok.isNot(AsmToken::Identifier))
     return TokError("expected register identifier");
   auto Result = tryParseSyspXzrPair(Operands);
-  if (Result == MatchOperand_NoMatch)
+  if (Result.isNoMatch())
     Result = tryParseGPRSeqPair(Operands);
-  if (Result != MatchOperand_Success)
+  if (!Result.isSuccess())
     return TokError("specified " + Mnemonic +
                     " op requires a pair of registers");
 
   if (parseToken(AsmToken::EndOfStatement, "unexpected token in argument list"))
     return true;
 
   return false;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
   const AsmToken &Tok = getTok();
 
-  if (Mnemonic == "tsb" && Tok.isNot(AsmToken::Identifier)) {
-    TokError("'csync' operand expected");
-    return MatchOperand_ParseFail;
-  } else if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
+  if (Mnemonic == "tsb" && Tok.isNot(AsmToken::Identifier))
+    return TokError("'csync' operand expected");
+  if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
     // Immediate operand.
     const MCExpr *ImmVal;
     SMLoc ExprLoc = getLoc();
     AsmToken IntTok = Tok;
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      Error(ExprLoc, "immediate value expected for barrier operand");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return Error(ExprLoc, "immediate value expected for barrier operand");
     int64_t Value = MCE->getValue();
     if (Mnemonic == "dsb" && Value > 15) {
       // This case is a no match here, but it might be matched by the nXS
       // variant. Deliberately not unlex the optional '#' as it is not necessary
       // to characterize an integer immediate.
       Parser.getLexer().UnLex(IntTok);
-      return MatchOperand_NoMatch;
-    }
-    if (Value < 0 || Value > 15) {
-      Error(ExprLoc, "barrier operand out of range");
-      return MatchOperand_ParseFail;
+      return ParseStatus::NoMatch;
     }
+    if (Value < 0 || Value > 15)
+      return Error(ExprLoc, "barrier operand out of range");
     auto DB = AArch64DB::lookupDBByEncoding(Value);
     Operands.push_back(AArch64Operand::CreateBarrier(Value, DB ? DB->Name : "",
                                                      ExprLoc, getContext(),
                                                      false /*hasnXSModifier*/));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("invalid operand for instruction");
 
   StringRef Operand = Tok.getString();
   auto TSB = AArch64TSB::lookupTSBByName(Operand);
   auto DB = AArch64DB::lookupDBByName(Operand);
   // The only valid named option for ISB is 'sy'
-  if (Mnemonic == "isb" && (!DB || DB->Encoding != AArch64DB::sy)) {
-    TokError("'sy' or #imm operand expected");
-    return MatchOperand_ParseFail;
+  if (Mnemonic == "isb" && (!DB || DB->Encoding != AArch64DB::sy))
+    return TokError("'sy' or #imm operand expected");
   // The only valid named option for TSB is 'csync'
-  } else if (Mnemonic == "tsb" && (!TSB || TSB->Encoding != AArch64TSB::csync)) {
-    TokError("'csync' operand expected");
-    return MatchOperand_ParseFail;
-  } else if (!DB && !TSB) {
+  if (Mnemonic == "tsb" && (!TSB || TSB->Encoding != AArch64TSB::csync))
+    return TokError("'csync' operand expected");
+  if (!DB && !TSB) {
     if (Mnemonic == "dsb") {
       // This case is a no match here, but it might be matched by the nXS
       // variant.
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
     }
-    TokError("invalid barrier option name");
-    return MatchOperand_ParseFail;
+    return TokError("invalid barrier option name");
   }
 
   Operands.push_back(AArch64Operand::CreateBarrier(
       DB ? DB->Encoding : TSB->Encoding, Tok.getString(), getLoc(),
       getContext(), false /*hasnXSModifier*/));
   Lex(); // Consume the option
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
+ParseStatus
 AArch64AsmParser::tryParseBarriernXSOperand(OperandVector &Operands) {
   const AsmToken &Tok = getTok();
 
   assert(Mnemonic == "dsb" && "Instruction does not accept nXS operands");
   if (Mnemonic != "dsb")
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   if (parseOptionalToken(AsmToken::Hash) || Tok.is(AsmToken::Integer)) {
     // Immediate operand.
     const MCExpr *ImmVal;
     SMLoc ExprLoc = getLoc();
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      Error(ExprLoc, "immediate value expected for barrier operand");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return Error(ExprLoc, "immediate value expected for barrier operand");
     int64_t Value = MCE->getValue();
     // v8.7-A DSB in the nXS variant accepts only the following immediate
     // values: 16, 20, 24, 28.
-    if (Value != 16 && Value != 20 && Value != 24 && Value != 28) {
-      Error(ExprLoc, "barrier operand out of range");
-      return MatchOperand_ParseFail;
-    }
+    if (Value != 16 && Value != 20 && Value != 24 && Value != 28)
+      return Error(ExprLoc, "barrier operand out of range");
     auto DB = AArch64DBnXS::lookupDBnXSByImmValue(Value);
     Operands.push_back(AArch64Operand::CreateBarrier(DB->Encoding, DB->Name,
                                                      ExprLoc, getContext(),
                                                      true /*hasnXSModifier*/));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  if (Tok.isNot(AsmToken::Identifier)) {
-    TokError("invalid operand for instruction");
-    return MatchOperand_ParseFail;
-  }
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("invalid operand for instruction");
 
   StringRef Operand = Tok.getString();
   auto DB = AArch64DBnXS::lookupDBnXSByName(Operand);
 
-  if (!DB) {
-    TokError("invalid barrier option name");
-    return MatchOperand_ParseFail;
-  }
+  if (!DB)
+    return TokError("invalid barrier option name");
 
   Operands.push_back(
       AArch64Operand::CreateBarrier(DB->Encoding, Tok.getString(), getLoc(),
                                     getContext(), true /*hasnXSModifier*/));
   Lex(); // Consume the option
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSysReg(OperandVector &Operands) {
   const AsmToken &Tok = getTok();
 
   if (Tok.isNot(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   if (AArch64SVCR::lookupSVCRByName(Tok.getString()))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   int MRSReg, MSRReg;
   auto SysReg = AArch64SysReg::lookupSysRegByName(Tok.getString());
   if (SysReg && SysReg->haveFeatures(getSTI().getFeatureBits())) {
     MRSReg = SysReg->Readable ? SysReg->Encoding : -1;
     MSRReg = SysReg->Writeable ? SysReg->Encoding : -1;
   } else
     MRSReg = MSRReg = AArch64SysReg::parseGenericRegister(Tok.getString());
 
   unsigned PStateImm = -1;
   auto PState15 = AArch64PState::lookupPStateImm0_15ByName(Tok.getString());
   if (PState15 && PState15->haveFeatures(getSTI().getFeatureBits()))
     PStateImm = PState15->Encoding;
   if (!PState15) {
     auto PState1 = AArch64PState::lookupPStateImm0_1ByName(Tok.getString());
     if (PState1 && PState1->haveFeatures(getSTI().getFeatureBits()))
       PStateImm = PState1->Encoding;
   }
 
   Operands.push_back(
       AArch64Operand::CreateSysReg(Tok.getString(), getLoc(), MRSReg, MSRReg,
                                    PStateImm, getContext()));
   Lex(); // Eat identifier
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// tryParseNeonVectorRegister - Parse a vector register operand.
 bool AArch64AsmParser::tryParseNeonVectorRegister(OperandVector &Operands) {
   if (getTok().isNot(AsmToken::Identifier))
     return true;
 
   SMLoc S = getLoc();
   // Check for a vector register specifier first.
   StringRef Kind;
   MCRegister Reg;
-  OperandMatchResultTy Res =
-      tryParseVectorRegister(Reg, Kind, RegKind::NeonVector);
-  if (Res != MatchOperand_Success)
+  ParseStatus Res = tryParseVectorRegister(Reg, Kind, RegKind::NeonVector);
+  if (!Res.isSuccess())
     return true;
 
   const auto &KindRes = parseVectorKind(Kind, RegKind::NeonVector);
   if (!KindRes)
     return true;
 
   unsigned ElementWidth = KindRes->second;
   Operands.push_back(
       AArch64Operand::CreateVectorReg(Reg, RegKind::NeonVector, ElementWidth,
                                       S, getLoc(), getContext()));
 
   // If there was an explicit qualifier, that goes on as a literal text
   // operand.
   if (!Kind.empty())
     Operands.push_back(AArch64Operand::CreateToken(Kind, S, getContext()));
 
-  return tryParseVectorIndex(Operands) == MatchOperand_ParseFail;
+  return tryParseVectorIndex(Operands).isFailure();
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseVectorIndex(OperandVector &Operands) {
   SMLoc SIdx = getLoc();
   if (parseOptionalToken(AsmToken::LBrac)) {
     const MCExpr *ImmVal;
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      TokError("immediate value expected for vector index");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return TokError("immediate value expected for vector index");
 
     SMLoc E = getLoc();
 
     if (parseToken(AsmToken::RBrac, "']' expected"))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     Operands.push_back(AArch64Operand::CreateVectorIndex(MCE->getValue(), SIdx,
                                                          E, getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  return MatchOperand_NoMatch;
+  return ParseStatus::NoMatch;
 }
 
 // tryParseVectorRegister - Try to parse a vector register name with
 // optional kind specifier. If it is a register specifier, eat the token
 // and return it.
-OperandMatchResultTy
-AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg, StringRef &Kind,
+ParseStatus AArch64AsmParser::tryParseVectorRegister(MCRegister &Reg,
+                                                     StringRef &Kind,
                                                      RegKind MatchKind) {
   const AsmToken &Tok = getTok();
 
   if (Tok.isNot(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   StringRef Name = Tok.getString();
   // If there is a kind specifier, it's separated from the register name by
   // a '.'.
   size_t Start = 0, Next = Name.find('.');
   StringRef Head = Name.slice(Start, Next);
   unsigned RegNum = matchRegisterNameAlias(Head, MatchKind);
 
   if (RegNum) {
     if (Next != StringRef::npos) {
       Kind = Name.slice(Next, StringRef::npos);
-      if (!isValidVectorKind(Kind, MatchKind)) {
-        TokError("invalid vector kind qualifier");
-        return MatchOperand_ParseFail;
-      }
+      if (!isValidVectorKind(Kind, MatchKind))
+        return TokError("invalid vector kind qualifier");
     }
     Lex(); // Eat the register token.
 
     Reg = RegNum;
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
-  return MatchOperand_NoMatch;
+  return ParseStatus::NoMatch;
 }
 
 /// tryParseSVEPredicateVector - Parse a SVE predicate register operand.
-template <RegKind RK> OperandMatchResultTy
+template <RegKind RK>
+ParseStatus
 AArch64AsmParser::tryParseSVEPredicateVector(OperandVector &Operands) {
   // Check for a SVE predicate register specifier first.
   const SMLoc S = getLoc();
   StringRef Kind;
   MCRegister RegNum;
   auto Res = tryParseVectorRegister(RegNum, Kind, RK);
-  if (Res != MatchOperand_Success)
+  if (!Res.isSuccess())
     return Res;
 
   const auto &KindRes = parseVectorKind(Kind, RK);
   if (!KindRes)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   unsigned ElementWidth = KindRes->second;
   Operands.push_back(AArch64Operand::CreateVectorReg(
       RegNum, RK, ElementWidth, S,
       getLoc(), getContext()));
 
   if (getLexer().is(AsmToken::LBrac)) {
     if (RK == RegKind::SVEPredicateAsCounter) {
-      OperandMatchResultTy ResIndex = tryParseVectorIndex(Operands);
-      if (ResIndex == MatchOperand_Success)
-        return MatchOperand_Success;
+      ParseStatus ResIndex = tryParseVectorIndex(Operands);
+      if (ResIndex.isSuccess())
+        return ParseStatus::Success;
     } else {
       // Indexed predicate, there's no comma so try parse the next operand
       // immediately.
       if (parseOperand(Operands, false, false))
-        return MatchOperand_NoMatch;
+        return ParseStatus::NoMatch;
     }
   }
 
   // Not all predicates are followed by a '/m' or '/z'.
   if (getTok().isNot(AsmToken::Slash))
-    return MatchOperand_Success;
+    return ParseStatus::Success;
 
   // But when they do they shouldn't have an element type suffix.
-  if (!Kind.empty()) {
-    Error(S, "not expecting size suffix");
-    return MatchOperand_ParseFail;
-  }
+  if (!Kind.empty())
+    return Error(S, "not expecting size suffix");
 
   // Add a literal slash as operand
   Operands.push_back(AArch64Operand::CreateToken("/", getLoc(), getContext()));
 
   Lex(); // Eat the slash.
 
   // Zeroing or merging?
   auto Pred = getTok().getString().lower();
-  if (RK == RegKind::SVEPredicateAsCounter && Pred != "z") {
-    Error(getLoc(), "expecting 'z' predication");
-    return MatchOperand_ParseFail;
-  }
+  if (RK == RegKind::SVEPredicateAsCounter && Pred != "z")
+    return Error(getLoc(), "expecting 'z' predication");
 
-  if (RK == RegKind::SVEPredicateVector && Pred != "z" && Pred != "m") {
-    Error(getLoc(), "expecting 'm' or 'z' predication");
-    return MatchOperand_ParseFail;
-  }
+  if (RK == RegKind::SVEPredicateVector && Pred != "z" && Pred != "m")
+    return Error(getLoc(), "expecting 'm' or 'z' predication");
 
   // Add zero/merge token.
   const char *ZM = Pred == "z" ? "z" : "m";
   Operands.push_back(AArch64Operand::CreateToken(ZM, getLoc(), getContext()));
 
   Lex(); // Eat zero/merge token.
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// parseRegister - Parse a register operand.
 bool AArch64AsmParser::parseRegister(OperandVector &Operands) {
   // Try for a Neon vector register.
   if (!tryParseNeonVectorRegister(Operands))
     return false;
 
-  if (tryParseZTOperand(Operands) == MatchOperand_Success)
+  if (tryParseZTOperand(Operands).isSuccess())
     return false;
 
   // Otherwise try for a scalar register.
-  if (tryParseGPROperand<false>(Operands) == MatchOperand_Success)
+  if (tryParseGPROperand<false>(Operands).isSuccess())
     return false;
 
   return true;
 }
 
 bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
   bool HasELFModifier = false;
   AArch64MCExpr::VariantKind RefKind;
if (getParser().parseExpression(ImmVal))
     return true;
 
   if (HasELFModifier)
     ImmVal = AArch64MCExpr::create(ImmVal, RefKind, getContext());
 
   return false;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseMatrixTileList(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseMatrixTileList(OperandVector &Operands) {
   if (getTok().isNot(AsmToken::LCurly))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
-  auto ParseMatrixTile = [this](unsigned &Reg, unsigned &ElementWidth) {
+  auto ParseMatrixTile = [this](unsigned &Reg,
+                                unsigned &ElementWidth) -> ParseStatus {
     StringRef Name = getTok().getString();
     size_t DotPosition = Name.find('.');
     if (DotPosition == StringRef::npos)
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
 
     unsigned RegNum = matchMatrixTileListRegName(Name);
     if (!RegNum)
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
 
     StringRef Tail = Name.drop_front(DotPosition);
     const std::optional<std::pair<int, int>> &KindRes =
         parseVectorKind(Tail, RegKind::Matrix);
-    if (!KindRes) {
-      TokError("Expected the register to be followed by element width suffix");
-      return MatchOperand_ParseFail;
-    }
+    if (!KindRes)
+      return TokError(
+          "Expected the register to be followed by element width suffix");
     ElementWidth = KindRes->second;
     Reg = RegNum;
     Lex(); // Eat the register.
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   };
 
   SMLoc S = getLoc();
   auto LCurly = getTok();
   Lex(); // Eat left bracket token.
 
   // Empty matrix list
   if (parseOptionalToken(AsmToken::RCurly)) {
     Operands.push_back(AArch64Operand::CreateMatrixTileList(
         /*RegMask=*/0, S, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // Try parse {za} alias early
   if (getTok().getString().equals_insensitive("za")) {
     Lex(); // Eat 'za'
 
     if (parseToken(AsmToken::RCurly, "'}' expected"))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     Operands.push_back(AArch64Operand::CreateMatrixTileList(
         /*RegMask=*/0xFF, S, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   SMLoc TileLoc = getLoc();
 
   unsigned FirstReg, ElementWidth;
   auto ParseRes = ParseMatrixTile(FirstReg, ElementWidth);
-  if (ParseRes != MatchOperand_Success) {
+  if (!ParseRes.isSuccess()) {
     getLexer().UnLex(LCurly);
     return ParseRes;
   }
 
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
 
   unsigned PrevReg = FirstReg;
 
   SmallSet<unsigned, 8> DRegs;
   AArch64Operand::ComputeRegsForAlias(FirstReg, DRegs, ElementWidth);
 
   SmallSet<unsigned, 8> SeenRegs;
   SeenRegs.insert(FirstReg);
 
   while (parseOptionalToken(AsmToken::Comma)) {
     TileLoc = getLoc();
     unsigned Reg, NextElementWidth;
     ParseRes = ParseMatrixTile(Reg, NextElementWidth);
-    if (ParseRes != MatchOperand_Success)
+    if (!ParseRes.isSuccess())
       return ParseRes;
 
     // Element size must match on all regs in the list.
-    if (ElementWidth != NextElementWidth) {
-      Error(TileLoc, "mismatched register size suffix");
-      return MatchOperand_ParseFail;
-    }
+    if (ElementWidth != NextElementWidth)
+      return Error(TileLoc, "mismatched register size suffix");
 
     if (RI->getEncodingValue(Reg) <= (RI->getEncodingValue(PrevReg)))
       Warning(TileLoc, "tile list not in ascending order");
 
     if (SeenRegs.contains(Reg))
       Warning(TileLoc, "duplicate tile in list");
     else {
       SeenRegs.insert(Reg);
       AArch64Operand::ComputeRegsForAlias(Reg, DRegs, ElementWidth);
     }
 
     PrevReg = Reg;
   }
 
   if (parseToken(AsmToken::RCurly, "'}' expected"))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   unsigned RegMask = 0;
   for (auto Reg : DRegs)
     RegMask |= 0x1 << (RI->getEncodingValue(Reg) -
                        RI->getEncodingValue(AArch64::ZAD0));
   Operands.push_back(
       AArch64Operand::CreateMatrixTileList(RegMask, S, getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 template <RegKind VectorKind>
-OperandMatchResultTy
-AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
+ParseStatus AArch64AsmParser::tryParseVectorList(OperandVector &Operands,
                                                  bool ExpectMatch) {
   MCAsmParser &Parser = getParser();
   if (!getTok().is(AsmToken::LCurly))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   // Wrapper around parse function
   auto ParseVector = [this](MCRegister &Reg, StringRef &Kind, SMLoc Loc,
-                            bool NoMatchIsError) {
+                            bool NoMatchIsError) -> ParseStatus {
     auto RegTok = getTok();
     auto ParseRes = tryParseVectorRegister(Reg, Kind, VectorKind);
-    if (ParseRes == MatchOperand_Success) {
+    if (ParseRes.isSuccess()) {
       if (parseVectorKind(Kind, VectorKind))
         return ParseRes;
       llvm_unreachable("Expected a valid vector kind");
     }
 
-    if (RegTok.is(AsmToken::Identifier) && ParseRes == MatchOperand_NoMatch &&
+    if (RegTok.is(AsmToken::Identifier) && ParseRes.isNoMatch() &&
         RegTok.getString().equals_insensitive("zt0"))
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
 
-    if (RegTok.isNot(AsmToken::Identifier) ||
-        ParseRes == MatchOperand_ParseFail ||
-        (ParseRes == MatchOperand_NoMatch && NoMatchIsError &&
-         !RegTok.getString().starts_with_insensitive("za"))) {
-      Error(Loc, "vector register expected");
-      return MatchOperand_ParseFail;
-    }
+    if (RegTok.isNot(AsmToken::Identifier) || ParseRes.isFailure() ||
+        (ParseRes.isNoMatch() && NoMatchIsError &&
+         !RegTok.getString().starts_with_insensitive("za")))
+      return Error(Loc, "vector register expected");
 
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
   };
 
   int NumRegs = getNumRegsForRegKind(VectorKind);
   SMLoc S = getLoc();
   auto LCurly = getTok();
   Lex(); // Eat left bracket token.
 
   StringRef Kind;
   MCRegister FirstReg;
   auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
 
   // Put back the original left bracket if there was no match, so that
   // different types of list-operands can be matched (e.g. SVE, Neon).
-  if (ParseRes == MatchOperand_NoMatch)
+  if (ParseRes.isNoMatch())
     Parser.getLexer().UnLex(LCurly);
 
-  if (ParseRes != MatchOperand_Success)
+  if (!ParseRes.isSuccess())
     return ParseRes;
 
   int64_t PrevReg = FirstReg;
   unsigned Count = 1;
 
   int Stride = 1;
   if (parseOptionalToken(AsmToken::Minus)) {
     SMLoc Loc = getLoc();
     StringRef NextKind;
 
     MCRegister Reg;
     ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
-    if (ParseRes != MatchOperand_Success)
+    if (!ParseRes.isSuccess())
       return ParseRes;
 
     // Any Kind suffices must match on all regs in the list.
-    if (Kind != NextKind) {
-      Error(Loc, "mismatched register size suffix");
-      return MatchOperand_ParseFail;
-    }
+    if (Kind != NextKind)
+      return Error(Loc, "mismatched register size suffix");
 
     unsigned Space =
         (PrevReg < Reg) ? (Reg - PrevReg) : (Reg + NumRegs - PrevReg);
 
-    if (Space == 0 || Space > 3) {
-      Error(Loc, "invalid number of vectors");
-      return MatchOperand_ParseFail;
-    }
+    if (Space == 0 || Space > 3)
+      return Error(Loc, "invalid number of vectors");
 
     Count += Space;
   }
   else {
     bool HasCalculatedStride = false;
     while (parseOptionalToken(AsmToken::Comma)) {
       SMLoc Loc = getLoc();
       StringRef NextKind;
       MCRegister Reg;
       ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
-      if (ParseRes != MatchOperand_Success)
+      if (!ParseRes.isSuccess())
         return ParseRes;
 
       // Any Kind suffices must match on all regs in the list.
-      if (Kind != NextKind) {
-        Error(Loc, "mismatched register size suffix");
-        return MatchOperand_ParseFail;
-      }
+      if (Kind != NextKind)
+        return Error(Loc, "mismatched register size suffix");
 
       unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg);
       unsigned PrevRegVal =
           getContext().getRegisterInfo()->getEncodingValue(PrevReg);
       if (!HasCalculatedStride) {
         Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal)
                                        : (RegVal + NumRegs - PrevRegVal);
         HasCalculatedStride = true;
       }
 
       // Register must be incremental (with a wraparound at last register).
-      if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs)) {
-        Error(Loc, "registers must have the same sequential stride");
-        return MatchOperand_ParseFail;
-      }
+      if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs))
+        return Error(Loc, "registers must have the same sequential stride");
 
       PrevReg = Reg;
       ++Count;
     }
   }
 
   if (parseToken(AsmToken::RCurly, "'}' expected"))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
-  if (Count > 4) {
-    Error(S, "invalid number of vectors");
-    return MatchOperand_ParseFail;
-  }
+  if (Count > 4)
+    return Error(S, "invalid number of vectors");
 
   unsigned NumElements = 0;
   unsigned ElementWidth = 0;
   if (!Kind.empty()) {
     if (const auto &VK = parseVectorKind(Kind, VectorKind))
       std::tie(NumElements, ElementWidth) = *VK;
   }
 
   Operands.push_back(AArch64Operand::CreateVectorList(
       FirstReg, Count, Stride, NumElements, ElementWidth, VectorKind, S,
       getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 /// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
 bool AArch64AsmParser::parseNeonVectorList(OperandVector &Operands) {
   auto ParseRes = tryParseVectorList<RegKind::NeonVector>(Operands, true);
-  if (ParseRes != MatchOperand_Success)
+  if (!ParseRes.isSuccess())
     return true;
 
-  return tryParseVectorIndex(Operands) == MatchOperand_ParseFail;
+  return tryParseVectorIndex(Operands).isFailure();
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
 
   MCRegister RegNum;
-  OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
-  if (Res != MatchOperand_Success)
+  ParseStatus Res = tryParseScalarRegister(RegNum);
+  if (!Res.isSuccess())
     return Res;
 
   if (!parseOptionalToken(AsmToken::Comma)) {
     Operands.push_back(AArch64Operand::CreateReg(
         RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   parseOptionalToken(AsmToken::Hash);
 
-  if (getTok().isNot(AsmToken::Integer)) {
-    Error(getLoc(), "index must be absent or #0");
-    return MatchOperand_ParseFail;
-  }
+  if (getTok().isNot(AsmToken::Integer))
+    return Error(getLoc(), "index must be absent or #0");
 
   const MCExpr *ImmVal;
   if (getParser().parseExpression(ImmVal) || !isa<MCConstantExpr>(ImmVal) ||
-      cast<MCConstantExpr>(ImmVal)->getValue() != 0) {
-    Error(getLoc(), "index must be absent or #0");
-    return MatchOperand_ParseFail;
-  }
+      cast<MCConstantExpr>(ImmVal)->getValue() != 0)
+    return Error(getLoc(), "index must be absent or #0");
 
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseZTOperand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseZTOperand(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
   const AsmToken &Tok = getTok();
   std::string Name = Tok.getString().lower();
 
   unsigned RegNum = matchRegisterNameAlias(Name, RegKind::LookupTable);
 
   if (RegNum == 0)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::LookupTable, StartLoc, getLoc(), getContext()));
   Lex(); // Eat identifier token.
 
   // Check if register is followed by an index
   if (parseOptionalToken(AsmToken::LBrac)) {
     const MCExpr *ImmVal;
     if (getParser().parseExpression(ImmVal))
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
     const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal);
-    if (!MCE) {
-      TokError("immediate value expected for vector index");
-      return MatchOperand_ParseFail;
-    }
+    if (!MCE)
+      return TokError("immediate value expected for vector index");
     if (parseToken(AsmToken::RBrac, "']' expected"))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     Operands.push_back(AArch64Operand::CreateImm(
         MCConstantExpr::create(MCE->getValue(), getContext()), StartLoc,
         getLoc(), getContext()));
   }
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 template <bool ParseShiftExtend, RegConstraintEqualityTy EqTy>
-OperandMatchResultTy
-AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseGPROperand(OperandVector &Operands) {
   SMLoc StartLoc = getLoc();
 
   MCRegister RegNum;
-  OperandMatchResultTy Res = tryParseScalarRegister(RegNum);
-  if (Res != MatchOperand_Success)
+  ParseStatus Res = tryParseScalarRegister(RegNum);
+  if (!Res.isSuccess())
     return Res;
 
   // No shift/extend is the default.
   if (!ParseShiftExtend || getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(AArch64Operand::CreateReg(
         RegNum, RegKind::Scalar, StartLoc, getLoc(), getContext(), EqTy));
-    return MatchOperand_Success;
+    return ParseStatus::Success;
   }
 
   // Eat the comma
   Lex();
 
   // Match the shift
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
   Res = tryParseOptionalShiftExtend(ExtOpnd);
-  if (Res != MatchOperand_Success)
+  if (!Res.isSuccess())
     return Res;
 
   auto Ext = static_cast<AArch64Operand*>(ExtOpnd.back().get());
   Operands.push_back(AArch64Operand::CreateReg(
       RegNum, RegKind::Scalar, StartLoc, Ext->getEndLoc(), getContext(), EqTy,
       Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
       Ext->hasShiftExtendAmount()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 bool AArch64AsmParser::parseOptionalMulOperand(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
 
   // Some SVE instructions have a decoration after the immediate, i.e.
   // "mul vl". We parse them here and add tokens, which must be present in the
   // asm string in the tablegen instruction.
if (NextIsHash) {
 
     // Parse immediate operand.
     const MCExpr *ImmVal;
     if (!Parser.parseExpression(ImmVal))
       if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(ImmVal)) {
         Operands.push_back(AArch64Operand::CreateImm(
             MCConstantExpr::create(MCE->getValue(), getContext()), S, getLoc(),
             getContext()));
-        return MatchOperand_Success;
+        return false;
       }
   }
 
   return Error(getLoc(), "expected 'vl' or '#<imm>'");
 }
 
 bool AArch64AsmParser::parseOptionalVGOperand(OperandVector &Operands,
                                               StringRef &VecGroup) {

 }
 
 /// parseOperand - Parse a arm instruction operand.  For now this parses the
 /// operand regardless of the mnemonic.
 bool AArch64AsmParser::parseOperand(OperandVector &Operands, bool isCondCode,
                                   bool invertCondCode) {
   MCAsmParser &Parser = getParser();
 
-  OperandMatchResultTy ResTy =
-      MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/ true);
+  ParseStatus ResTy =
+      MatchOperandParserImpl(Operands, Mnemonic, /*ParseForAllFeatures=*/true);
 
   // Check if the current operand has a custom associated parser, if so, try to
   // custom parse the operand, or fallback to the general approach.
-  if (ResTy == MatchOperand_Success)
+  if (ResTy.isSuccess())
     return false;
   // If there wasn't a custom match, try the generic matcher below. Otherwise,
   // there was a match, but an error occurred, in which case, just return that
   // the operand parsing failed.
-  if (ResTy == MatchOperand_ParseFail)
+  if (ResTy.isFailure())
     return true;
 
   // Nothing custom, so do general case parsing.
   SMLoc S, E;
   switch (getLexer().getKind()) {
   default: {
     SMLoc S = getLoc();
     const MCExpr *Expr;
if (!parseRegister(Operands))
       return false;
 
     // See if this is a "mul vl" decoration or "mul #<int>" operand used
     // by SVE instructions.
     if (!parseOptionalMulOperand(Operands))
       return false;
 
     // This could be an optional "shift" or "extend" operand.
-    OperandMatchResultTy GotShift = tryParseOptionalShiftExtend(Operands);
+    ParseStatus GotShift = tryParseOptionalShiftExtend(Operands);
     // We can only continue if no tokens were eaten.
-    if (GotShift != MatchOperand_NoMatch)
-      return GotShift;
+    if (!GotShift.isNoMatch())
+      return GotShift.isFailure();
 
     // If this is a two-word mnemonic, parse its special keyword
     // operand as an identifier.
     if (Mnemonic == "brb" || Mnemonic == "smstart" || Mnemonic == "smstop" ||
         Mnemonic == "gcsb")
       return parseKeywordOperand(Operands);
 
     // This was not a register so parse other operands that start with an

 
 /// parseDirectiveReq
 ///  ::= name .req registername
 bool AArch64AsmParser::parseDirectiveReq(StringRef Name, SMLoc L) {
   Lex(); // Eat the '.req' token.
   SMLoc SRegLoc = getLoc();
   RegKind RegisterKind = RegKind::Scalar;
   MCRegister RegNum;
-  OperandMatchResultTy ParseRes = tryParseScalarRegister(RegNum);
+  ParseStatus ParseRes = tryParseScalarRegister(RegNum);
 
-  if (ParseRes != MatchOperand_Success) {
+  if (!ParseRes.isSuccess()) {
     StringRef Kind;
     RegisterKind = RegKind::NeonVector;
     ParseRes = tryParseVectorRegister(RegNum, Kind, RegKind::NeonVector);
 
-    if (ParseRes == MatchOperand_ParseFail)
+    if (ParseRes.isFailure())
       return true;
 
-    if (ParseRes == MatchOperand_Success && !Kind.empty())
+    if (ParseRes.isSuccess() && !Kind.empty())
       return Error(SRegLoc, "vector register without type specifier expected");
   }
 
-  if (ParseRes != MatchOperand_Success) {
+  if (!ParseRes.isSuccess()) {
     StringRef Kind;
     RegisterKind = RegKind::SVEDataVector;
     ParseRes =
         tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector);
 
-    if (ParseRes == MatchOperand_ParseFail)
+    if (ParseRes.isFailure())
       return true;
 
-    if (ParseRes == MatchOperand_Success && !Kind.empty())
+    if (ParseRes.isSuccess() && !Kind.empty())
       return Error(SRegLoc,
                    "sve vector register without type specifier expected");
   }
 
-  if (ParseRes != MatchOperand_Success) {
+  if (!ParseRes.isSuccess()) {
     StringRef Kind;
     RegisterKind = RegKind::SVEPredicateVector;
     ParseRes = tryParseVectorRegister(RegNum, Kind, RegKind::SVEPredicateVector);
 
-    if (ParseRes == MatchOperand_ParseFail)
+    if (ParseRes.isFailure())
       return true;
 
-    if (ParseRes == MatchOperand_Success && !Kind.empty())
+    if (ParseRes.isSuccess() && !Kind.empty())
       return Error(SRegLoc,
                    "sve predicate register without type specifier expected");
   }
 
-  if (ParseRes != MatchOperand_Success)
+  if (!ParseRes.isSuccess())
     return Error(SRegLoc, "register name or alias expected");
 
   // Shouldn't be anything else.
   if (parseEOL())
     return true;
 
   auto pair = std::make_pair(RegisterKind, (unsigned) RegNum);
   if (RegisterReqs.insert(std::make_pair(Name, pair)).first->second != pair)
case MCK__HASH__MINUS_##N:                                                   \
     return MatchesOpImmediate(-N);
     MATCH_HASH_MINUS(4)
     MATCH_HASH_MINUS(8)
     MATCH_HASH_MINUS(16)
 #undef MATCH_HASH_MINUS
   }
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) {
 
   SMLoc S = getLoc();
 
-  if (getTok().isNot(AsmToken::Identifier)) {
-    Error(S, "expected register");
-    return MatchOperand_ParseFail;
-  }
+  if (getTok().isNot(AsmToken::Identifier))
+    return Error(S, "expected register");
 
   MCRegister FirstReg;
-  OperandMatchResultTy Res = tryParseScalarRegister(FirstReg);
-  if (Res != MatchOperand_Success) {
-    Error(S, "expected first even register of a "
-             "consecutive same-size even/odd register pair");
-    return MatchOperand_ParseFail;
-  }
+  ParseStatus Res = tryParseScalarRegister(FirstReg);
+  if (!Res.isSuccess())
+    return Error(S, "expected first even register of a consecutive same-size "
+                    "even/odd register pair");
 
   const MCRegisterClass &WRegClass =
       AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
   const MCRegisterClass &XRegClass =
       AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
 
   bool isXReg = XRegClass.contains(FirstReg),
        isWReg = WRegClass.contains(FirstReg);
-  if (!isXReg && !isWReg) {
-    Error(S, "expected first even register of a "
-             "consecutive same-size even/odd register pair");
-    return MatchOperand_ParseFail;
-  }
+  if (!isXReg && !isWReg)
+    return Error(S, "expected first even register of a consecutive same-size "
+                    "even/odd register pair");
 
   const MCRegisterInfo *RI = getContext().getRegisterInfo();
   unsigned FirstEncoding = RI->getEncodingValue(FirstReg);
 
-  if (FirstEncoding & 0x1) {
-    Error(S, "expected first even register of a "
-             "consecutive same-size even/odd register pair");
-    return MatchOperand_ParseFail;
-  }
+  if (FirstEncoding & 0x1)
+    return Error(S, "expected first even register of a consecutive same-size "
+                    "even/odd register pair");
 
-  if (getTok().isNot(AsmToken::Comma)) {
-    Error(getLoc(), "expected comma");
-    return MatchOperand_ParseFail;
-  }
+  if (getTok().isNot(AsmToken::Comma))
+    return Error(getLoc(), "expected comma");
   // Eat the comma
   Lex();
 
   SMLoc E = getLoc();
   MCRegister SecondReg;
   Res = tryParseScalarRegister(SecondReg);
-  if (Res != MatchOperand_Success) {
-    Error(E, "expected second odd register of a "
-             "consecutive same-size even/odd register pair");
-    return MatchOperand_ParseFail;
-  }
+  if (!Res.isSuccess())
+    return Error(E, "expected second odd register of a consecutive same-size "
+                    "even/odd register pair");
 
   if (RI->getEncodingValue(SecondReg) != FirstEncoding + 1 ||
       (isXReg && !XRegClass.contains(SecondReg)) ||
-      (isWReg && !WRegClass.contains(SecondReg))) {
-    Error(E, "expected second odd register of a "
-             "consecutive same-size even/odd register pair");
-    return MatchOperand_ParseFail;
-  }
+      (isWReg && !WRegClass.contains(SecondReg)))
+    return Error(E, "expected second odd register of a consecutive same-size "
+                    "even/odd register pair");
 
   unsigned Pair = 0;
   if (isXReg) {
     Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube64,
            &AArch64MCRegisterClasses[AArch64::XSeqPairsClassRegClassID]);
   } else {
     Pair = RI->getMatchingSuperReg(FirstReg, AArch64::sube32,
            &AArch64MCRegisterClasses[AArch64::WSeqPairsClassRegClassID]);
   }
 
   Operands.push_back(AArch64Operand::CreateReg(Pair, RegKind::Scalar, S,
       getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 template <bool ParseShiftExtend, bool ParseSuffix>
-OperandMatchResultTy
-AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSVEDataVector(OperandVector &Operands) {
   const SMLoc S = getLoc();
   // Check for a SVE vector register specifier first.
   MCRegister RegNum;
   StringRef Kind;
 
-  OperandMatchResultTy Res =
+  ParseStatus Res =
       tryParseVectorRegister(RegNum, Kind, RegKind::SVEDataVector);
 
-  if (Res != MatchOperand_Success)
+  if (!Res.isSuccess())
     return Res;
 
   if (ParseSuffix && Kind.empty())
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   const auto &KindRes = parseVectorKind(Kind, RegKind::SVEDataVector);
   if (!KindRes)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   unsigned ElementWidth = KindRes->second;
 
   // No shift/extend is the default.
   if (!ParseShiftExtend || getTok().isNot(AsmToken::Comma)) {
     Operands.push_back(AArch64Operand::CreateVectorReg(
         RegNum, RegKind::SVEDataVector, ElementWidth, S, S, getContext()));
 
-    OperandMatchResultTy Res = tryParseVectorIndex(Operands);
-    if (Res == MatchOperand_ParseFail)
-      return MatchOperand_ParseFail;
-    return MatchOperand_Success;
+    ParseStatus Res = tryParseVectorIndex(Operands);
+    if (Res.isFailure())
+      return ParseStatus::Failure;
+    return ParseStatus::Success;
   }
 
   // Eat the comma
   Lex();
 
   // Match the shift
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 1> ExtOpnd;
   Res = tryParseOptionalShiftExtend(ExtOpnd);
-  if (Res != MatchOperand_Success)
+  if (!Res.isSuccess())
     return Res;
 
   auto Ext = static_cast<AArch64Operand *>(ExtOpnd.back().get());
   Operands.push_back(AArch64Operand::CreateVectorReg(
       RegNum, RegKind::SVEDataVector, ElementWidth, S, Ext->getEndLoc(),
       getContext(), Ext->getShiftExtendType(), Ext->getShiftExtendAmount(),
       Ext->hasShiftExtendAmount()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseSVEPattern(OperandVector &Operands) {
   MCAsmParser &Parser = getParser();
 
   SMLoc SS = getLoc();
   const AsmToken &TokE = getTok();
   bool IsHash = TokE.is(AsmToken::Hash);
 
   if (!IsHash && TokE.isNot(AsmToken::Identifier))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   int64_t Pattern;
   if (IsHash) {
     Lex(); // Eat hash
 
     // Parse the immediate operand.
     const MCExpr *ImmVal;
     SS = getLoc();
     if (Parser.parseExpression(ImmVal))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     auto *MCE = dyn_cast<MCConstantExpr>(ImmVal);
     if (!MCE)
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     Pattern = MCE->getValue();
   } else {
     // Parse the pattern
     auto Pat = AArch64SVEPredPattern::lookupSVEPREDPATByName(TokE.getString());
     if (!Pat)
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
 
     Lex();
     Pattern = Pat->Encoding;
     assert(Pattern >= 0 && Pattern < 32);
   }
 
   Operands.push_back(
       AArch64Operand::CreateImm(MCConstantExpr::create(Pattern, getContext()),
                                 SS, getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
+ParseStatus
 AArch64AsmParser::tryParseSVEVecLenSpecifier(OperandVector &Operands) {
   int64_t Pattern;
   SMLoc SS = getLoc();
   const AsmToken &TokE = getTok();
   // Parse the pattern
   auto Pat = AArch64SVEVecLenSpecifier::lookupSVEVECLENSPECIFIERByName(
       TokE.getString());
   if (!Pat)
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   Lex();
   Pattern = Pat->Encoding;
   assert(Pattern >= 0 && Pattern <= 1 && "Pattern does not exist");
 
   Operands.push_back(
       AArch64Operand::CreateImm(MCConstantExpr::create(Pattern, getContext()),
                                 SS, getLoc(), getContext()));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseGPR64x8(OperandVector &Operands) {
   SMLoc SS = getLoc();
 
   MCRegister XReg;
-  if (tryParseScalarRegister(XReg) != MatchOperand_Success)
-    return MatchOperand_NoMatch;
+  if (!tryParseScalarRegister(XReg).isSuccess())
+    return ParseStatus::NoMatch;
 
   MCContext &ctx = getContext();
   const MCRegisterInfo *RI = ctx.getRegisterInfo();
   int X8Reg = RI->getMatchingSuperReg(
       XReg, AArch64::x8sub_0,
       &AArch64MCRegisterClasses[AArch64::GPR64x8ClassRegClassID]);
-  if (!X8Reg) {
-    Error(SS, "expected an even-numbered x-register in the range [x0,x22]");
-    return MatchOperand_ParseFail;
-  }
+  if (!X8Reg)
+    return Error(SS,
+                 "expected an even-numbered x-register in the range [x0,x22]");
 
   Operands.push_back(
       AArch64Operand::CreateReg(X8Reg, RegKind::Scalar, SS, getLoc(), ctx));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
-OperandMatchResultTy
-AArch64AsmParser::tryParseImmRange(OperandVector &Operands) {
+ParseStatus AArch64AsmParser::tryParseImmRange(OperandVector &Operands) {
   SMLoc S = getLoc();
 
   if (getTok().isNot(AsmToken::Integer))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   if (getLexer().peekTok().isNot(AsmToken::Colon))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   const MCExpr *ImmF;
   if (getParser().parseExpression(ImmF))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   if (getTok().isNot(AsmToken::Colon))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   Lex(); // Eat ':'
   if (getTok().isNot(AsmToken::Integer))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   SMLoc E = getTok().getLoc();
   const MCExpr *ImmL;
   if (getParser().parseExpression(ImmL))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   unsigned ImmFVal = dyn_cast<MCConstantExpr>(ImmF)->getValue();
   unsigned ImmLVal = dyn_cast<MCConstantExpr>(ImmL)->getValue();
 
   Operands.push_back(
       AArch64Operand::CreateImmRange(ImmFVal, ImmLVal, S, E, getContext()));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }