[SystemZ] Replace OperandMatchResultTy with ParseStatus (NFC)

[barannikov88]

Summary

ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:

return Error(L, "msg");

when with MatchOperandResultTy it had to be:

Error(L, "msg");
return MatchOperand_ParseFail;

It also has more appropriate name since parse* methods are not only for
parsing operands.

[barannikov88]

ping

[iii]

The change looks good to me; the other arches apparently use either bool or ParseStatus here.

But only Uli can approve this, so let's wait for his opinion.

[uweigand]

Sure, this looks like a nice cleanup - thanks! LGTM.

llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp

SystemZTargetStreamer &getTargetStreamer() {
     MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
     return static_cast<SystemZTargetStreamer &>(TS);
   }
 
   bool parseRegister(Register &Reg, bool RestoreOnFailure = false);
 
   bool parseIntegerRegister(Register &Reg, RegisterGroup Group);
 
-  OperandMatchResultTy parseRegister(OperandVector &Operands,
-                                     RegisterKind Kind);
+  ParseStatus parseRegister(OperandVector &Operands, RegisterKind Kind);
 
-  OperandMatchResultTy parseAnyRegister(OperandVector &Operands);
+  ParseStatus parseAnyRegister(OperandVector &Operands);
 
   bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2,
                     Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length,
                     bool HasLength = false, bool HasVectorIndex = false);
   bool parseAddressRegister(Register &Reg);
 
   bool ParseDirectiveInsn(SMLoc L);
   bool ParseDirectiveMachine(SMLoc L);
   bool ParseGNUAttribute(SMLoc L);
 
-  OperandMatchResultTy parseAddress(OperandVector &Operands,
-                                    MemoryKind MemKind,
-                                    RegisterKind RegKind);
+  ParseStatus parseAddress(OperandVector &Operands, MemoryKind MemKind,
 
-  OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
-                                  int64_t MaxVal, bool AllowTLS);
+  ParseStatus parsePCRel(OperandVector &Operands, int64_t MinVal,
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   // Both the hlasm and att variants still rely on the basic gnu asm
   // format with respect to inputs, clobbers, outputs etc.
   //
   // However, calling the overriden getAssemblerDialect() method in
   // AsmParser is problematic. It either returns the AssemblerDialect field
bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
   bool isLabel(AsmToken &Token) override;
 
   // Used by the TableGen code to parse particular operand types.
-  OperandMatchResultTy parseGR32(OperandVector &Operands) {
+  ParseStatus parseGR32(OperandVector &Operands) {
     return parseRegister(Operands, GR32Reg);
   }
-  OperandMatchResultTy parseGRH32(OperandVector &Operands) {
+  ParseStatus parseGRH32(OperandVector &Operands) {
     return parseRegister(Operands, GRH32Reg);
   }
-  OperandMatchResultTy parseGRX32(OperandVector &Operands) {
+  ParseStatus parseGRX32(OperandVector &Operands) {
     llvm_unreachable("GRX32 should only be used for pseudo instructions");
   }
-  OperandMatchResultTy parseGR64(OperandVector &Operands) {
+  ParseStatus parseGR64(OperandVector &Operands) {
     return parseRegister(Operands, GR64Reg);
   }
-  OperandMatchResultTy parseGR128(OperandVector &Operands) {
+  ParseStatus parseGR128(OperandVector &Operands) {
     return parseRegister(Operands, GR128Reg);
   }
-  OperandMatchResultTy parseADDR32(OperandVector &Operands) {
+  ParseStatus parseADDR32(OperandVector &Operands) {
     // For the AsmParser, we will accept %r0 for ADDR32 as well.
     return parseRegister(Operands, GR32Reg);
   }
-  OperandMatchResultTy parseADDR64(OperandVector &Operands) {
+  ParseStatus parseADDR64(OperandVector &Operands) {
     // For the AsmParser, we will accept %r0 for ADDR64 as well.
     return parseRegister(Operands, GR64Reg);
   }
-  OperandMatchResultTy parseADDR128(OperandVector &Operands) {
+  ParseStatus parseADDR128(OperandVector &Operands) {
     llvm_unreachable("Shouldn't be used as an operand");
   }
-  OperandMatchResultTy parseFP32(OperandVector &Operands) {
+  ParseStatus parseFP32(OperandVector &Operands) {
     return parseRegister(Operands, FP32Reg);
   }
-  OperandMatchResultTy parseFP64(OperandVector &Operands) {
+  ParseStatus parseFP64(OperandVector &Operands) {
     return parseRegister(Operands, FP64Reg);
   }
-  OperandMatchResultTy parseFP128(OperandVector &Operands) {
+  ParseStatus parseFP128(OperandVector &Operands) {
     return parseRegister(Operands, FP128Reg);
   }
-  OperandMatchResultTy parseVR32(OperandVector &Operands) {
+  ParseStatus parseVR32(OperandVector &Operands) {
     return parseRegister(Operands, VR32Reg);
   }
-  OperandMatchResultTy parseVR64(OperandVector &Operands) {
+  ParseStatus parseVR64(OperandVector &Operands) {
     return parseRegister(Operands, VR64Reg);
   }
-  OperandMatchResultTy parseVF128(OperandVector &Operands) {
+  ParseStatus parseVF128(OperandVector &Operands) {
     llvm_unreachable("Shouldn't be used as an operand");
   }
-  OperandMatchResultTy parseVR128(OperandVector &Operands) {
+  ParseStatus parseVR128(OperandVector &Operands) {
     return parseRegister(Operands, VR128Reg);
   }
-  OperandMatchResultTy parseAR32(OperandVector &Operands) {
+  ParseStatus parseAR32(OperandVector &Operands) {
     return parseRegister(Operands, AR32Reg);
   }
-  OperandMatchResultTy parseCR64(OperandVector &Operands) {
+  ParseStatus parseCR64(OperandVector &Operands) {
     return parseRegister(Operands, CR64Reg);
   }
-  OperandMatchResultTy parseAnyReg(OperandVector &Operands) {
+  ParseStatus parseAnyReg(OperandVector &Operands) {
     return parseAnyRegister(Operands);
   }
-  OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
+  ParseStatus parseBDAddr32(OperandVector &Operands) {
     return parseAddress(Operands, BDMem, GR32Reg);
   }
-  OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
+  ParseStatus parseBDAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDMem, GR64Reg);
   }
-  OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
+  ParseStatus parseBDXAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDXMem, GR64Reg);
   }
-  OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
+  ParseStatus parseBDLAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDLMem, GR64Reg);
   }
-  OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) {
+  ParseStatus parseBDRAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDRMem, GR64Reg);
   }
-  OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) {
+  ParseStatus parseBDVAddr64(OperandVector &Operands) {
     return parseAddress(Operands, BDVMem, GR64Reg);
   }
-  OperandMatchResultTy parsePCRel12(OperandVector &Operands) {
+  ParseStatus parsePCRel12(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false);
   }
-  OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
+  ParseStatus parsePCRel16(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false);
   }
-  OperandMatchResultTy parsePCRel24(OperandVector &Operands) {
+  ParseStatus parsePCRel24(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false);
   }
-  OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
+  ParseStatus parsePCRel32(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false);
   }
-  OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) {
+  ParseStatus parsePCRelTLS16(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true);
   }
-  OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) {
+  ParseStatus parsePCRelTLS32(OperandVector &Operands) {
     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true);
   }
 };
 
 } // end anonymous namespace
 
 #define GET_REGISTER_MATCHER
 #define GET_SUBTARGET_FEATURE_NAME
bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) {
   }
 
   Reg.EndLoc = Parser.getTok().getLoc();
   Parser.Lex();
   return false;
 }
 
 // Parse a register of kind Kind and add it to Operands.
-OperandMatchResultTy
-SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) {
+ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
+                                            RegisterKind Kind) {
   Register Reg;
   RegisterGroup Group;
   switch (Kind) {
   case GR32Reg:
   case GRH32Reg:
   case GR64Reg:
   case GR128Reg:
     Group = RegGR;
ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
   case CR64Reg:
     Group = RegCR;
     break;
   }
 
   // Handle register names of the form %<prefix><number>
   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
     if (parseRegister(Reg))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     // Check the parsed register group "Reg.Group" with the expected "Group"
     // Have to error out if user specified wrong prefix.
     switch (Group) {
     case RegGR:
     case RegFP:
     case RegAR:
     case RegCR:
-      if (Group != Reg.Group) {
-        Error(Reg.StartLoc, "invalid operand for instruction");
-        return MatchOperand_ParseFail;
-      }
+      if (Group != Reg.Group)
+        return Error(Reg.StartLoc, "invalid operand for instruction");
       break;
     case RegV:
-      if (Reg.Group != RegV && Reg.Group != RegFP) {
-        Error(Reg.StartLoc, "invalid operand for instruction");
-        return MatchOperand_ParseFail;
-      }
+      if (Reg.Group != RegV && Reg.Group != RegFP)
+        return Error(Reg.StartLoc, "invalid operand for instruction");
       break;
     }
   } else if (Parser.getTok().is(AsmToken::Integer)) {
     if (parseIntegerRegister(Reg, Group))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
   }
   // Otherwise we didn't match a register operand.
   else
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   // Determine the LLVM register number according to Kind.
   const unsigned *Regs;
   switch (Kind) {
   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
   case GRH32Reg: Regs = SystemZMC::GRH32Regs; break;
   case GR64Reg:  Regs = SystemZMC::GR64Regs;  break;
   case GR128Reg: Regs = SystemZMC::GR128Regs; break;
   case FP32Reg:  Regs = SystemZMC::FP32Regs;  break;
   case FP64Reg:  Regs = SystemZMC::FP64Regs;  break;
   case FP128Reg: Regs = SystemZMC::FP128Regs; break;
   case VR32Reg:  Regs = SystemZMC::VR32Regs;  break;
   case VR64Reg:  Regs = SystemZMC::VR64Regs;  break;
   case VR128Reg: Regs = SystemZMC::VR128Regs; break;
   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
   }
-  if (Regs[Reg.Num] == 0) {
-    Error(Reg.StartLoc, "invalid register pair");
-    return MatchOperand_ParseFail;
-  }
+  if (Regs[Reg.Num] == 0)
+    return Error(Reg.StartLoc, "invalid register pair");
 
   Operands.push_back(
       SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 // Parse any type of register (including integers) and add it to Operands.
-OperandMatchResultTy
-SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
+ParseStatus SystemZAsmParser::parseAnyRegister(OperandVector &Operands) {
   SMLoc StartLoc = Parser.getTok().getLoc();
 
   // Handle integer values.
   if (Parser.getTok().is(AsmToken::Integer)) {
     const MCExpr *Register;
     if (Parser.parseExpression(Register))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
     if (auto *CE = dyn_cast<MCConstantExpr>(Register)) {
       int64_t Value = CE->getValue();
-      if (Value < 0 || Value > 15) {
-        Error(StartLoc, "invalid register");
-        return MatchOperand_ParseFail;
-      }
+      if (Value < 0 || Value > 15)
+        return Error(StartLoc, "invalid register");
     }
 
     SMLoc EndLoc =
       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 
     Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc));
   }
   else {
     if (isParsingHLASM())
-      return MatchOperand_NoMatch;
+      return ParseStatus::NoMatch;
 
     Register Reg;
     if (parseRegister(Reg))
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
 
-    if (Reg.Num > 15) {
-      Error(StartLoc, "invalid register");
-      return MatchOperand_ParseFail;
-    }
+    if (Reg.Num > 15)
+      return Error(StartLoc, "invalid register");
 
     // Map to the correct register kind.
     RegisterKind Kind;
     unsigned RegNo;
     if (Reg.Group == RegGR) {
       Kind = GR64Reg;
       RegNo = SystemZMC::GR64Regs[Reg.Num];
     }
else if (Reg.Group == RegAR) {
       Kind = AR32Reg;
       RegNo = SystemZMC::AR32Regs[Reg.Num];
     }
     else if (Reg.Group == RegCR) {
       Kind = CR64Reg;
       RegNo = SystemZMC::CR64Regs[Reg.Num];
     }
     else {
-      return MatchOperand_ParseFail;
+      return ParseStatus::Failure;
     }
 
     Operands.push_back(SystemZOperand::createReg(Kind, RegNo,
                                                  Reg.StartLoc, Reg.EndLoc));
   }
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 bool SystemZAsmParser::parseIntegerRegister(Register &Reg,
                                             RegisterGroup Group) {
   Reg.StartLoc = Parser.getTok().getLoc();
   // We have an integer token
   const MCExpr *Register;
   if (Parser.parseExpression(Register))
if (Reg.Group == RegV) {
     Error(Reg.StartLoc, "invalid address register");
     return true;
   }
   return false;
 }
 
 // Parse a memory operand and add it to Operands.  The other arguments
 // are as above.
-OperandMatchResultTy
-SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind,
+ParseStatus SystemZAsmParser::parseAddress(OperandVector &Operands,
+                                           MemoryKind MemKind,
                                            RegisterKind RegKind) {
   SMLoc StartLoc = Parser.getTok().getLoc();
   unsigned Base = 0, Index = 0, LengthReg = 0;
   Register Reg1, Reg2;
   bool HaveReg1, HaveReg2;
   const MCExpr *Disp;
   const MCExpr *Length;
 
   bool HasLength = (MemKind == BDLMem) ? true : false;
   bool HasVectorIndex = (MemKind == BDVMem) ? true : false;
   if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength,
                    HasVectorIndex))
-    return MatchOperand_ParseFail;
+    return ParseStatus::Failure;
 
   const unsigned *Regs;
   switch (RegKind) {
   case GR32Reg: Regs = SystemZMC::GR32Regs; break;
   case GR64Reg: Regs = SystemZMC::GR64Regs; break;
   default: llvm_unreachable("invalid RegKind");
   }
 
   switch (MemKind) {
   case BDMem:
     // If we have Reg1, it must be an address register.
     if (HaveReg1) {
       if (parseAddressRegister(Reg1))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       Base = Regs[Reg1.Num];
     }
     // There must be no Reg2.
-    if (HaveReg2) {
-      Error(StartLoc, "invalid use of indexed addressing");
-      return MatchOperand_ParseFail;
-    }
+    if (HaveReg2)
+      return Error(StartLoc, "invalid use of indexed addressing");
     break;
   case BDXMem:
     // If we have Reg1, it must be an address register.
     if (HaveReg1) {
       if (parseAddressRegister(Reg1))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       // If the are two registers, the first one is the index and the
       // second is the base.
       if (HaveReg2)
         Index = Regs[Reg1.Num];
       else
         Base = Regs[Reg1.Num];
     }
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       Base = Regs[Reg2.Num];
     }
     break;
   case BDLMem:
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       Base = Regs[Reg2.Num];
     }
     // We cannot support base+index addressing.
-    if (HaveReg1 && HaveReg2) {
-      Error(StartLoc, "invalid use of indexed addressing");
-      return MatchOperand_ParseFail;
-    }
+    if (HaveReg1 && HaveReg2)
+      return Error(StartLoc, "invalid use of indexed addressing");
     // We must have a length.
-    if (!Length) {
-      Error(StartLoc, "missing length in address");
-      return MatchOperand_ParseFail;
-    }
+    if (!Length)
+      return Error(StartLoc, "missing length in address");
     break;
   case BDRMem:
     // We must have Reg1, and it must be a GPR.
-    if (!HaveReg1 || Reg1.Group != RegGR) {
-      Error(StartLoc, "invalid operand for instruction");
-      return MatchOperand_ParseFail;
-    }
+    if (!HaveReg1 || Reg1.Group != RegGR)
+      return Error(StartLoc, "invalid operand for instruction");
     LengthReg = SystemZMC::GR64Regs[Reg1.Num];
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       Base = Regs[Reg2.Num];
     }
     break;
   case BDVMem:
     // We must have Reg1, and it must be a vector register.
-    if (!HaveReg1 || Reg1.Group != RegV) {
-      Error(StartLoc, "vector index required in address");
-      return MatchOperand_ParseFail;
-    }
+    if (!HaveReg1 || Reg1.Group != RegV)
+      return Error(StartLoc, "vector index required in address");
     Index = SystemZMC::VR128Regs[Reg1.Num];
     // If we have Reg2, it must be an address register.
     if (HaveReg2) {
       if (parseAddressRegister(Reg2))
-        return MatchOperand_ParseFail;
+        return ParseStatus::Failure;
       Base = Regs[Reg2.Num];
     }
     break;
   }
 
   SMLoc EndLoc =
       SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
   Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp,
                                                Index, Length, LengthReg,
                                                StartLoc, EndLoc));
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 ParseStatus SystemZAsmParser::parseDirective(AsmToken DirectiveID) {
   StringRef IDVal = DirectiveID.getIdentifier();
 
   if (IDVal == ".insn")
     return ParseDirectiveInsn(DirectiveID.getLoc());
   if (IDVal == ".machine")
for (int i = 0; i < Entry->NumOperands; i++) {
     SMLoc StartLoc = Parser.getTok().getLoc();
 
     // Always expect commas as separators for operands.
     if (getLexer().isNot(AsmToken::Comma))
       return Error(StartLoc, "unexpected token in directive");
     Lex();
 
     // Parse operands.
-    OperandMatchResultTy ResTy;
+    ParseStatus ResTy;
     if (Kind == MCK_AnyReg)
       ResTy = parseAnyReg(Operands);
     else if (Kind == MCK_VR128)
       ResTy = parseVR128(Operands);
     else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20)
       ResTy = parseBDXAddr64(Operands);
     else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20)
       ResTy = parseBDAddr64(Operands);
else {
       // Expect immediate expression.
       if (Parser.parseExpression(Expr))
         return Error(StartLoc, "unexpected token in directive");
 
       SMLoc EndLoc =
         SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 
       Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
-      ResTy = MatchOperand_Success;
+      ResTy = ParseStatus::Success;
     }
 
-    if (ResTy != MatchOperand_Success)
+    if (!ResTy.isSuccess())
       return true;
   }
 
   // Build the instruction with the parsed operands.
   MCInst Inst = MCInstBuilder(Entry->Opcode);
 
   for (size_t i = 0; i < Operands.size(); i++) {
     MCParsedAsmOperand &Operand = *Operands[i];
bool SystemZAsmParser::parseOperand(OperandVector &Operands,
   // custom parse the operand, or fallback to the general approach.  Force all
   // features to be available during the operand check, or else we will fail to
   // find the custom parser, and then we will later get an InvalidOperand error
   // instead of a MissingFeature errror.
   FeatureBitset AvailableFeatures = getAvailableFeatures();
   FeatureBitset All;
   All.set();
   setAvailableFeatures(All);
-  OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
+  ParseStatus Res = MatchOperandParserImpl(Operands, Mnemonic);
   setAvailableFeatures(AvailableFeatures);
-  if (ResTy == MatchOperand_Success)
+  if (Res.isSuccess())
     return false;
 
   // If there wasn't a custom match, try the generic matcher below. Otherwise,
   // there was a match, but an error occurred, in which case, just return that
   // the operand parsing failed.
-  if (ResTy == MatchOperand_ParseFail)
+  if (Res.isFailure())
     return true;
 
   // Check for a register.  All real register operands should have used
   // a context-dependent parse routine, which gives the required register
   // class.  The code is here to mop up other cases, like those where
   // the instruction isn't recognized.
   if (isParsingATT() && Parser.getTok().is(AsmToken::Percent)) {
     Register Reg;
case Match_MnemonicFail: {
     return Error(IDLoc, "invalid instruction" + Suggestion,
                  ((SystemZOperand &)*Operands[0]).getLocRange());
   }
   }
 
   llvm_unreachable("Unexpected match type");
 }
 
-OperandMatchResultTy
-SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
-                             int64_t MaxVal, bool AllowTLS) {
+ParseStatus SystemZAsmParser::parsePCRel(OperandVector &Operands,
+                                         int64_t MinVal, int64_t MaxVal,
+                                         bool AllowTLS) {
   MCContext &Ctx = getContext();
   MCStreamer &Out = getStreamer();
   const MCExpr *Expr;
   SMLoc StartLoc = Parser.getTok().getLoc();
   if (getParser().parseExpression(Expr))
-    return MatchOperand_NoMatch;
+    return ParseStatus::NoMatch;
 
   auto isOutOfRangeConstant = [&](const MCExpr *E, bool Negate) -> bool {
     if (auto *CE = dyn_cast<MCConstantExpr>(E)) {
       int64_t Value = CE->getValue();
       if (Negate)
         Value = -Value;
       if ((Value & 1) || Value < MinVal || Value > MaxVal)
         return true;
     }
     return false;
   };
 
   // For consistency with the GNU assembler, treat immediates as offsets
   // from ".".
   if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
-    if (isParsingHLASM()) {
-      Error(StartLoc, "Expected PC-relative expression");
-      return MatchOperand_ParseFail;
-    }
-    if (isOutOfRangeConstant(CE, false)) {
-      Error(StartLoc, "offset out of range");
-      return MatchOperand_ParseFail;
-    }
+    if (isParsingHLASM())
+      return Error(StartLoc, "Expected PC-relative expression");
+    if (isOutOfRangeConstant(CE, false))
+      return Error(StartLoc, "offset out of range");
     int64_t Value = CE->getValue();
     MCSymbol *Sym = Ctx.createTempSymbol();
     Out.emitLabel(Sym);
     const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None,
                                                  Ctx);
     Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx);
   }
 
   // For consistency with the GNU assembler, conservatively assume that a
   // constant offset must by itself be within the given size range.
   if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr))
     if (isOutOfRangeConstant(BE->getLHS(), false) ||
         isOutOfRangeConstant(BE->getRHS(),
-                             BE->getOpcode() == MCBinaryExpr::Sub)) {
-      Error(StartLoc, "offset out of range");
-      return MatchOperand_ParseFail;
-    }
+                             BE->getOpcode() == MCBinaryExpr::Sub))
+      return Error(StartLoc, "offset out of range");
 
   // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol.
   const MCExpr *Sym = nullptr;
   if (AllowTLS && getLexer().is(AsmToken::Colon)) {
     Parser.Lex();
 
-    if (Parser.getTok().isNot(AsmToken::Identifier)) {
-      Error(Parser.getTok().getLoc(), "unexpected token");
-      return MatchOperand_ParseFail;
-    }
+    if (Parser.getTok().isNot(AsmToken::Identifier))
+      return Error(Parser.getTok().getLoc(), "unexpected token");
 
     MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None;
     StringRef Name = Parser.getTok().getString();
     if (Name == "tls_gdcall")
       Kind = MCSymbolRefExpr::VK_TLSGD;
     else if (Name == "tls_ldcall")
       Kind = MCSymbolRefExpr::VK_TLSLDM;
-    else {
-      Error(Parser.getTok().getLoc(), "unknown TLS tag");
-      return MatchOperand_ParseFail;
-    }
+    else
+      return Error(Parser.getTok().getLoc(), "unknown TLS tag");
     Parser.Lex();
 
-    if (Parser.getTok().isNot(AsmToken::Colon)) {
-      Error(Parser.getTok().getLoc(), "unexpected token");
-      return MatchOperand_ParseFail;
-    }
+    if (Parser.getTok().isNot(AsmToken::Colon))
+      return Error(Parser.getTok().getLoc(), "unexpected token");
     Parser.Lex();
 
-    if (Parser.getTok().isNot(AsmToken::Identifier)) {
-      Error(Parser.getTok().getLoc(), "unexpected token");
-      return MatchOperand_ParseFail;
-    }
+    if (Parser.getTok().isNot(AsmToken::Identifier))
+      return Error(Parser.getTok().getLoc(), "unexpected token");
 
     StringRef Identifier = Parser.getTok().getString();
     Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier),
                                   Kind, Ctx);
     Parser.Lex();
   }
 
   SMLoc EndLoc =
     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
 
   if (AllowTLS)
     Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym,
                                                     StartLoc, EndLoc));
   else
     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
 
-  return MatchOperand_Success;
+  return ParseStatus::Success;
 }
 
 bool SystemZAsmParser::isLabel(AsmToken &Token) {
   if (isParsingATT())
     return true;
 
   // HLASM labels are ordinary symbols.
   // An HLASM label always starts at column 1.