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Differential D154245

[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
ClosedPublic

Authored by reames on Jun 30 2023, 11:33 AM.

Details

Reviewers
craig.topper
asb
frasercrmck
kito-cheng
luke
Commits
rG5cd41dc62db7: [RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
Summary

This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295.

This change handles most of the binary pseudos. I excluded pseudos which _TIED variants, and those that produce mask results. Both a bit different in functionality, and deserve their own change and review. As with previous changes in the series, we replace the existing TA and TU forms with a single unified pseudo with a passthru (which may be implicit_def) and a policy operand.

As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions.

Diff Detail

Event Timeline

reames created this revision.Jun 30 2023, 11:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 30 2023, 11:33 AM
Herald added subscribers: jobnoorman, VincentWu, vkmr and 28 others. · View Herald Transcript
reames requested review of this revision.Jun 30 2023, 11:33 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 30 2023, 11:33 AM
Herald added subscribers: wangpc, eopXD, MaskRay. · View Herald Transcript
reames added a parent revision: D154141: [RISCV] Remove legacy TA/TU pseudo distinction for load instructions.Jun 30 2023, 11:33 AM
Harbormaster completed remote builds in B242487: Diff 536337.Jun 30 2023, 11:34 AM
reames updated this revision to Diff 537528.Jul 5 2023, 3:39 PM
reames edited the summary of this revision. (Show Details)

Manually updated MIR tests

Harbormaster completed remote builds in B243333: Diff 537528.Jul 5 2023, 4:50 PM
reames updated this revision to Diff 537554.Jul 5 2023, 5:44 PM

Add in RoundingMode variants.

Harbormaster completed remote builds in B243352: Diff 537554.Jul 5 2023, 6:42 PM
reames mentioned this in D154620: [RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge refactoring [nfc].Jul 6 2023, 9:06 AM
reames added a child revision: D154620: [RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge refactoring [nfc].
craig.topper added inline comments.Jul 7 2023, 4:14 PM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

What happens if we don't use undef here?

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
729

Add a FIXME here so we can find it later. Unless you're planning to fix it.

llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
37–38

Should this be IMPLICIT_DEF instead? I see some other IMPLICIT_DEFs and no undefs in the existing code.

llvm/test/CodeGen/RISCV/rvv/vxrm.mir
1

Is this test no longer generated by the script?

reames added inline comments.Jul 10 2023, 7:31 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

If I remember correctly, you get a verifier error due to a use before definition.

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
729

I'm not, so will do.

llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir
37–38

Looks like it yeah. I got confused because this is post InsertVSETVLI. Seeing implicit vtype and implicit vl almost always means your post regalloc, and I apparently didn't look close enough. Update pending.

llvm/test/CodeGen/RISCV/rvv/vxrm.mir
1

From what I could tell, it wasn't before. It just had the header. Or at least, auto-update didn't appear to work in any meaningful way.

reames updated this revision to Diff 538653.Jul 10 2023, 8:07 AM

Address review comments

Harbormaster completed remote builds in B244149: Diff 538653.Jul 10 2023, 8:08 AM
craig.topper mentioned this in D152996: [RISCV][POC] Model frm control for vfadd.Jul 10 2023, 11:31 AM
craig.topper added inline comments.Jul 10 2023, 11:38 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

Shouldn't we be using the register from Operand 1 not Operand 0?

craig.topper mentioned this in D154629: [2/8][RISCV] Add rounding mode control variant for vfwadd, vfwsub.Jul 10 2023, 12:26 PM
reames added inline comments.Jul 11 2023, 8:03 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

Not unless I'm missing something?

We're forming the non-tied form of the instruction here. This used to be the unsuffixed (TA) version, and thus the merge was implicitly undef. With the new representation, we have the policy and merge operands. We have to explicitly form the undef merge operand.

Since the operand is undef, it can be any register whose class matches the def, but it conceptually makes the most sense to me to have this be the destination register given that's what it's tied to. I believe that using 0 or 1 here is NFC, provided it's flagged undef. If you have a strong preference here, I'm happy to change.

reames added inline comments.Jul 11 2023, 8:12 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

Actually, using operand 1 isn't allowed by the verifier. It's checked in MachineVerifier.cpp like so.

unsigned DefIdx;
if (MF->getProperties().hasProperty(
        MachineFunctionProperties::Property::TiedOpsRewritten) &&
    MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
    Reg != MI->getOperand(DefIdx).getReg())
  report("Two-address instruction operands must be identical", MO, MONum);
reames added a child revision: D154857: [RISCV] In RISCVRVVInitUndef, optimize case where entire register is undef.Jul 11 2023, 8:21 AM
craig.topper accepted this revision.Jul 11 2023, 9:39 AM

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
2543

Ok I wasn't quite sure what side of the transition out of SSA we're on and what the Two-Address instruction pass will do after this call.

I think based on what you've said, operand 0 with undef is correct. Thanks.

This revision is now accepted and ready to land.Jul 11 2023, 9:39 AM
This revision was landed with ongoing or failed builds.Jul 11 2023, 10:21 AM
Closed by commit rG5cd41dc62db7: [RISCV] Remove legacy TA/TU pseudo distinction for binary instructions (authored by reames). · Explain Why
This revision was automatically updated to reflect the committed changes.
reames added a commit: rG5cd41dc62db7: [RISCV] Remove legacy TA/TU pseudo distinction for binary instructions.
reames mentioned this in rG95d62344c0eb: [RISCV] Cleanup dead complexity in RISCVMaskedPseudo after TA/TU merge….Jul 11 2023, 10:33 AM

Revision Contents

Diff 539176

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

Show First 20 Lines • Show All 2,534 Lines • ▼ Show 20 Lines case CASE_WIDEOP_OPCODE_LMULS(WSUBU_WV): {
CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV) CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUB_WV)
CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV) CASE_WIDEOP_CHANGE_OPCODE_LMULS(WSUBU_WV)
} }
// clang-format on // clang-format on
MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock &MBB = *MI.getParent();
MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc)) MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), get(NewOpc))
.add(MI.getOperand(0)) .add(MI.getOperand(0))
.addReg(MI.getOperand(0).getReg(), RegState::Undef)
craig.topperUnsubmitted
Not Done
ReplyInline Actions

What happens if we don't use undef here?

craig.topper: What happens if we don't use undef here?
reamesAuthorUnsubmitted
Done
ReplyInline Actions

If I remember correctly, you get a verifier error due to a use before definition.

reames: If I remember correctly, you get a verifier error due to a use before definition.
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Shouldn't we be using the register from Operand 1 not Operand 0?

craig.topper: Shouldn't we be using the register from Operand 1 not Operand 0?
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Not unless I'm missing something?

We're forming the non-tied form of the instruction here. This used to be the unsuffixed (TA) version, and thus the merge was implicitly undef. With the new representation, we have the policy and merge operands. We have to explicitly form the undef merge operand.

Since the operand is undef, it can be any register whose class matches the def, but it conceptually makes the most sense to me to have this be the destination register given that's what it's tied to. I believe that using 0 or 1 here is NFC, provided it's flagged undef. If you have a strong preference here, I'm happy to change.

reames: Not unless I'm missing something? We're forming the non-tied form of the instruction here.
reamesAuthorUnsubmitted
Done
ReplyInline Actions

Actually, using operand 1 isn't allowed by the verifier. It's checked in MachineVerifier.cpp like so.

unsigned DefIdx;
if (MF->getProperties().hasProperty(
        MachineFunctionProperties::Property::TiedOpsRewritten) &&
    MO->isUse() && MI->isRegTiedToDefOperand(MONum, &DefIdx) &&
    Reg != MI->getOperand(DefIdx).getReg())
  report("Two-address instruction operands must be identical", MO, MONum);
reames: Actually, using operand 1 isn't allowed by the verifier. It's checked in MachineVerifier.cpp…
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Ok I wasn't quite sure what side of the transition out of SSA we're on and what the Two-Address instruction pass will do after this call.

I think based on what you've said, operand 0 with undef is correct. Thanks.

craig.topper: Ok I wasn't quite sure what side of the transition out of SSA we're on and what the Two-Address…
.add(MI.getOperand(1)) .add(MI.getOperand(1))
.add(MI.getOperand(2)) .add(MI.getOperand(2))
.add(MI.getOperand(3)) .add(MI.getOperand(3))
.add(MI.getOperand(4)); .add(MI.getOperand(4))
.add(MI.getOperand(5));
MIB.copyImplicitOps(MI); MIB.copyImplicitOps(MI);
if (LV) { if (LV) {
unsigned NumOps = MI.getNumOperands(); unsigned NumOps = MI.getNumOperands();
for (unsigned I = 1; I < NumOps; ++I) { for (unsigned I = 1; I < NumOps; ++I) {
MachineOperand &Op = MI.getOperand(I); MachineOperand &Op = MI.getOperand(I);
if (Op.isReg() && Op.isKill()) if (Op.isReg() && Op.isKill())
LV->replaceKillInstruction(Op.getReg(), MI, *MIB); LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
▲ Show 20 Lines • Show All 239 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,105 Lines • ▼ Show 20 Linesclass VPseudoBinaryNoMaskTU<VReg RetClass,
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
} }
class VPseudoBinaryNoMaskRoundingMode<VReg RetClass, class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasRoundModeOp = 1;
}
class VPseudoBinaryNoMaskTURoundingMode<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm, (ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ","); let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
▲ Show 20 Lines • Show All 117 Lines • ▼ Show 20 Linesclass VPseudoTernaryMaskPolicy<VReg RetClass,
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ","); let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
} }
// Like VPseudoBinaryNoMask, but output can be V0.
class VPseudoBinaryMOutNoMask<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let HasVLOp = 1;
let HasSEWOp = 1;
}
// Like VPseudoBinaryMask, but output can be V0. // Like VPseudoBinaryMask, but output can be V0.
class VPseudoBinaryMOutMask<VReg RetClass, class VPseudoBinaryMOutMask<VReg RetClass,
RegisterClass Op1Class, RegisterClass Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
string Constraint> : string Constraint> :
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, (ins RetClass:$merge,
Op1Class:$rs2, Op2Class:$rs1, Op1Class:$rs2, Op2Class:$rs1,
▲ Show 20 Lines • Show All 598 Lines • ▼ Show 20 Lines
multiclass VPseudoBinary<VReg RetClass, multiclass VPseudoBinary<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
int sew = 0> { int sew = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
Constraint>;
def suffix # "_TU" : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>; RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false,
/*IsCombined*/ true>;
} }
} }
multiclass VPseudoBinaryRoundingMode<VReg RetClass, multiclass VPseudoBinaryRoundingMode<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = "", string Constraint = "",
int sew = 0> { int sew = 0> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class, def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
def suffix # "_TU" :VPseudoBinaryNoMaskTURoundingMode<RetClass,
Op1Class, Op2Class,
Constraint>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass, def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass,
Op1Class, Op1Class,
Op2Class, Op2Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>; RISCVMaskedPseudo</*MaskOpIdx*/ 3,
/*HasTU*/false,
/*IsCombined*/true>;
} }
} }
multiclass VPseudoBinaryM<VReg RetClass, multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
let ForceTailAgnostic = true in let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>, Op2Class, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false>; RISCVMaskedPseudo</*MaskOpIdx*/ 3, /*HasTU*/ false>;
} }
} }
multiclass VPseudoBinaryEmul<VReg RetClass, multiclass VPseudoBinaryEmul<VReg RetClass,
VReg Op1Class, VReg Op1Class,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo lmul, LMULInfo lmul,
LMULInfo emul, LMULInfo emul,
string Constraint = "", string Constraint = "",
int sew = 0> { int sew = 0> {
let VLMul = lmul.value in { let VLMul = lmul.value in {
defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX); defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
def suffix # "_" # emul.MX : VPseudoBinaryNoMask<RetClass, Op1Class, Op2Class, def suffix # "_" # emul.MX : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
Constraint>;
def suffix # "_" # emul.MX # "_TU": VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
Constraint>; Constraint>;
def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>; RISCVMaskedPseudo</*MaskOpIdx*/ 3,
/*HasTU*/ false,
/*IsCombined*/ true>;
} }
} }
multiclass VPseudoTiedBinary<VReg RetClass, multiclass VPseudoTiedBinary<VReg RetClass,
DAGOperand Op2Class, DAGOperand Op2Class,
LMULInfo MInfo, LMULInfo MInfo,
string Constraint = ""> { string Constraint = ""> {
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
▲ Show 20 Lines • Show All 1,936 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst) (!cast<Instruction>(inst)
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
GPR:$vl, sew)>; GPR:$vl, sew)>;
class VPatBinaryNoMask<string intrinsic_name,
string inst,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
int sew,
VReg op1_reg_class,
DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type (undef)),
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
VLOpFrag)),
(!cast<Instruction>(inst)
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
GPR:$vl, sew)>;
class VPatBinaryNoMaskTU<string intrinsic_name, class VPatBinaryNoMaskTU<string intrinsic_name,
string inst, string inst,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name) Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_TU") (!cast<Instruction>(inst)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
GPR:$vl, sew, TU_MU)>; GPR:$vl, sew, TU_MU)>;
class VPatBinaryNoMaskRoundingMode<string intrinsic_name, class VPatBinaryNoMaskRoundingMode<string intrinsic_name,
string inst, string inst,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name) Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type (undef)), (result_type (undef)),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(XLenVT timm:$round), (XLenVT timm:$round),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst) (!cast<Instruction>(inst)
(result_type (IMPLICIT_DEF)),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(XLenVT timm:$round), (XLenVT timm:$round),
GPR:$vl, sew)>; GPR:$vl, sew, TA_MA)>;
class VPatBinaryNoMaskTURoundingMode<string intrinsic_name, class VPatBinaryNoMaskTURoundingMode<string intrinsic_name,
string inst, string inst,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
int sew, int sew,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> : DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic_name) Pat<(result_type (!cast<Intrinsic>(intrinsic_name)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(XLenVT timm:$round), (XLenVT timm:$round),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(inst#"_TU") (!cast<Instruction>(inst)
(result_type result_reg_class:$merge), (result_type result_reg_class:$merge),
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
(XLenVT timm:$round), (XLenVT timm:$round),
GPR:$vl, sew, TU_MU)>; GPR:$vl, sew, TU_MU)>;
// Same as above but source operands are swapped. // Same as above but source operands are swapped.
▲ Show 20 Lines • Show All 422 Lines • ▼ Show 20 Linesmulticlass VPatBinary<string intrinsic,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
VReg result_reg_class, VReg result_reg_class,
VReg op1_reg_class, VReg op1_reg_class,
DAGOperand op2_kind> { DAGOperand op2_kind> {
def : VPatBinaryNoMask<intrinsic, inst, result_type, op1_type, op2_type,
sew, op1_reg_class, op2_kind>;
def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type, def : VPatBinaryNoMaskTU<intrinsic, inst, result_type, op1_type, op2_type,
sew, result_reg_class, op1_reg_class, op2_kind>; sew, result_reg_class, op1_reg_class, op2_kind>;
def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type, def : VPatBinaryMaskTA<intrinsic, inst, result_type, op1_type, op2_type,
mask_type, sew, result_reg_class, op1_reg_class, mask_type, sew, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatBinaryRoundingMode<string intrinsic, multiclass VPatBinaryRoundingMode<string intrinsic,
▲ Show 20 Lines • Show All 1,109 Lines • ▼ Show 20 Lines
defm PseudoVRSUB : VPseudoVALU_VX_VI; defm PseudoVRSUB : VPseudoVALU_VX_VI;
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Match vrsub with 2 vector operands to vsub.vv by swapping operands. This // Match vrsub with 2 vector operands to vsub.vv by swapping operands. This
// Occurs when legalizing vrsub.vx intrinsics for i64 on RV32 since we need // Occurs when legalizing vrsub.vx intrinsics for i64 on RV32 since we need
// to use a more complex splat sequence. Add the pattern for all VTs for // to use a more complex splat sequence. Add the pattern for all VTs for
// consistency. // consistency.
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector (undef)),
(vti.Vector vti.RegClass:$rs2),
(vti.Vector vti.RegClass:$rs1),
VLOpFrag)),
(!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX) vti.RegClass:$rs1,
vti.RegClass:$rs2,
GPR:$vl,
vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector vti.RegClass:$merge), def : Pat<(vti.Vector (int_riscv_vrsub (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVSUB_VV_"#vti.LMul.MX)
vti.RegClass:$merge, vti.RegClass:$merge,
vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.RegClass:$rs2, vti.RegClass:$rs2,
GPR:$vl, GPR:$vl,
vti.Log2SEW, TU_MU)>; vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (int_riscv_vrsub_mask (vti.Vector vti.RegClass:$merge), def : Pat<(vti.Vector (int_riscv_vrsub_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
Show All 9 Lines def : Pat<(vti.Vector (int_riscv_vrsub_mask (vti.Vector vti.RegClass:$merge),
vti.Log2SEW, vti.Log2SEW,
(XLenVT timm:$policy))>; (XLenVT timm:$policy))>;
// Match VSUB with a small immediate to vadd.vi by negating the immediate. // Match VSUB with a small immediate to vadd.vi by negating the immediate.
def : Pat<(vti.Vector (int_riscv_vsub (vti.Vector (undef)), def : Pat<(vti.Vector (int_riscv_vsub (vti.Vector (undef)),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti.Scalar simm5_plus1:$rs2), (vti.Scalar simm5_plus1:$rs2),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX) vti.RegClass:$rs1, (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX) (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1,
(NegImm simm5_plus1:$rs2), (NegImm simm5_plus1:$rs2),
GPR:$vl, GPR:$vl,
vti.Log2SEW)>; vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (int_riscv_vsub_mask (vti.Vector vti.RegClass:$merge), def : Pat<(vti.Vector (int_riscv_vsub_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti.Scalar simm5_plus1:$rs2), (vti.Scalar simm5_plus1:$rs2),
(vti.Mask V0), (vti.Mask V0),
VLOpFrag, VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK") (!cast<Instruction>("PseudoVADD_VI_"#vti.LMul.MX#"_MASK")
vti.RegClass:$merge, vti.RegClass:$merge,
▲ Show 20 Lines • Show All 638 Lines • ▼ Show 20 Linesdefm : VPatBinaryV_VV_VX_VI<"int_riscv_vsra", "PseudoVSRA", AllIntegerVectors,
uimm5>; uimm5>;
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster. // Emit shift by 1 as an add since it might be faster.
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector undef), def : Pat<(vti.Vector (int_riscv_vsll (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(XLenVT 1), VLOpFrag)), (XLenVT 1), VLOpFrag)),
(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX) vti.RegClass:$rs1, (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
GPR:$vl, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
vti.Log2SEW)>;
def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge), def : Pat<(vti.Vector (int_riscv_vsll_mask (vti.Vector vti.RegClass:$merge),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(XLenVT 1), (XLenVT 1),
(vti.Mask V0), (vti.Mask V0),
VLOpFrag, VLOpFrag,
(XLenVT timm:$policy))), (XLenVT timm:$policy))),
(!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK") (!cast<Instruction>("PseudoVADD_VV_"#vti.LMul.MX#"_MASK")
vti.RegClass:$merge, vti.RegClass:$merge,
▲ Show 20 Lines • Show All 520 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 79 Lines • ▼ Show 20 Linesclass VPatBinarySDNode_VV<SDPatternOperator vop,
OutPatFrag avl, OutPatFrag avl,
VReg op_reg_class, VReg op_reg_class,
bit isSEWAware = 0> : bit isSEWAware = 0> :
Pat<(result_type (vop Pat<(result_type (vop
(op_type op_reg_class:$rs1), (op_type op_reg_class:$rs1),
(op_type op_reg_class:$rs2))), (op_type op_reg_class:$rs2))),
(!cast<Instruction>( (!cast<Instruction>(
!if(isSEWAware, !if(isSEWAware,
instruction_name#"_VV_"# vlmul.MX#"_E"#!shl(1, log2sew)#"_TU", instruction_name#"_VV_"# vlmul.MX#"_E"#!shl(1, log2sew),
instruction_name#"_VV_"# vlmul.MX#"_TU")) instruction_name#"_VV_"# vlmul.MX))
(result_type (IMPLICIT_DEF)), (result_type (IMPLICIT_DEF)),
op_reg_class:$rs1, op_reg_class:$rs1,
op_reg_class:$rs2, op_reg_class:$rs2,
avl, log2sew, TA_MA)>; avl, log2sew, TA_MA)>;
class VPatBinarySDNode_XI<SDPatternOperator vop, class VPatBinarySDNode_XI<SDPatternOperator vop,
string instruction_name, string instruction_name,
string suffix, string suffix,
ValueType result_type, ValueType result_type,
ValueType vop_type, ValueType vop_type,
int log2sew, int log2sew,
LMULInfo vlmul, LMULInfo vlmul,
OutPatFrag avl, OutPatFrag avl,
VReg vop_reg_class, VReg vop_reg_class,
ComplexPattern SplatPatKind, ComplexPattern SplatPatKind,
DAGOperand xop_kind, DAGOperand xop_kind,
bit isSEWAware = 0> : bit isSEWAware = 0> :
Pat<(result_type (vop Pat<(result_type (vop
(vop_type vop_reg_class:$rs1), (vop_type vop_reg_class:$rs1),
(vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))), (vop_type (SplatPatKind (XLenVT xop_kind:$rs2))))),
(!cast<Instruction>( (!cast<Instruction>(
!if(isSEWAware, !if(isSEWAware,
instruction_name#_#suffix#_# vlmul.MX#"_E"#!shl(1, log2sew)#"_TU", instruction_name#_#suffix#_# vlmul.MX#"_E"#!shl(1, log2sew),
instruction_name#_#suffix#_# vlmul.MX#"_TU")) instruction_name#_#suffix#_# vlmul.MX))
(result_type (IMPLICIT_DEF)), (result_type (IMPLICIT_DEF)),
vop_reg_class:$rs1, vop_reg_class:$rs1,
xop_kind:$rs2, xop_kind:$rs2,
avl, log2sew, TA_MA)>; avl, log2sew, TA_MA)>;
multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name, multiclass VPatBinarySDNode_VV_VX<SDPatternOperator vop, string instruction_name,
list<VTypeInfo> vtilist = AllIntegerVectors, list<VTypeInfo> vtilist = AllIntegerVectors,
bit isSEWAware = 0> { bit isSEWAware = 0> {
Show All 33 Linesclass VPatBinarySDNode_VF<SDPatternOperator vop,
OutPatFrag avl, OutPatFrag avl,
VReg vop_reg_class, VReg vop_reg_class,
DAGOperand xop_kind, DAGOperand xop_kind,
bit isSEWAware = 0> : bit isSEWAware = 0> :
Pat<(result_type (vop (vop_type vop_reg_class:$rs1), Pat<(result_type (vop (vop_type vop_reg_class:$rs1),
(vop_type (SplatFPOp xop_kind:$rs2)))), (vop_type (SplatFPOp xop_kind:$rs2)))),
(!cast<Instruction>( (!cast<Instruction>(
!if(isSEWAware, !if(isSEWAware,
instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew)#"_TU", instruction_name#"_"#vlmul.MX#"_E"#!shl(1, log2sew),
instruction_name#"_"#vlmul.MX#"_TU")) instruction_name#"_"#vlmul.MX))
(result_type (IMPLICIT_DEF)), (result_type (IMPLICIT_DEF)),
vop_reg_class:$rs1, vop_reg_class:$rs1,
(xop_type xop_kind:$rs2), (xop_type xop_kind:$rs2),
avl, log2sew, TA_MA)>; avl, log2sew, TA_MA)>;
multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_name, multiclass VPatBinaryFPSDNode_VV_VF<SDPatternOperator vop, string instruction_name,
bit isSEWAware = 0> { bit isSEWAware = 0> {
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
Show All 12 Lines
multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_name, multiclass VPatBinaryFPSDNode_R_VF<SDPatternOperator vop, string instruction_name,
bit isSEWAware = 0> { bit isSEWAware = 0> {
foreach fvti = AllFloatVectors in foreach fvti = AllFloatVectors in
let Predicates = GetVTypePredicates<fvti>.Predicates in let Predicates = GetVTypePredicates<fvti>.Predicates in
def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)), def : Pat<(fvti.Vector (vop (fvti.Vector (SplatFPOp fvti.Scalar:$rs2)),
(fvti.Vector fvti.RegClass:$rs1))), (fvti.Vector fvti.RegClass:$rs1))),
(!cast<Instruction>( (!cast<Instruction>(
!if(isSEWAware, !if(isSEWAware,
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW#"_TU", instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_E"#fvti.SEW,
instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX#"_TU")) instruction_name#"_V"#fvti.ScalarSuffix#"_"#fvti.LMul.MX))
(fvti.Vector (IMPLICIT_DEF)), (fvti.Vector (IMPLICIT_DEF)),
fvti.RegClass:$rs1, fvti.RegClass:$rs1,
(fvti.Scalar fvti.ScalarRegClass:$rs2), (fvti.Scalar fvti.ScalarRegClass:$rs2),
fvti.AVL, fvti.Log2SEW, TA_MA)>; fvti.AVL, fvti.Log2SEW, TA_MA)>;
} }
multiclass VPatIntegerSetCCSDNode_VV<string instruction_name, multiclass VPatIntegerSetCCSDNode_VV<string instruction_name,
CondCode cc> { CondCode cc> {
▲ Show 20 Lines • Show All 204 Lines • ▼ Show 20 Linesmulticlass VPatWidenBinarySDNode_VV_VX<SDNode op, PatFrags extop1, PatFrags extop2,
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))), def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (extop2 (vti.Vector vti.RegClass:$rs1)))), (wti.Vector (extop2 (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))), def : Pat<(op (wti.Vector (extop1 (vti.Vector vti.RegClass:$rs2))),
(wti.Vector (extop2 (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))), (wti.Vector (extop2 (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
(!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VX_"#vti.LMul.MX)
vti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
GPR:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatWidenBinarySDNode_WV_WX<SDNode op, PatFrags extop, multiclass VPatWidenBinarySDNode_WV_WX<SDNode op, PatFrags extop,
string instruction_name> { string instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED")
wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW,
TAIL_AGNOSTIC)>; TAIL_AGNOSTIC)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))), (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
wti.RegClass:$rs2, GPR:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2, GPR:$rs1,
vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop, multiclass VPatWidenBinarySDNode_VV_VX_WV_WX<SDNode op, PatFrags extop,
string instruction_name> string instruction_name>
: VPatWidenBinarySDNode_VV_VX<op, extop, extop, instruction_name>, : VPatWidenBinarySDNode_VV_VX<op, extop, extop, instruction_name>,
VPatWidenBinarySDNode_WV_WX<op, extop, instruction_name>; VPatWidenBinarySDNode_WV_WX<op, extop, instruction_name>;
Show All 39 Lines let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))), (vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))), (vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_VV_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))), (vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (riscv_fpextend_vl_oneuse (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))), (vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse def : Pat<(op (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
(vti.Mask true_mask), (XLenVT srcvalue))), (vti.Mask true_mask), (XLenVT srcvalue))),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs2,
vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> { multiclass VPatWidenBinaryFPSDNode_WV_WF<SDNode op, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (riscv_fpextend_vl_oneuse (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
(vti.Mask true_mask), (XLenVT srcvalue)))), (vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED") (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX#"_TIED")
wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, wti.RegClass:$rs2, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW,
TAIL_AGNOSTIC)>; TAIL_AGNOSTIC)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (riscv_fpextend_vl_oneuse (wti.Vector (riscv_fpextend_vl_oneuse
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs1)),
(vti.Mask true_mask), (XLenVT srcvalue)))), (vti.Mask true_mask), (XLenVT srcvalue)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2,
vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(op (wti.Vector wti.RegClass:$rs2), def : Pat<(op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))), (wti.Vector (SplatFPOp (fpext_oneuse vti.ScalarRegClass:$rs1)))),
(!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_W"#vti.ScalarSuffix#"_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), wti.RegClass:$rs2,
vti.ScalarRegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op, multiclass VPatWidenBinaryFPSDNode_VV_VF_WV_WF<SDNode op,
string instruction_name> string instruction_name>
: VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>, : VPatWidenBinaryFPSDNode_VV_VF<op, instruction_name>,
VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>; VPatWidenBinaryFPSDNode_WV_WF<op, instruction_name>;
▲ Show 20 Lines • Show All 168 Lines • ▼ Show 20 Lines
// 11. Vector Integer Arithmetic Instructions // 11. Vector Integer Arithmetic Instructions
// 11.1. Vector Single-Width Integer Add and Subtract // 11.1. Vector Single-Width Integer Add and Subtract
defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">; defm : VPatBinarySDNode_VV_VX_VI<add, "PseudoVADD">;
defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">; defm : VPatBinarySDNode_VV_VX<sub, "PseudoVSUB">;
// Handle VRSUB specially since it's the only integer binary op with reversed // Handle VRSUB specially since it's the only integer binary op with reversed
// pattern operands // pattern operands
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// FIXME: The AddedComplexity here is covering up a missing matcher for
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Add a FIXME here so we can find it later. Unless you're planning to fix it.

craig.topper: Add a FIXME here so we can find it later. Unless you're planning to fix it.
reamesAuthorUnsubmitted
Done
ReplyInline Actions

I'm not, so will do.

reames: I'm not, so will do.
// widening vwsub.vx which can recognize a extended folded into the
// scalar of the splat.
let AddedComplexity = 20 in
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(sub (vti.Vector (SplatPat (XLenVT GPR:$rs2))), def : Pat<(sub (vti.Vector (SplatPat (XLenVT GPR:$rs2))),
(vti.Vector vti.RegClass:$rs1)), (vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
vti.RegClass:$rs1, GPR:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, GPR:$rs2,
vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)), def : Pat<(sub (vti.Vector (SplatPat_simm5 simm5:$rs2)),
(vti.Vector vti.RegClass:$rs1)), (vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
vti.RegClass:$rs1, simm5:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
simm5:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
// 11.2. Vector Widening Integer Add and Subtract // 11.2. Vector Widening Integer Add and Subtract
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, sext_oneuse, "PseudoVWADD">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, zext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<add, anyext_oneuse, "PseudoVWADDU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, sext_oneuse, "PseudoVWSUB">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, zext_oneuse, "PseudoVWSUBU">;
defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">; defm : VPatWidenBinarySDNode_VV_VX_WV_WX<sub, anyext_oneuse, "PseudoVWSUBU">;
// shl (ext v, splat 1) is a special case of widening add. // shl (ext v, splat 1) is a special case of widening add.
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(shl (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs1))), def : Pat<(shl (wti.Vector (sext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))), (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX) (!cast<Instruction>("PseudoVWADD_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs1))), def : Pat<(shl (wti.Vector (zext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))), (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX) (!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs1))), def : Pat<(shl (wti.Vector (anyext_oneuse (vti.Vector vti.RegClass:$rs1))),
(wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))), (wti.Vector (riscv_vmv_v_x_vl (wti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX) (!cast<Instruction>("PseudoVWADDU_VV_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (wti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1, vti.RegClass:$rs1,
vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
// 11.3. Vector Integer Extension // 11.3. Vector Integer Extension
defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2", defm : VPatExtendSDNode_V<[zext, anyext], "PseudoVZEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2", defm : VPatExtendSDNode_V<[sext], "PseudoVSEXT", "VF2",
AllFractionableVF2IntVectors>; AllFractionableVF2IntVectors>;
Show All 17 Lines
defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>; defm : VPatBinarySDNode_VV_VX_VI<sra, "PseudoVSRA", uimm5>;
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster. // Emit shift by 1 as an add since it might be faster.
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
def : Pat<(shl (vti.Vector vti.RegClass:$rs1), def : Pat<(shl (vti.Vector vti.RegClass:$rs1),
(vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))), (vti.Vector (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)))),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)), vti.RegClass:$rs1,
vti.RegClass:$rs1, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
// 11.8. Vector Integer Comparison Instructions // 11.8. Vector Integer Comparison Instructions
defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>; defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSEQ", SETEQ>;
defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>; defm : VPatIntegerSetCCSDNode_VV<"PseudoVMSNE", SETNE>;
defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>; defm : VPatIntegerSetCCSDNode_VV_Swappable<"PseudoVMSLT", SETLT, SETGT>;
▲ Show 20 Lines • Show All 244 Lines • ▼ Show 20 Lines let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)), def : Pat<(any_fsqrt (vti.Vector vti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW) (!cast<Instruction>("PseudoVFSQRT_V_"# vti.LMul.MX#"_E"#vti.SEW)
(vti.Vector (IMPLICIT_DEF)), (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>; vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
// 13.12. Vector Floating-Point Sign-Injection Instructions // 13.12. Vector Floating-Point Sign-Injection Instructions
def : Pat<(fabs (vti.Vector vti.RegClass:$rs)), def : Pat<(fabs (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJX_VV_"# vti.LMul.MX)
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TU_MU)>;
// Handle fneg with VFSGNJN using the same input for both operands. // Handle fneg with VFSGNJN using the same input for both operands.
def : Pat<(fneg (vti.Vector vti.RegClass:$rs)), def : Pat<(fneg (vti.Vector vti.RegClass:$rs)),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs, vti.RegClass:$rs, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2))), (vti.Vector vti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJ_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))), (vti.Vector (SplatFPOp vti.ScalarRegClass:$rs2)))),
(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg vti.RegClass:$rs2)))), (vti.Vector (fneg vti.RegClass:$rs2)))),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (fcopysign (vti.Vector vti.RegClass:$rs1),
(vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))), (vti.Vector (fneg (SplatFPOp vti.ScalarRegClass:$rs2))))),
(!cast<Instruction>("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.Log2SEW, TU_MU)>;
} }
} }
// 13.11. Vector Floating-Point MIN/MAX Instructions // 13.11. Vector Floating-Point MIN/MAX Instructions
defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN">; defm : VPatBinaryFPSDNode_VV_VF<fminnum, "PseudoVFMIN">;
defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX">; defm : VPatBinaryFPSDNode_VV_VF<fmaxnum, "PseudoVFMAX">;
// 13.13. Vector Floating-Point Compare Instructions // 13.13. Vector Floating-Point Compare Instructions
▲ Show 20 Lines • Show All 103 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,179 Lines • ▼ Show 20 Lines let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
def : Pat< def : Pat<
(vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (wti.Vector wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))), (wti.Vector (extop (vti.Vector vti.RegClass:$rs1)))),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WV_"#vti.LMul.MX)
wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs2, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat< def : Pat<
(vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (wti.Vector wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))), (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1)))))),
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name> multiclass VPatBinaryVL_WV_WX_WI<SDNode op, string instruction_name>
: VPatBinaryExtVL_WV_WX<op, sext_oneuse, instruction_name>, : VPatBinaryExtVL_WV_WX<op, sext_oneuse, instruction_name>,
VPatBinaryExtVL_WV_WX<op, zext_oneuse, instruction_name> { VPatBinaryExtVL_WV_WX<op, zext_oneuse, instruction_name> {
foreach vtiToWti = AllWidenableIntVectors in { foreach vtiToWti = AllWidenableIntVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in GetVTypePredicates<wti>.Predicates) in
def : Pat< def : Pat<
(vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (wti.Vector wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask), (wti.Vector (SplatPat_uimm5 uimm5:$rs1))), (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs2, uimm5:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> { multiclass VPatWidenReductionVL<SDNode vop, PatFrags extop, string instruction_name, bit is_float> {
foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in { foreach vtiToWti = !if(is_float, AllWidenableFloatVectors, AllWidenableIntVectors) in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1"); defvar wti_m1 = !cast<VTypeInfo>(!if(is_float, "VF", "VI") # wti.SEW # "M1");
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines def : Pat<
(vti.Vector (vti.Vector
(riscv_trunc_vector_vl (riscv_trunc_vector_vl
(op (wti.Vector wti.RegClass:$rs2), (op (wti.Vector wti.RegClass:$rs2),
(wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1))), (wti.Vector (extop (vti.Vector (SplatPat (XLenVT GPR:$rs1))),
(vti.Mask true_mask), VLOpFrag)), (vti.Mask true_mask), VLOpFrag)),
srcvalue, (wti.Mask true_mask), VLOpFrag), srcvalue, (wti.Mask true_mask), VLOpFrag),
(vti.Mask true_mask), VLOpFrag)), (vti.Mask true_mask), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs2, GPR:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> { multiclass VPatMultiplyAddVL_VV_VX<SDNode op, string instruction_name> {
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
defvar suffix = vti.LMul.MX; defvar suffix = vti.LMul.MX;
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
// NOTE: We choose VMADD because it has the most commuting freedom. So it // NOTE: We choose VMADD because it has the most commuting freedom. So it
▲ Show 20 Lines • Show All 96 Lines • ▼ Show 20 Lines foreach vtiTowti = AllWidenableIntVectors in {
defvar vti = vtiTowti.Vti; defvar vti = vtiTowti.Vti;
defvar wti = vtiTowti.Wti; defvar wti = vtiTowti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(vti.Vector (riscv_trunc_vector_vl def : Pat<(vti.Vector (riscv_trunc_vector_vl
(wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2), (wti.Vector (op wti.RegClass:$rs1, (SplatPat XLenVT:$rs2),
srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)), srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WX_"#vti.LMul.MX)
wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (riscv_trunc_vector_vl def : Pat<(vti.Vector (riscv_trunc_vector_vl
(wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2), (wti.Vector (op wti.RegClass:$rs1, (SplatPat_uimm5 uimm5:$rs2),
srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)), srcvalue, true_mask, VLOpFrag)), true_mask, VLOpFrag)),
(!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX) (!cast<Instruction>(instruction_name#"_WI_"#vti.LMul.MX)
wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
wti.RegClass:$rs1, uimm5:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
} }
multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name> { multiclass VPatFPMulAddVL_VV_VF<SDPatternOperator vop, string instruction_name> {
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
defvar suffix = vti.LMul.MX; defvar suffix = vti.LMul.MX;
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
▲ Show 20 Lines • Show All 162 Lines • ▼ Show 20 Lines
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
// Emit shift by 1 as an add since it might be faster. // Emit shift by 1 as an add since it might be faster.
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(riscv_shl_vl (vti.Vector vti.RegClass:$rs1),
(riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)), (riscv_vmv_v_x_vl (vti.Vector undef), 1, (XLenVT srcvalue)),
srcvalue, (vti.Mask true_mask), VLOpFrag), srcvalue, (vti.Mask true_mask), VLOpFrag),
(!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVADD_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs1, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
// 11.7. Vector Narrowing Integer Right Shift Instructions // 11.7. Vector Narrowing Integer Right Shift Instructions
defm : VPatBinaryVL_WV_WX_WI<srl, "PseudoVNSRL">; defm : VPatBinaryVL_WV_WX_WI<srl, "PseudoVNSRL">;
defm : VPatBinaryVL_WV_WX_WI<sra, "PseudoVNSRA">; defm : VPatBinaryVL_WV_WX_WI<sra, "PseudoVNSRA">;
defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">; defm : VPatNarrowShiftSplat_WX_WI<riscv_sra_vl, "PseudoVNSRA">;
defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">; defm : VPatNarrowShiftSplat_WX_WI<riscv_srl_vl, "PseudoVNSRL">;
▲ Show 20 Lines • Show All 284 Lines • ▼ Show 20 Lines let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
(riscv_fneg_vl vti.RegClass:$rs2, (riscv_fneg_vl vti.RegClass:$rs2,
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag), VLOpFrag),
srcvalue, srcvalue,
(vti.Mask true_mask), (vti.Mask true_mask),
VLOpFrag), VLOpFrag),
(!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX) (!cast<Instruction>("PseudoVFSGNJN_VV_"# vti.LMul.MX)
vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW)>; (vti.Vector (IMPLICIT_DEF)),
vti.RegClass:$rs1, vti.RegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1), def : Pat<(riscv_fcopysign_vl (vti.Vector vti.RegClass:$rs1),
(SplatFPOp vti.ScalarRegClass:$rs2), (SplatFPOp vti.ScalarRegClass:$rs2),
vti.RegClass:$merge, vti.RegClass:$merge,
(vti.Mask V0), (vti.Mask V0),
VLOpFrag), VLOpFrag),
(!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_MASK") (!cast<Instruction>("PseudoVFSGNJ_V"#vti.ScalarSuffix#"_"# vti.LMul.MX#"_MASK")
vti.RegClass:$merge, vti.RegClass:$rs1, vti.RegClass:$merge, vti.RegClass:$rs1,
▲ Show 20 Lines • Show All 453 Lines • ▼ Show 20 Lines
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0), def : Pat<(vti.Vector (riscv_vid_vl (vti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK") (!cast<Instruction>("PseudoVID_V_"#vti.LMul.MX#"_MASK")
(vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW, (vti.Vector (IMPLICIT_DEF)), (vti.Mask V0), GPR:$vl, vti.Log2SEW,
TAIL_AGNOSTIC)>; TAIL_AGNOSTIC)>;
def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX)
vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd), def : Pat<(vti.Vector (riscv_slide1up_vl (vti.Vector vti.RegClass:$rd),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask), GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVSLIDE1UP_VX_"#vti.LMul.MX)
vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX)
vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd), def : Pat<(vti.Vector (riscv_slide1down_vl (vti.Vector vti.RegClass:$rd),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
GPR:$rs2, (vti.Mask true_mask), GPR:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVSLIDE1DOWN_VX_"#vti.LMul.MX)
vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; vti.RegClass:$rd, vti.RegClass:$rs1, GPR:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_fslide1up_vl (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
vti.Scalar:$rs2, (vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVFSLIDE1UP_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_fslide1up_vl (vti.Vector vti.RegClass:$rd), def : Pat<(vti.Vector (riscv_fslide1up_vl (vti.Vector vti.RegClass:$rd),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
vti.Scalar:$rs2, (vti.Mask true_mask), vti.Scalar:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVFSLIDE1UP_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVFSLIDE1UP_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; vti.RegClass:$rd, vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(vti.Vector (riscv_fslide1down_vl (vti.Vector undef),
(vti.Vector vti.RegClass:$rs1),
vti.Scalar:$rs2, (vti.Mask true_mask),
VLOpFrag)),
(!cast<Instruction>("PseudoVFSLIDE1DOWN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW)>;
def : Pat<(vti.Vector (riscv_fslide1down_vl (vti.Vector vti.RegClass:$rd), def : Pat<(vti.Vector (riscv_fslide1down_vl (vti.Vector vti.RegClass:$rd),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
vti.Scalar:$rs2, (vti.Mask true_mask), vti.Scalar:$rs2, (vti.Mask true_mask),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>("PseudoVFSLIDE1DOWN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX#"_TU") (!cast<Instruction>("PseudoVFSLIDE1DOWN_V"#vti.ScalarSuffix#"_"#vti.LMul.MX)
vti.RegClass:$rd, vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>; vti.RegClass:$rd, vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, GPR:$vl, vti.Log2SEW, TU_MU)>;
} }
} }
foreach vti = AllVectors in { foreach vti = AllVectors in {
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3), def : Pat<(vti.Vector (riscv_slideup_vl (vti.Vector vti.RegClass:$rs3),
(vti.Vector vti.RegClass:$rs1), (vti.Vector vti.RegClass:$rs1),
Show All 31 Lines

llvm/test/CodeGen/RISCV/double_reduct.ll

Show All 38 Lines; CHECK-NEXT: ret
%r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b) %r2 = call fast float @llvm.vector.reduce.fmul.f32.v4f32(float 1.0, <4 x float> %b)
%r = fmul fast float %r1, %r2 %r = fmul fast float %r1, %r2
ret float %r ret float %r
} }
define float @fmin_f32(<4 x float> %a, <4 x float> %b) { define float @fmin_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: fmin_f32: ; CHECK-LABEL: fmin_f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vfmin.vv v8, v8, v9 ; CHECK-NEXT: vfmin.vv v8, v8, v9
; CHECK-NEXT: vfredmin.vs v8, v8, v10 ; CHECK-NEXT: lui a0, 523264
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vfredmin.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a) %r1 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %a)
%r2 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b) %r2 = call fast float @llvm.vector.reduce.fmin.v4f32(<4 x float> %b)
%r = call float @llvm.minnum.f32(float %r1, float %r2) %r = call float @llvm.minnum.f32(float %r1, float %r2)
ret float %r ret float %r
} }
define float @fmax_f32(<4 x float> %a, <4 x float> %b) { define float @fmax_f32(<4 x float> %a, <4 x float> %b) {
; CHECK-LABEL: fmax_f32: ; CHECK-LABEL: fmax_f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 1047552
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vfmax.vv v8, v8, v9 ; CHECK-NEXT: vfmax.vv v8, v8, v9
; CHECK-NEXT: vfredmax.vs v8, v8, v10 ; CHECK-NEXT: lui a0, 1047552
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vfredmax.vs v8, v8, v9
; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a) %r1 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %a)
%r2 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b) %r2 = call fast float @llvm.vector.reduce.fmax.v4f32(<4 x float> %b)
%r = call float @llvm.maxnum.f32(float %r1, float %r2) %r = call float @llvm.maxnum.f32(float %r1, float %r2)
ret float %r ret float %r
} }
define i32 @add_i32(<4 x i32> %a, <4 x i32> %b) { define i32 @add_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: add_i32: ; CHECK-LABEL: add_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vadd.vv v8, v8, v9 ; CHECK-NEXT: vadd.vv v8, v8, v9
; CHECK-NEXT: vredsum.vs v8, v8, v10 ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vredsum.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %a) %r1 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %a)
%r2 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.add.i32.v4i32(<4 x i32> %b)
%r = add i32 %r1, %r2 %r = add i32 %r1, %r2
ret i32 %r ret i32 %r
} }
define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) { define i16 @add_ext_i16(<16 x i8> %a, <16 x i8> %b) {
; CHECK-LABEL: add_ext_i16: ; CHECK-LABEL: add_ext_i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e16, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vwaddu.vv v12, v8, v9 ; CHECK-NEXT: vwaddu.vv v10, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vredsum.vs v8, v12, v10 ; CHECK-NEXT: vmv.s.x v8, zero
; CHECK-NEXT: vredsum.vs v8, v10, v8
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%ae = zext <16 x i8> %a to <16 x i16> %ae = zext <16 x i8> %a to <16 x i16>
%be = zext <16 x i8> %b to <16 x i16> %be = zext <16 x i8> %b to <16 x i16>
%r1 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %ae) %r1 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %ae)
%r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be) %r2 = call i16 @llvm.vector.reduce.add.i16.v16i16(<16 x i16> %be)
%r = add i16 %r1, %r2 %r = add i16 %r1, %r2
ret i16 %r ret i16 %r
▲ Show 20 Lines • Show All 76 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%r = and i32 %r1, %r2 %r = and i32 %r1, %r2
ret i32 %r ret i32 %r
} }
define i32 @or_i32(<4 x i32> %a, <4 x i32> %b) { define i32 @or_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: or_i32: ; CHECK-LABEL: or_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vor.vv v8, v8, v9 ; CHECK-NEXT: vor.vv v8, v8, v9
; CHECK-NEXT: vredor.vs v8, v8, v10 ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vredor.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %a) %r1 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %a)
%r2 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.or.i32.v4i32(<4 x i32> %b)
%r = or i32 %r1, %r2 %r = or i32 %r1, %r2
ret i32 %r ret i32 %r
} }
define i32 @xor_i32(<4 x i32> %a, <4 x i32> %b) { define i32 @xor_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: xor_i32: ; CHECK-LABEL: xor_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vxor.vv v8, v8, v9 ; CHECK-NEXT: vxor.vv v8, v8, v9
; CHECK-NEXT: vredxor.vs v8, v8, v10 ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vredxor.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %a) %r1 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %a)
%r2 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.xor.i32.v4i32(<4 x i32> %b)
%r = xor i32 %r1, %r2 %r = xor i32 %r1, %r2
ret i32 %r ret i32 %r
} }
Show All 11 Lines; CHECK-NEXT: ret
%r = call i32 @llvm.umin.i32(i32 %r1, i32 %r2) %r = call i32 @llvm.umin.i32(i32 %r1, i32 %r2)
ret i32 %r ret i32 %r
} }
define i32 @umax_i32(<4 x i32> %a, <4 x i32> %b) { define i32 @umax_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: umax_i32: ; CHECK-LABEL: umax_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, zero
; CHECK-NEXT: vmaxu.vv v8, v8, v9 ; CHECK-NEXT: vmaxu.vv v8, v8, v9
; CHECK-NEXT: vredmaxu.vs v8, v8, v10 ; CHECK-NEXT: vmv.s.x v9, zero
; CHECK-NEXT: vredmaxu.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %a) %r1 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %a)
%r2 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.umax.i32.v4i32(<4 x i32> %b)
%r = call i32 @llvm.umax.i32(i32 %r1, i32 %r2) %r = call i32 @llvm.umax.i32(i32 %r1, i32 %r2)
ret i32 %r ret i32 %r
} }
Show All 23 Lines; RV64-NEXT: ret
%r2 = call i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.smin.i32.v4i32(<4 x i32> %b)
%r = call i32 @llvm.smin.i32(i32 %r1, i32 %r2) %r = call i32 @llvm.smin.i32(i32 %r1, i32 %r2)
ret i32 %r ret i32 %r
} }
define i32 @smax_i32(<4 x i32> %a, <4 x i32> %b) { define i32 @smax_i32(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: smax_i32: ; CHECK-LABEL: smax_i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.s.x v10, a0
; CHECK-NEXT: vmax.vv v8, v8, v9 ; CHECK-NEXT: vmax.vv v8, v8, v9
; CHECK-NEXT: vredmax.vs v8, v8, v10 ; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: vmv.s.x v9, a0
; CHECK-NEXT: vredmax.vs v8, v8, v9
; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: vmv.x.s a0, v8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%r1 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %a) %r1 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %a)
%r2 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %b) %r2 = call i32 @llvm.vector.reduce.smax.i32.v4i32(<4 x i32> %b)
%r = call i32 @llvm.smax.i32(i32 %r1, i32 %r2) %r = call i32 @llvm.smax.i32(i32 %r1, i32 %r2)
ret i32 %r ret i32 %r
} }
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llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll

Show First 20 Lines • Show All 58 Lines • ▼ Show 20 Lines
; CHECK-NEXT: slli a2, a2, 2 ; CHECK-NEXT: slli a2, a2, 2
; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: add a1, a1, a2 ; CHECK-NEXT: add a1, a1, a2
; CHECK-NEXT: vl4r.v v28, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl4r.v v28, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 4 ; CHECK-NEXT: slli a1, a1, 4
; CHECK-NEXT: add a1, sp, a1 ; CHECK-NEXT: add a1, sp, a1
; CHECK-NEXT: addi a1, a1, 16 ; CHECK-NEXT: addi a1, a1, 16
; CHECK-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; CHECK-NEXT: vfwsub.wv v16, v8, v24 ; CHECK-NEXT: vfwsub.wv v8, v16, v24
; CHECK-NEXT: addi a1, sp, 16 ; CHECK-NEXT: addi a1, sp, 16
; CHECK-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: vssubu.vv v4, v4, v8, v0.t ; CHECK-NEXT: vssubu.vv v4, v4, v8, v0.t
; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu ; CHECK-NEXT: vsetvli zero, s0, e32, m8, tu, mu
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
▲ Show 20 Lines • Show All 94 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/active_lane_mask.ll

Show First 20 Lines • Show All 97 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc) %mask = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 %index, i64 %tc)
ret <8 x i1> %mask ret <8 x i1> %mask
} }
define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) { define <32 x i1> @fv32(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv32: ; CHECK-LABEL: fv32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI8_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc) %mask = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 %index, i64 %tc)
ret <32 x i1> %mask ret <32 x i1> %mask
} }
define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) { define <64 x i1> @fv64(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv64: ; CHECK-LABEL: fv64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma ; CHECK-NEXT: vsetivli zero, 4, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: lui a0, %hi(.LCPI9_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_1) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI9_1)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
Show All 10 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc) %mask = call <64 x i1> @llvm.get.active.lane.mask.v64i1.i64(i64 %index, i64 %tc)
ret <64 x i1> %mask ret <64 x i1> %mask
} }
define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) { define <128 x i1> @fv128(ptr %p, i64 %index, i64 %tc) {
; CHECK-LABEL: fv128: ; CHECK-LABEL: fv128:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_0)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vid.v v16
; CHECK-NEXT: vsaddu.vx v16, v16, a1
; CHECK-NEXT: vmsltu.vx v0, v16, a2
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v0, v8, a2
; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma ; CHECK-NEXT: vsetivli zero, 4, e8, m1, tu, ma
; CHECK-NEXT: vslideup.vi v0, v16, 2 ; CHECK-NEXT: vslideup.vi v0, v16, 2
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: lui a0, %hi(.LCPI10_1)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_1) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI10_1)
; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; CHECK-NEXT: vle64.v v8, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: vsaddu.vx v8, v8, a1 ; CHECK-NEXT: vsaddu.vx v8, v8, a1
; CHECK-NEXT: vmsltu.vx v16, v8, a2 ; CHECK-NEXT: vmsltu.vx v16, v8, a2
▲ Show 20 Lines • Show All 54 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

Show First 20 Lines • Show All 2,133 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: mv a4, sp
; RV32-NEXT: vsetvli a5, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v11, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v10, v10, v11
; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vand.vx v10, v10, a4
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v11, v11, v12
; RV32-NEXT: vor.vv v10, v11, v10
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vand.vx v11, v8, a3
; RV32-NEXT: vsll.vx v12, v12, a2 ; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: vand.vx v12, v8, a4 ; RV32-NEXT: vand.vx v11, v8, a4
; RV32-NEXT: vsll.vi v12, v12, 24 ; RV32-NEXT: vsll.vi v11, v11, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v10, (a1), zero ; RV32-NEXT: vlse64.v v10, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: mv a4, sp
; RV32-NEXT: vsetvli a5, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v14, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v12, v12, v14
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4 ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vsrl.vi v14, v8, 8
; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v14, v14, v16
; RV32-NEXT: vor.vv v12, v14, v12
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v14, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: vand.vx v14, v8, a4
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v14, v14, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v12, (a1), zero ; RV32-NEXT: vlse64.v v12, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v10, v10, v12 ; RV32-NEXT: vand.vv v10, v10, v12
▲ Show 20 Lines • Show All 256 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: mv a4, sp
; RV32-NEXT: vsetvli a5, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v20, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v16, v16, v20
; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v24, v24, a4 ; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: mv a5, sp
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v24
; RV32-NEXT: vor.vv v16, v20, v16
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v20, v8, a3
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: vand.vx v24, v8, a4 ; RV32-NEXT: vand.vx v20, v8, a4
; RV32-NEXT: vsll.vi v24, v24, 24 ; RV32-NEXT: vsll.vi v20, v20, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: addi a1, sp, 24 ; RV32-NEXT: addi a1, sp, 24
; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v16, (a1), zero ; RV32-NEXT: vlse64.v v16, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
▲ Show 20 Lines • Show All 326 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 48 ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vsetvli a5, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v0, v16
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vx v24, v24, a4 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vand.vx v0, v24, a4
; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
▲ Show 20 Lines • Show All 330 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 48 ; RV32-NEXT: addi a4, sp, 48
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vsetvli a5, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v0, v16
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vx v24, v24, a4 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vand.vx v0, v24, a4
; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: addi a5, sp, 16
; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a5, sp, 48 ; RV32-NEXT: addi a5, sp, 48
; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a5) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v24, (a5) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a5) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: addi a1, sp, 48 ; RV32-NEXT: addi a1, sp, 48
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: addi a1, sp, 40 ; RV32-NEXT: addi a1, sp, 40
; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma ; RV32-NEXT: vsetvli a2, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v24, (a1), zero ; RV32-NEXT: vlse64.v v24, (a1), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
▲ Show 20 Lines • Show All 395 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll

Show First 20 Lines • Show All 643 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsrl.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: vsrl.vx v10, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vand.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsrl.vi v10, v8, 8 ; RV32-NEXT: vsrl.vi v10, v8, 24
; RV32-NEXT: addi a4, sp, 8 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vsetvli a5, zero, e64, m1, ta, ma ; RV32-NEXT: vand.vx v10, v10, a4
; RV32-NEXT: vlse64.v v11, (a4), zero ; RV32-NEXT: vsrl.vi v11, v8, 8
; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m1, ta, ma
; RV32-NEXT: vlse64.v v12, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v10, v10, v11 ; RV32-NEXT: vand.vv v11, v11, v12
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vor.vv v10, v11, v10
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v12, v12, a0
; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v10, v9
; RV32-NEXT: vsll.vx v10, v8, a1 ; RV32-NEXT: vsll.vx v10, v8, a1
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vand.vx v11, v8, a3
; RV32-NEXT: vsll.vx v12, v12, a2 ; RV32-NEXT: vsll.vx v11, v11, a2
; RV32-NEXT: vor.vv v10, v10, v12 ; RV32-NEXT: vor.vv v10, v10, v11
; RV32-NEXT: vand.vx v12, v8, a0 ; RV32-NEXT: vand.vx v11, v8, a4
; RV32-NEXT: vsll.vi v12, v12, 24 ; RV32-NEXT: vsll.vi v11, v11, 24
; RV32-NEXT: vand.vv v8, v8, v11 ; RV32-NEXT: vand.vv v8, v8, v12
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v10, v8 ; RV32-NEXT: vor.vv v8, v10, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v9
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv1i64_unmasked: ; RV64-LABEL: vp_bswap_nxv1i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: addi a4, sp, 8 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vsetvli a5, zero, e64, m2, ta, ma ; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vlse64.v v14, (a4), zero ; RV32-NEXT: vsrl.vi v14, v8, 8
; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m2, ta, ma
; RV32-NEXT: vlse64.v v16, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v12, v12, v14 ; RV32-NEXT: vand.vv v14, v14, v16
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vor.vv v12, v14, v12
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v14, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: vand.vx v16, v8, a0 ; RV32-NEXT: vand.vx v14, v8, a4
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v14, v14, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv2i64_unmasked: ; RV64-LABEL: vp_bswap_nxv2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
▲ Show 20 Lines • Show All 124 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 8 ; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: addi a4, sp, 8 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vsetvli a5, zero, e64, m4, ta, ma ; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vlse64.v v20, (a4), zero ; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vsetvli a6, zero, e64, m4, ta, ma
; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v16, v16, v20 ; RV32-NEXT: vand.vv v20, v20, v24
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vor.vv v16, v20, v16
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v24, v24, a0
; RV32-NEXT: vor.vv v16, v16, v24
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v20, v8, a3
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: vand.vx v24, v8, a0 ; RV32-NEXT: vand.vx v20, v8, a4
; RV32-NEXT: vsll.vi v24, v24, 24 ; RV32-NEXT: vsll.vi v20, v20, 24
; RV32-NEXT: vand.vv v8, v8, v20 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_nxv4i64_unmasked: ; RV64-LABEL: vp_bswap_nxv4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
▲ Show 20 Lines • Show All 194 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: addi a4, sp, 8
; RV32-NEXT: vsetvli a5, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v0, v16
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vand.vx v0, v24, a4
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
▲ Show 20 Lines • Show All 197 Lines • ▼ Show 20 Lines
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v24, v8, a2 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v24, v16 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: addi a4, sp, 8
; RV32-NEXT: vsetvli a5, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a4), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v0, v16
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vsrl.vi v24, v8, 24
; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vand.vx v0, v24, a4
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: vsrl.vi v16, v8, 8
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload ; RV32-NEXT: addi a5, sp, 8
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vsetvli a6, zero, e64, m8, ta, ma
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vlse64.v v24, (a5), zero
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v16, v16, v0
; RV32-NEXT: vand.vv v16, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v24
; RV32-NEXT: vand.vx v8, v8, a0 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8 ; RV32-NEXT: vsll.vi v24, v24, 8
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vor.vv v8, v24, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v8, v16 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
▲ Show 20 Lines • Show All 123 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/commuted-op-indices-regression.mir

Show All 26 Lines bb.0:
; CHECK-LABEL: name: commuted_op_indices ; CHECK-LABEL: name: commuted_op_indices
; CHECK: liveins: $v0, $v1, $v2 ; CHECK: liveins: $v0, $v1, $v2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vrnov0 = COPY $v1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vrnov0 = COPY $v2
; CHECK-NEXT: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], -1, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVNMSUB_VV_M1_:%[0-9]+]]:vr = PseudoVNMSUB_VV_M1 [[PseudoVNMSUB_VV_M1_]], [[COPY1]], [[COPY2]], -1, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]] ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY [[PseudoVNMSUB_VV_M1_]]
; CHECK-NEXT: dead [[COPY2]]:vr = PseudoVSLL_VI_M1 [[COPY2]], 11, $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: dead [[PseudoVSLL_VI_M1_:%[0-9]+]]:vr = PseudoVSLL_VI_M1 undef [[PseudoVSLL_VI_M1_]], [[PseudoVSLL_VI_M1_]], 11, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v0 = COPY [[PseudoVNMSUB_VV_M1_]] ; CHECK-NEXT: $v0 = COPY [[PseudoVNMSUB_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v0 ; CHECK-NEXT: PseudoRET implicit $v0
%0:vr = COPY $v0 %0:vr = COPY $v0
%1:vrnov0 = COPY $v1 %1:vrnov0 = COPY $v1
%2:vrnov0 = COPY $v2 %2:vrnov0 = COPY $v2
%0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype %0:vr = PseudoVNMSUB_VV_M1 %0, %1, killed %2, -1, 6, 1, implicit $vl, implicit $vtype
%3:vr = COPY %0 %3:vr = COPY %0
%3:vr = PseudoVSLL_VI_M1 %3, 11, $noreg, 6, implicit $vl, implicit $vtype %3:vr = PseudoVSLL_VI_M1 undef %3, %3, 11, $noreg, 6, 0, implicit $vl, implicit $vtype
$v0 = COPY %0 $v0 = COPY %0
PseudoRET implicit $v0 PseudoRET implicit $v0
... ...

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

Show First 20 Lines • Show All 1,514 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_bitreverse_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bitreverse_v2i64_unmasked: ; RV32-LABEL: vp_bitreverse_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsll.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vmv.v.i v0, 5 ; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vand.vv v11, v11, v10 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v12, v12, a4 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vor.vv v11, v11, v12 ; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vor.vv v9, v11, v9 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vsll.vx v11, v8, a1 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vsll.vx v12, v12, a2 ; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: vor.vv v11, v11, v12 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vv v10, v8, v10
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: vsrl.vi v9, v8, 4 ; RV32-NEXT: vsrl.vi v9, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v10, a1 ; RV32-NEXT: vmv.v.x v10, a1
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vand.vv v9, v9, v10 ; RV32-NEXT: vand.vv v9, v9, v10
; RV32-NEXT: vand.vv v8, v8, v10 ; RV32-NEXT: vand.vv v8, v8, v10
▲ Show 20 Lines • Show All 230 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: li a4, 85 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vsrl.vi v14, v8, 8
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v14, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v14, v14, a4, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v12, v12, v14 ; RV32-NEXT: vand.vv v14, v14, v16
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vor.vv v12, v14, v12
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v14, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: vand.vx v14, v8, a4
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v14, v14, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vsrl.vi v10, v8, 4 ; RV32-NEXT: vsrl.vi v10, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.x v12, a1 ; RV32-NEXT: vmv.v.x v12, a1
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
▲ Show 20 Lines • Show All 233 Lines • ▼ Show 20 Lines
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v16 ; RV32-NEXT: vand.vv v20, v20, v24
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vor.vv v16, v20, v16
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vand.vx v24, v24, a4 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vand.vx v20, v8, a3
; RV32-NEXT: vor.vv v12, v20, v12 ; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vsll.vx v20, v8, a1 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v20, v8, a4
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vi v20, v20, 24
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vx v24, v8, a4
; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: vsrl.vi v12, v8, 4 ; RV32-NEXT: vsrl.vi v12, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v12, v12, v16 ; RV32-NEXT: vand.vv v12, v12, v16
▲ Show 20 Lines • Show All 320 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: li a2, 40
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: li a3, 40 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vsll.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsll.vi v24, v16, 24 ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v8, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vsll.vi v0, v0, 8 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a6
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vsrl.vi v0, v8, 8 ; RV32-NEXT: vand.vv v16, v8, v16
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vx v8, v8, a6
; RV32-NEXT: vsrl.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2 ; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a6 ; RV32-NEXT: vmv.v.x v24, a5
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
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; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: li a2, 40
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: li a3, 40 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vsll.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsll.vi v24, v16, 24 ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v8, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vsll.vi v0, v0, 8 ; RV32-NEXT: lui a6, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a6
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a7, sp, 16 ; RV32-NEXT: addi a7, sp, 16
; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v0, (a7) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v24, (a7) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v0, v8, a3 ; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2 ; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1 ; RV32-NEXT: vsll.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vsrl.vi v0, v8, 8 ; RV32-NEXT: vand.vv v16, v8, v16
; RV32-NEXT: vand.vv v16, v0, v16 ; RV32-NEXT: vand.vx v8, v8, a6
; RV32-NEXT: vsrl.vi v8, v8, 24 ; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4 ; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v8, v24 ; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: addi a1, sp, 16
; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vsrl.vi v16, v8, 4 ; RV32-NEXT: vsrl.vi v16, v8, 4
; RV32-NEXT: lui a1, 61681 ; RV32-NEXT: lui a1, 61681
; RV32-NEXT: addi a1, a1, -241 ; RV32-NEXT: addi a1, a1, -241
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 4 ; RV32-NEXT: vsll.vi v8, v8, 4
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 2 ; RV32-NEXT: vsrl.vi v16, v8, 2
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vsll.vi v8, v8, 2 ; RV32-NEXT: vsll.vi v8, v8, 2
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vsrl.vi v16, v8, 1 ; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v24, a6 ; RV32-NEXT: vmv.v.x v24, a5
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v16, v16, v24 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v8, v8, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap-vp.ll

Show First 20 Lines • Show All 497 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
ret <2 x i64> %v ret <2 x i64> %v
} }
define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) { define <2 x i64> @vp_bswap_v2i64_unmasked(<2 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_bswap_v2i64_unmasked: ; RV32-LABEL: vp_bswap_v2i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vx v9, v8, a1 ; RV32-NEXT: vsll.vx v9, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: lui a2, 16
; RV32-NEXT: vsrl.vx v10, v8, a2 ; RV32-NEXT: addi a2, a2, -256
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: vand.vx v10, v8, a2
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: li a3, 40
; RV32-NEXT: vand.vx v10, v10, a3 ; RV32-NEXT: vsll.vx v10, v10, a3
; RV32-NEXT: vor.vv v9, v10, v9 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v10, v8, a4
; RV32-NEXT: vsll.vi v10, v10, 24
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.i v10, 0 ; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vmv.v.i v0, 5 ; RV32-NEXT: vmv.v.i v0, 5
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v10, v10, a4, v0 ; RV32-NEXT: vmerge.vxm v11, v11, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV32-NEXT: vsrl.vi v11, v8, 8 ; RV32-NEXT: vand.vv v12, v8, v11
; RV32-NEXT: vand.vv v11, v11, v10 ; RV32-NEXT: vsll.vi v12, v12, 8
; RV32-NEXT: vsrl.vi v12, v8, 24 ; RV32-NEXT: vor.vv v10, v10, v12
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vor.vv v9, v9, v10
; RV32-NEXT: vand.vx v12, v12, a0 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: vor.vv v11, v11, v12 ; RV32-NEXT: vsrl.vx v12, v8, a3
; RV32-NEXT: vor.vv v9, v11, v9 ; RV32-NEXT: vand.vx v12, v12, a2
; RV32-NEXT: vsll.vx v11, v8, a1 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vand.vx v12, v8, a3 ; RV32-NEXT: vsrl.vi v12, v8, 8
; RV32-NEXT: vsll.vx v12, v12, a2 ; RV32-NEXT: vand.vv v11, v12, v11
; RV32-NEXT: vor.vv v11, v11, v12 ; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vv v10, v8, v10 ; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vsll.vi v10, v10, 8
; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v11, v8 ; RV32-NEXT: vor.vv v8, v11, v8
; RV32-NEXT: vor.vv v8, v8, v9 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: vor.vv v8, v9, v8
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v2i64_unmasked: ; RV64-LABEL: vp_bswap_v2i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; RV64-NEXT: vand.vx v9, v8, a1 ; RV64-NEXT: vand.vx v9, v8, a1
; RV64-NEXT: vsll.vi v9, v9, 24 ; RV64-NEXT: vsll.vi v9, v9, 24
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; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vsrl.vx v10, v8, a1 ; RV32-NEXT: vsrl.vx v10, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v12, v8, a2 ; RV32-NEXT: vsrl.vx v12, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v12, v12, a3 ; RV32-NEXT: vand.vx v12, v12, a3
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsrl.vi v12, v8, 8 ; RV32-NEXT: vsrl.vi v12, v8, 24
; RV32-NEXT: li a4, 85 ; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v12, v12, a4
; RV32-NEXT: vsrl.vi v14, v8, 8
; RV32-NEXT: li a5, 85
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
; RV32-NEXT: vmv.v.i v14, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v14, v14, a4, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; RV32-NEXT: vand.vv v12, v12, v14 ; RV32-NEXT: vand.vv v14, v14, v16
; RV32-NEXT: vsrl.vi v16, v8, 24 ; RV32-NEXT: vor.vv v12, v14, v12
; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vand.vx v16, v16, a0
; RV32-NEXT: vor.vv v12, v12, v16
; RV32-NEXT: vor.vv v10, v12, v10 ; RV32-NEXT: vor.vv v10, v12, v10
; RV32-NEXT: vsll.vx v12, v8, a1 ; RV32-NEXT: vsll.vx v12, v8, a1
; RV32-NEXT: vand.vx v16, v8, a3 ; RV32-NEXT: vand.vx v14, v8, a3
; RV32-NEXT: vsll.vx v16, v16, a2 ; RV32-NEXT: vsll.vx v14, v14, a2
; RV32-NEXT: vor.vv v12, v12, v16 ; RV32-NEXT: vor.vv v12, v12, v14
; RV32-NEXT: vand.vx v16, v8, a0 ; RV32-NEXT: vand.vx v14, v8, a4
; RV32-NEXT: vsll.vi v16, v16, 24 ; RV32-NEXT: vsll.vi v14, v14, 24
; RV32-NEXT: vand.vv v8, v8, v14 ; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v14, v8
; RV32-NEXT: vor.vv v8, v12, v8 ; RV32-NEXT: vor.vv v8, v12, v8
; RV32-NEXT: vor.vv v8, v8, v10 ; RV32-NEXT: vor.vv v8, v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v4i64_unmasked: ; RV64-LABEL: vp_bswap_v4i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m2, ta, ma
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; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vsrl.vx v12, v8, a1 ; RV32-NEXT: vsrl.vx v12, v8, a1
; RV32-NEXT: li a2, 40 ; RV32-NEXT: li a2, 40
; RV32-NEXT: vsrl.vx v16, v8, a2 ; RV32-NEXT: vsrl.vx v16, v8, a2
; RV32-NEXT: lui a3, 16 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: addi a3, a3, -256 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vand.vx v16, v16, a3 ; RV32-NEXT: vand.vx v16, v16, a3
; RV32-NEXT: vor.vv v12, v16, v12 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vsrl.vi v16, v8, 24
; RV32-NEXT: lui a4, 4080
; RV32-NEXT: vand.vx v16, v16, a4
; RV32-NEXT: vsrl.vi v20, v8, 8 ; RV32-NEXT: vsrl.vi v20, v8, 8
; RV32-NEXT: lui a4, 5 ; RV32-NEXT: lui a5, 5
; RV32-NEXT: addi a4, a4, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a4 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v24, 0
; RV32-NEXT: lui a4, 1044480 ; RV32-NEXT: lui a5, 1044480
; RV32-NEXT: vmerge.vxm v16, v16, a4, v0 ; RV32-NEXT: vmerge.vxm v24, v24, a5, v0
; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV32-NEXT: vand.vv v20, v20, v16 ; RV32-NEXT: vand.vv v20, v20, v24
; RV32-NEXT: vsrl.vi v24, v8, 24 ; RV32-NEXT: vor.vv v16, v20, v16
; RV32-NEXT: lui a0, 4080 ; RV32-NEXT: vor.vv v12, v16, v12
; RV32-NEXT: vand.vx v24, v24, a0 ; RV32-NEXT: vsll.vx v16, v8, a1
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vand.vx v20, v8, a3
; RV32-NEXT: vor.vv v12, v20, v12 ; RV32-NEXT: vsll.vx v20, v20, a2
; RV32-NEXT: vsll.vx v20, v8, a1 ; RV32-NEXT: vor.vv v16, v16, v20
; RV32-NEXT: vand.vx v24, v8, a3 ; RV32-NEXT: vand.vx v20, v8, a4
; RV32-NEXT: vsll.vx v24, v24, a2 ; RV32-NEXT: vsll.vi v20, v20, 24
; RV32-NEXT: vor.vv v20, v20, v24 ; RV32-NEXT: vand.vv v8, v8, v24
; RV32-NEXT: vand.vx v24, v8, a0
; RV32-NEXT: vsll.vi v24, v24, 24
; RV32-NEXT: vand.vv v8, v8, v16
; RV32-NEXT: vsll.vi v8, v8, 8 ; RV32-NEXT: vsll.vi v8, v8, 8
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: vor.vv v8, v20, v8 ; RV32-NEXT: vor.vv v8, v20, v8
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v12 ; RV32-NEXT: vor.vv v8, v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v8i64_unmasked: ; RV64-LABEL: vp_bswap_v8i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a1, 4080 ; RV64-NEXT: lui a1, 4080
; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; RV64-NEXT: vsetvli zero, a0, e64, m4, ta, ma
; RV64-NEXT: vand.vx v12, v8, a1 ; RV64-NEXT: vand.vx v12, v8, a1
▲ Show 20 Lines • Show All 208 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: li a2, 40
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: li a3, 40 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vsll.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsll.vi v24, v16, 24 ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v8, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vsll.vi v0, v0, 8 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vand.vv v16, v8, v16
; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v15i64_unmasked: ; RV64-LABEL: vp_bswap_v15i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
▲ Show 20 Lines • Show All 211 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: csrr a1, vlenb ; RV32-NEXT: csrr a1, vlenb
; RV32-NEXT: slli a1, a1, 3 ; RV32-NEXT: slli a1, a1, 3
; RV32-NEXT: sub sp, sp, a1 ; RV32-NEXT: sub sp, sp, a1
; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb ; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 8 * vlenb
; RV32-NEXT: li a1, 56 ; RV32-NEXT: li a1, 56
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsll.vx v16, v8, a1 ; RV32-NEXT: vsrl.vx v16, v8, a1
; RV32-NEXT: lui a2, 16 ; RV32-NEXT: li a2, 40
; RV32-NEXT: addi a2, a2, -256 ; RV32-NEXT: vsrl.vx v24, v8, a2
; RV32-NEXT: vand.vx v24, v8, a2 ; RV32-NEXT: lui a3, 16
; RV32-NEXT: li a3, 40 ; RV32-NEXT: addi a3, a3, -256
; RV32-NEXT: vsll.vx v24, v24, a3 ; RV32-NEXT: vand.vx v24, v24, a3
; RV32-NEXT: vor.vv v16, v16, v24 ; RV32-NEXT: vor.vv v16, v24, v16
; RV32-NEXT: addi a4, sp, 16 ; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill
; RV32-NEXT: lui a4, 4080 ; RV32-NEXT: vsrl.vi v24, v8, 8
; RV32-NEXT: vand.vx v16, v8, a4 ; RV32-NEXT: li a4, 32
; RV32-NEXT: vsll.vi v24, v16, 24 ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: li a5, 32
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma
; RV32-NEXT: vmv.v.i v16, 0 ; RV32-NEXT: vmv.v.i v16, 0
; RV32-NEXT: lui a6, 349525 ; RV32-NEXT: lui a5, 349525
; RV32-NEXT: addi a6, a6, 1365 ; RV32-NEXT: addi a5, a5, 1365
; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-NEXT: lui a7, 1044480 ; RV32-NEXT: lui a6, 1044480
; RV32-NEXT: vmv.v.x v0, a6 ; RV32-NEXT: vmv.v.x v0, a5
; RV32-NEXT: vsetvli zero, a5, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a4, e32, m8, ta, ma
; RV32-NEXT: vmerge.vxm v16, v16, a7, v0 ; RV32-NEXT: vmerge.vxm v16, v16, a6, v0
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v0, v8, v16 ; RV32-NEXT: vand.vv v24, v24, v16
; RV32-NEXT: vsll.vi v0, v0, 8 ; RV32-NEXT: lui a0, 4080
; RV32-NEXT: vsrl.vi v0, v8, 24
; RV32-NEXT: vand.vx v0, v0, a0
; RV32-NEXT: vor.vv v24, v24, v0 ; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: addi a4, sp, 16
; RV32-NEXT: vl8r.v v0, (a4) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vs8r.v v24, (a4) # Unknown-size Folded Spill
; RV32-NEXT: vand.vx v0, v8, a3
; RV32-NEXT: vsll.vx v0, v0, a2
; RV32-NEXT: vsll.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v24, v0
; RV32-NEXT: vand.vv v16, v8, v16
; RV32-NEXT: vand.vx v8, v8, a0
; RV32-NEXT: vsll.vi v8, v8, 24
; RV32-NEXT: vsll.vi v16, v16, 8
; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: vor.vv v8, v24, v8
; RV32-NEXT: addi a0, sp, 16 ; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-NEXT: vsrl.vx v0, v8, a3
; RV32-NEXT: vand.vx v0, v0, a2
; RV32-NEXT: vsrl.vx v24, v8, a1
; RV32-NEXT: vor.vv v24, v0, v24
; RV32-NEXT: vsrl.vi v0, v8, 8
; RV32-NEXT: vand.vv v16, v0, v16
; RV32-NEXT: vsrl.vi v8, v8, 24
; RV32-NEXT: vand.vx v8, v8, a4
; RV32-NEXT: vor.vv v8, v16, v8
; RV32-NEXT: vor.vv v8, v8, v24
; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; RV32-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; RV32-NEXT: vor.vv v8, v16, v8 ; RV32-NEXT: vor.vv v8, v8, v16
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 3 ; RV32-NEXT: slli a0, a0, 3
; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: add sp, sp, a0
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vp_bswap_v16i64_unmasked: ; RV64-LABEL: vp_bswap_v16i64_unmasked:
; RV64: # %bb.0: ; RV64: # %bb.0:
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctpop-vp.ll

Show First 20 Lines • Show All 1,612 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl) %v = call <15 x i64> @llvm.vp.ctpop.v15i64(<15 x i64> %va, <15 x i1> %m, i32 %evl)
ret <15 x i64> %v ret <15 x i64> %v
} }
define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) { define <15 x i64> @vp_ctpop_v15i64_unmasked(<15 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v15i64_unmasked: ; RV32-LABEL: vp_ctpop_v15i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 1 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
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; RV64-NEXT: ret ; RV64-NEXT: ret
%v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl) %v = call <16 x i64> @llvm.vp.ctpop.v16i64(<16 x i64> %va, <16 x i1> %m, i32 %evl)
ret <16 x i64> %v ret <16 x i64> %v
} }
define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) { define <16 x i64> @vp_ctpop_v16i64_unmasked(<16 x i64> %va, i32 zeroext %evl) {
; RV32-LABEL: vp_ctpop_v16i64_unmasked: ; RV32-LABEL: vp_ctpop_v16i64_unmasked:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v16, v8, 1
; RV32-NEXT: lui a1, 349525 ; RV32-NEXT: lui a1, 349525
; RV32-NEXT: addi a1, a1, 1365 ; RV32-NEXT: addi a1, a1, 1365
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v24, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vsrl.vi v24, v8, 1 ; RV32-NEXT: vand.vv v16, v16, v24
; RV32-NEXT: vand.vv v16, v24, v16
; RV32-NEXT: vsub.vv v8, v8, v16 ; RV32-NEXT: vsub.vv v8, v8, v16
; RV32-NEXT: lui a1, 209715 ; RV32-NEXT: lui a1, 209715
; RV32-NEXT: addi a1, a1, 819 ; RV32-NEXT: addi a1, a1, 819
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vmv.v.x v16, a1 ; RV32-NEXT: vmv.v.x v16, a1
; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a0, e64, m8, ta, ma
; RV32-NEXT: vand.vv v24, v8, v16 ; RV32-NEXT: vand.vv v24, v8, v16
; RV32-NEXT: vsrl.vi v8, v8, 2 ; RV32-NEXT: vsrl.vi v8, v8, 2
▲ Show 20 Lines • Show All 531 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s -check-prefixes=CHECK,RV32 ; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s -check-prefixes=CHECK,RV32
; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s -check-prefixes=CHECK,RV64 ; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck %s -check-prefixes=CHECK,RV64
; Integers ; Integers
define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) { define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
; RV32-LABEL: vector_deinterleave_load_v16i1_v32i1: ; RV32-LABEL: vector_deinterleave_load_v16i1_v32i1:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: li a1, 32 ; RV32-NEXT: li a1, 32
; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV32-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; RV32-NEXT: vlm.v v8, (a0) ; RV32-NEXT: vlm.v v0, (a0)
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v8, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmv.v.i v9, 0 ; RV32-NEXT: vmv.v.i v8, 0
; RV32-NEXT: vmerge.vim v10, v9, 1, v0 ; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vmv1r.v v0, v8
; RV32-NEXT: vmerge.vim v8, v9, 1, v0
; RV32-NEXT: vid.v v9 ; RV32-NEXT: vid.v v9
; RV32-NEXT: vadd.vv v11, v9, v9 ; RV32-NEXT: vadd.vv v11, v9, v9
; RV32-NEXT: vrgather.vv v9, v8, v11 ; RV32-NEXT: vrgather.vv v9, v10, v11
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vadd.vi v12, v11, -16 ; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: vrgather.vv v9, v10, v12, v0.t
; RV32-NEXT: vmsne.vi v9, v9, 0 ; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vadd.vi v12, v11, 1 ; RV32-NEXT: vadd.vi v12, v11, 1
; RV32-NEXT: vrgather.vv v13, v8, v12 ; RV32-NEXT: vrgather.vv v13, v10, v12
; RV32-NEXT: vadd.vi v8, v11, -15 ; RV32-NEXT: vadd.vi v10, v11, -15
; RV32-NEXT: vrgather.vv v13, v10, v8, v0.t ; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV32-NEXT: vmsne.vi v8, v13, 0 ; RV32-NEXT: vmsne.vi v8, v13, 0
; RV32-NEXT: vmv.v.v v0, v9 ; RV32-NEXT: vmv.v.v v0, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vector_deinterleave_load_v16i1_v32i1: ; RV64-LABEL: vector_deinterleave_load_v16i1_v32i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a1, 32 ; RV64-NEXT: li a1, 32
; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; RV64-NEXT: vsetvli zero, a1, e8, m2, ta, ma
; RV64-NEXT: vlm.v v8, (a0) ; RV64-NEXT: vlm.v v0, (a0)
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v8, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v9, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmerge.vim v10, v9, 1, v0 ; RV64-NEXT: vmerge.vim v10, v8, 1, v0
; RV64-NEXT: vmv1r.v v0, v8
; RV64-NEXT: vmerge.vim v8, v9, 1, v0
; RV64-NEXT: vid.v v9 ; RV64-NEXT: vid.v v9
; RV64-NEXT: vadd.vv v11, v9, v9 ; RV64-NEXT: vadd.vv v11, v9, v9
; RV64-NEXT: vrgather.vv v9, v8, v11 ; RV64-NEXT: vrgather.vv v9, v10, v11
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vadd.vi v12, v11, -16 ; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: vrgather.vv v9, v10, v12, v0.t
; RV64-NEXT: vmsne.vi v9, v9, 0 ; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vadd.vi v12, v11, 1 ; RV64-NEXT: vadd.vi v12, v11, 1
; RV64-NEXT: vrgather.vv v13, v8, v12 ; RV64-NEXT: vrgather.vv v13, v10, v12
; RV64-NEXT: vadd.vi v8, v11, -15 ; RV64-NEXT: vadd.vi v10, v11, -15
; RV64-NEXT: vrgather.vv v13, v10, v8, v0.t ; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV64-NEXT: vmsne.vi v8, v13, 0 ; RV64-NEXT: vmsne.vi v8, v13, 0
; RV64-NEXT: vmv.v.v v0, v9 ; RV64-NEXT: vmv.v.v v0, v9
; RV64-NEXT: ret ; RV64-NEXT: ret
%vec = load <32 x i1>, ptr %p %vec = load <32 x i1>, ptr %p
%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec) %retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec)
ret {<16 x i1>, <16 x i1>} %retval ret {<16 x i1>, <16 x i1>} %retval
} }
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fmf.ll

; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 -stop-after=finalize-isel | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v -riscv-v-vector-bits-min=-1 -stop-after=finalize-isel | FileCheck %s
define <2 x double> @foo(<2 x double> %x, <2 x double> %y) { define <2 x double> @foo(<2 x double> %x, <2 x double> %y) {
; CHECK-LABEL: name: foo ; CHECK-LABEL: name: foo
; CHECK: bb.0 (%ir-block.0): ; CHECK: bb.0 (%ir-block.0):
; CHECK-NEXT: liveins: $v8, $v9 ; CHECK-NEXT: liveins: $v8, $v9
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[PseudoVFADD_VV_M1_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[COPY1]], [[COPY]], 2, 6 /* e64 */, implicit $frm ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVFADD_VV_M1_:%[0-9]+]]:vr = nnan ninf nsz arcp contract afn reassoc nofpexcept PseudoVFADD_VV_M1 [[DEF]], [[COPY1]], [[COPY]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $frm
; CHECK-NEXT: $v8 = COPY [[PseudoVFADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVFADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%1 = fadd fast <2 x double> %x, %y %1 = fadd fast <2 x double> %x, %y
ret <2 x double> %1 ret <2 x double> %1
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll

Show First 20 Lines • Show All 249 Lines • ▼ Show 20 Lines
} }
define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) { define <64 x float> @interleave_v32f32(<32 x float> %x, <32 x float> %y) {
; RV32-V128-LABEL: interleave_v32f32: ; RV32-V128-LABEL: interleave_v32f32:
; RV32-V128: # %bb.0: ; RV32-V128: # %bb.0:
; RV32-V128-NEXT: addi sp, sp, -16 ; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16 ; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: li a1, 24 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: sub sp, sp, a0 ; RV32-V128-NEXT: sub sp, sp, a0
; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV32-V128-NEXT: slli a0, a0, 3 ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: li a1, 32
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vle32.v v0, (a0)
; RV32-V128-NEXT: vmv8r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: li a0, 32 ; RV32-V128-NEXT: vrgather.vv v8, v24, v0
; RV32-V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-V128-NEXT: lui a0, %hi(.LCPI10_1)
; RV32-V128-NEXT: lui a1, %hi(.LCPI10_1) ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
; RV32-V128-NEXT: addi a1, a1, %lo(.LCPI10_1) ; RV32-V128-NEXT: vle32.v v24, (a0)
; RV32-V128-NEXT: vle32.v v0, (a1)
; RV32-V128-NEXT: lui a1, %hi(.LCPI10_0)
; RV32-V128-NEXT: addi a1, a1, %lo(.LCPI10_0)
; RV32-V128-NEXT: vle32.v v16, (a1)
; RV32-V128-NEXT: csrr a1, vlenb
; RV32-V128-NEXT: slli a1, a1, 4
; RV32-V128-NEXT: add a1, sp, a1
; RV32-V128-NEXT: addi a1, a1, 16
; RV32-V128-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-V128-NEXT: vrgather.vv v16, v8, v0
; RV32-V128-NEXT: lui a1, 699051
; RV32-V128-NEXT: addi a1, a1, -1366
; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-V128-NEXT: vmv.v.x v0, a1
; RV32-V128-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 4 ; RV32-V128-NEXT: slli a0, a0, 3
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, 699051
; RV32-V128-NEXT: addi a0, a0, -1366
; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-V128-NEXT: vmv.v.x v0, a0
; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 3 ; RV32-V128-NEXT: slli a0, a0, 3
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-V128-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV32-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV32-V128-NEXT: vmv.v.v v24, v8
; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-V128-NEXT: vmv4r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-V128-NEXT: vwaddu.vv v0, v8, v24 ; RV32-V128-NEXT: vwaddu.vv v0, v8, v16
; RV32-V128-NEXT: li a0, -1 ; RV32-V128-NEXT: li a0, -1
; RV32-V128-NEXT: vwmaccu.vx v0, a0, v24 ; RV32-V128-NEXT: vwmaccu.vx v0, a0, v16
; RV32-V128-NEXT: vmv8r.v v8, v0 ; RV32-V128-NEXT: vmv8r.v v8, v0
; RV32-V128-NEXT: vmv8r.v v16, v24
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: li a1, 24 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: add sp, sp, a0 ; RV32-V128-NEXT: add sp, sp, a0
; RV32-V128-NEXT: addi sp, sp, 16 ; RV32-V128-NEXT: addi sp, sp, 16
; RV32-V128-NEXT: ret ; RV32-V128-NEXT: ret
; ;
; RV64-V128-LABEL: interleave_v32f32: ; RV64-V128-LABEL: interleave_v32f32:
; RV64-V128: # %bb.0: ; RV64-V128: # %bb.0:
; RV64-V128-NEXT: addi sp, sp, -16 ; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16 ; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: li a1, 24 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: sub sp, sp, a0 ; RV64-V128-NEXT: sub sp, sp, a0
; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: lui a0, %hi(.LCPI10_0)
; RV64-V128-NEXT: slli a0, a0, 3 ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_0)
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: li a1, 32
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vle32.v v0, (a0)
; RV64-V128-NEXT: vmv8r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: li a0, 32 ; RV64-V128-NEXT: vrgather.vv v8, v24, v0
; RV64-V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV64-V128-NEXT: lui a0, %hi(.LCPI10_1)
; RV64-V128-NEXT: lui a1, %hi(.LCPI10_1) ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI10_1)
; RV64-V128-NEXT: addi a1, a1, %lo(.LCPI10_1) ; RV64-V128-NEXT: vle32.v v24, (a0)
; RV64-V128-NEXT: vle32.v v0, (a1)
; RV64-V128-NEXT: lui a1, %hi(.LCPI10_0)
; RV64-V128-NEXT: addi a1, a1, %lo(.LCPI10_0)
; RV64-V128-NEXT: vle32.v v16, (a1)
; RV64-V128-NEXT: csrr a1, vlenb
; RV64-V128-NEXT: slli a1, a1, 4
; RV64-V128-NEXT: add a1, sp, a1
; RV64-V128-NEXT: addi a1, a1, 16
; RV64-V128-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-V128-NEXT: vrgather.vv v16, v8, v0
; RV64-V128-NEXT: lui a1, 699051
; RV64-V128-NEXT: addiw a1, a1, -1366
; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-V128-NEXT: vmv.v.x v0, a1
; RV64-V128-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 4 ; RV64-V128-NEXT: slli a0, a0, 3
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, 699051
; RV64-V128-NEXT: addiw a0, a0, -1366
; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-V128-NEXT: vmv.v.x v0, a0
; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 3 ; RV64-V128-NEXT: slli a0, a0, 3
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV64-V128-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV64-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV64-V128-NEXT: vmv.v.v v24, v8
; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-V128-NEXT: vmv4r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-V128-NEXT: vwaddu.vv v0, v8, v24 ; RV64-V128-NEXT: vwaddu.vv v0, v8, v16
; RV64-V128-NEXT: li a0, -1 ; RV64-V128-NEXT: li a0, -1
; RV64-V128-NEXT: vwmaccu.vx v0, a0, v24 ; RV64-V128-NEXT: vwmaccu.vx v0, a0, v16
; RV64-V128-NEXT: vmv8r.v v8, v0 ; RV64-V128-NEXT: vmv8r.v v8, v0
; RV64-V128-NEXT: vmv8r.v v16, v24
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: li a1, 24 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: add sp, sp, a0 ; RV64-V128-NEXT: add sp, sp, a0
; RV64-V128-NEXT: addi sp, sp, 16 ; RV64-V128-NEXT: addi sp, sp, 16
; RV64-V128-NEXT: ret ; RV64-V128-NEXT: ret
; ;
; V512-LABEL: interleave_v32f32: ; V512-LABEL: interleave_v32f32:
; V512: # %bb.0: ; V512: # %bb.0:
; V512-NEXT: li a0, 32 ; V512-NEXT: li a0, 32
; V512-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; V512-NEXT: vsetvli zero, a0, e32, m2, ta, ma
▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-shuffles.ll

Show First 20 Lines • Show All 132 Lines • ▼ Show 20 Lines
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5> %s = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
ret <4 x double> %s ret <4 x double> %s
} }
define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) { define <4 x double> @vrgather_shuffle_xv_v4f64(<4 x double> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v4f64: ; RV32-LABEL: vrgather_shuffle_xv_v4f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vid.v v12
; RV32-NEXT: lui a0, %hi(.LCPI7_0) ; RV32-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI7_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV32-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; RV32-NEXT: vlse64.v v10, (a0), zero ; RV32-NEXT: vlse64.v v10, (a0), zero
; RV32-NEXT: vid.v v12
; RV32-NEXT: vrsub.vi v12, v12, 4 ; RV32-NEXT: vrsub.vi v12, v12, 4
; RV32-NEXT: vmv.v.i v0, 12 ; RV32-NEXT: vmv.v.i v0, 12
; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m2, ta, mu
; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t ; RV32-NEXT: vrgatherei16.vv v10, v8, v12, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_xv_v4f64: ; RV64-LABEL: vrgather_shuffle_xv_v4f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vid.v v10
; RV64-NEXT: vrsub.vi v12, v10, 4
; RV64-NEXT: lui a0, %hi(.LCPI7_0) ; RV64-NEXT: lui a0, %hi(.LCPI7_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI7_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64-NEXT: vlse64.v v10, (a0), zero ; RV64-NEXT: vlse64.v v10, (a0), zero
; RV64-NEXT: vid.v v12
; RV64-NEXT: vrsub.vi v12, v12, 4
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.i v0, 12 ; RV64-NEXT: vmv.v.i v0, 12
; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu ; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, mu
; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t ; RV64-NEXT: vrgather.vv v10, v8, v12, v0.t
; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5> %s = shufflevector <4 x double> <double 2.0, double 2.0, double 2.0, double 2.0>, <4 x double> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x double> %s ret <4 x double> %s
▲ Show 20 Lines • Show All 158 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll

Show First 20 Lines • Show All 408 Lines • ▼ Show 20 Lines
} }
define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) { define <64 x i32> @interleave_v32i32(<32 x i32> %x, <32 x i32> %y) {
; RV32-V128-LABEL: interleave_v32i32: ; RV32-V128-LABEL: interleave_v32i32:
; RV32-V128: # %bb.0: ; RV32-V128: # %bb.0:
; RV32-V128-NEXT: addi sp, sp, -16 ; RV32-V128-NEXT: addi sp, sp, -16
; RV32-V128-NEXT: .cfi_def_cfa_offset 16 ; RV32-V128-NEXT: .cfi_def_cfa_offset 16
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: li a1, 24 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: sub sp, sp, a0 ; RV32-V128-NEXT: sub sp, sp, a0
; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV32-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: lui a0, %hi(.LCPI17_0)
; RV32-V128-NEXT: slli a0, a0, 3 ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: li a1, 32
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV32-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vle32.v v0, (a0)
; RV32-V128-NEXT: vmv8r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV32-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: li a0, 32 ; RV32-V128-NEXT: vrgather.vv v8, v24, v0
; RV32-V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV32-V128-NEXT: lui a0, %hi(.LCPI17_1)
; RV32-V128-NEXT: lui a1, %hi(.LCPI17_1) ; RV32-V128-NEXT: addi a0, a0, %lo(.LCPI17_1)
; RV32-V128-NEXT: addi a1, a1, %lo(.LCPI17_1) ; RV32-V128-NEXT: vle32.v v24, (a0)
; RV32-V128-NEXT: vle32.v v0, (a1)
; RV32-V128-NEXT: lui a1, %hi(.LCPI17_0)
; RV32-V128-NEXT: addi a1, a1, %lo(.LCPI17_0)
; RV32-V128-NEXT: vle32.v v16, (a1)
; RV32-V128-NEXT: csrr a1, vlenb
; RV32-V128-NEXT: slli a1, a1, 4
; RV32-V128-NEXT: add a1, sp, a1
; RV32-V128-NEXT: addi a1, a1, 16
; RV32-V128-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV32-V128-NEXT: vrgather.vv v16, v8, v0
; RV32-V128-NEXT: lui a1, 699051
; RV32-V128-NEXT: addi a1, a1, -1366
; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-V128-NEXT: vmv.v.x v0, a1
; RV32-V128-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 4 ; RV32-V128-NEXT: slli a0, a0, 3
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV32-V128-NEXT: lui a0, 699051
; RV32-V128-NEXT: addi a0, a0, -1366
; RV32-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV32-V128-NEXT: vmv.v.x v0, a0
; RV32-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: slli a0, a0, 3 ; RV32-V128-NEXT: slli a0, a0, 3
; RV32-V128-NEXT: add a0, sp, a0 ; RV32-V128-NEXT: add a0, sp, a0
; RV32-V128-NEXT: addi a0, a0, 16 ; RV32-V128-NEXT: addi a0, a0, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV32-V128-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV32-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV32-V128-NEXT: vmv.v.v v24, v8
; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV32-V128-NEXT: vmv4r.v v24, v8
; RV32-V128-NEXT: addi a0, sp, 16 ; RV32-V128-NEXT: addi a0, sp, 16
; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV32-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV32-V128-NEXT: vwaddu.vv v0, v8, v24 ; RV32-V128-NEXT: vwaddu.vv v0, v8, v16
; RV32-V128-NEXT: li a0, -1 ; RV32-V128-NEXT: li a0, -1
; RV32-V128-NEXT: vwmaccu.vx v0, a0, v24 ; RV32-V128-NEXT: vwmaccu.vx v0, a0, v16
; RV32-V128-NEXT: vmv8r.v v8, v0 ; RV32-V128-NEXT: vmv8r.v v8, v0
; RV32-V128-NEXT: vmv8r.v v16, v24
; RV32-V128-NEXT: csrr a0, vlenb ; RV32-V128-NEXT: csrr a0, vlenb
; RV32-V128-NEXT: li a1, 24 ; RV32-V128-NEXT: slli a0, a0, 4
; RV32-V128-NEXT: mul a0, a0, a1
; RV32-V128-NEXT: add sp, sp, a0 ; RV32-V128-NEXT: add sp, sp, a0
; RV32-V128-NEXT: addi sp, sp, 16 ; RV32-V128-NEXT: addi sp, sp, 16
; RV32-V128-NEXT: ret ; RV32-V128-NEXT: ret
; ;
; RV64-V128-LABEL: interleave_v32i32: ; RV64-V128-LABEL: interleave_v32i32:
; RV64-V128: # %bb.0: ; RV64-V128: # %bb.0:
; RV64-V128-NEXT: addi sp, sp, -16 ; RV64-V128-NEXT: addi sp, sp, -16
; RV64-V128-NEXT: .cfi_def_cfa_offset 16 ; RV64-V128-NEXT: .cfi_def_cfa_offset 16
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: li a1, 24 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: sub sp, sp, a0 ; RV64-V128-NEXT: sub sp, sp, a0
; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; RV64-V128-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x10, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 16 * vlenb
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: lui a0, %hi(.LCPI17_0)
; RV64-V128-NEXT: slli a0, a0, 3 ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: li a1, 32
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, ma
; RV64-V128-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vle32.v v0, (a0)
; RV64-V128-NEXT: vmv8r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill ; RV64-V128-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: li a0, 32 ; RV64-V128-NEXT: vrgather.vv v8, v24, v0
; RV64-V128-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; RV64-V128-NEXT: lui a0, %hi(.LCPI17_1)
; RV64-V128-NEXT: lui a1, %hi(.LCPI17_1) ; RV64-V128-NEXT: addi a0, a0, %lo(.LCPI17_1)
; RV64-V128-NEXT: addi a1, a1, %lo(.LCPI17_1) ; RV64-V128-NEXT: vle32.v v24, (a0)
; RV64-V128-NEXT: vle32.v v0, (a1)
; RV64-V128-NEXT: lui a1, %hi(.LCPI17_0)
; RV64-V128-NEXT: addi a1, a1, %lo(.LCPI17_0)
; RV64-V128-NEXT: vle32.v v16, (a1)
; RV64-V128-NEXT: csrr a1, vlenb
; RV64-V128-NEXT: slli a1, a1, 4
; RV64-V128-NEXT: add a1, sp, a1
; RV64-V128-NEXT: addi a1, a1, 16
; RV64-V128-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-V128-NEXT: vrgather.vv v16, v8, v0
; RV64-V128-NEXT: lui a1, 699051
; RV64-V128-NEXT: addiw a1, a1, -1366
; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-V128-NEXT: vmv.v.x v0, a1
; RV64-V128-NEXT: vsetvli zero, a0, e32, m8, ta, mu
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 4 ; RV64-V128-NEXT: slli a0, a0, 3
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; RV64-V128-NEXT: lui a0, 699051
; RV64-V128-NEXT: addiw a0, a0, -1366
; RV64-V128-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
; RV64-V128-NEXT: vmv.v.x v0, a0
; RV64-V128-NEXT: vsetvli zero, a1, e32, m8, ta, mu
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: slli a0, a0, 3 ; RV64-V128-NEXT: slli a0, a0, 3
; RV64-V128-NEXT: add a0, sp, a0 ; RV64-V128-NEXT: add a0, sp, a0
; RV64-V128-NEXT: addi a0, a0, 16 ; RV64-V128-NEXT: addi a0, a0, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; RV64-V128-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV64-V128-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV64-V128-NEXT: vmv.v.v v24, v8
; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV64-V128-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; RV64-V128-NEXT: vmv4r.v v24, v8
; RV64-V128-NEXT: addi a0, sp, 16 ; RV64-V128-NEXT: addi a0, sp, 16
; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload ; RV64-V128-NEXT: vl8r.v v8, (a0) # Unknown-size Folded Reload
; RV64-V128-NEXT: vwaddu.vv v0, v8, v24 ; RV64-V128-NEXT: vwaddu.vv v0, v8, v16
; RV64-V128-NEXT: li a0, -1 ; RV64-V128-NEXT: li a0, -1
; RV64-V128-NEXT: vwmaccu.vx v0, a0, v24 ; RV64-V128-NEXT: vwmaccu.vx v0, a0, v16
; RV64-V128-NEXT: vmv8r.v v8, v0 ; RV64-V128-NEXT: vmv8r.v v8, v0
; RV64-V128-NEXT: vmv8r.v v16, v24
; RV64-V128-NEXT: csrr a0, vlenb ; RV64-V128-NEXT: csrr a0, vlenb
; RV64-V128-NEXT: li a1, 24 ; RV64-V128-NEXT: slli a0, a0, 4
; RV64-V128-NEXT: mul a0, a0, a1
; RV64-V128-NEXT: add sp, sp, a0 ; RV64-V128-NEXT: add sp, sp, a0
; RV64-V128-NEXT: addi sp, sp, 16 ; RV64-V128-NEXT: addi sp, sp, 16
; RV64-V128-NEXT: ret ; RV64-V128-NEXT: ret
; ;
; V512-LABEL: interleave_v32i32: ; V512-LABEL: interleave_v32i32:
; V512: # %bb.0: ; V512: # %bb.0:
; V512-NEXT: li a0, 32 ; V512-NEXT: li a0, 32
; V512-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; V512-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

Show First 20 Lines • Show All 93 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5> %s = shufflevector <4 x i16> %x, <4 x i16> %y, <4 x i32> <i32 1, i32 2, i32 0, i32 5>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) { define <4 x i16> @vrgather_shuffle_xv_v4i16(<4 x i16> %x) {
; CHECK-LABEL: vrgather_shuffle_xv_v4i16: ; CHECK-LABEL: vrgather_shuffle_xv_v4i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu
; CHECK-NEXT: vmv.v.i v9, 5 ; CHECK-NEXT: vid.v v9
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vrsub.vi v10, v9, 4
; CHECK-NEXT: vmv.v.i v0, 12 ; CHECK-NEXT: vmv.v.i v0, 12
; CHECK-NEXT: vrsub.vi v10, v10, 4 ; CHECK-NEXT: vmv.v.i v9, 5
; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t ; CHECK-NEXT: vrgather.vv v9, v8, v10, v0.t
; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: vmv1r.v v8, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5> %s = shufflevector <4 x i16> <i16 5, i16 5, i16 5, i16 5>, <4 x i16> %x, <4 x i32> <i32 0, i32 3, i32 6, i32 5>
ret <4 x i16> %s ret <4 x i16> %s
} }
define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) { define <4 x i16> @vrgather_shuffle_vx_v4i16(<4 x i16> %x) {
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; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> poison, <8 x i64> %x, <8 x i32> <i32 9, i32 10, i32 8, i32 9, i32 15, i32 8, i32 8, i32 11> %s = shufflevector <8 x i64> poison, <8 x i64> %x, <8 x i32> <i32 9, i32 10, i32 8, i32 9, i32 15, i32 8, i32 8, i32 11>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) {
; RV32-LABEL: vrgather_shuffle_vv_v8i64: ; RV32-LABEL: vrgather_shuffle_vv_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; RV32-NEXT: vmv.v.i v16, 5
; RV32-NEXT: lui a0, %hi(.LCPI11_0) ; RV32-NEXT: lui a0, %hi(.LCPI11_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vle16.v v20, (a0) ; RV32-NEXT: vle16.v v20, (a0)
; RV32-NEXT: vmv.v.i v21, 2
; RV32-NEXT: vslideup.vi v21, v16, 7
; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, ma
; RV32-NEXT: vrgatherei16.vv v16, v8, v20 ; RV32-NEXT: vrgatherei16.vv v16, v8, v20
; RV32-NEXT: vsetvli zero, zero, e16, m1, ta, ma
; RV32-NEXT: vmv.v.i v8, 5
; RV32-NEXT: vmv.v.i v9, 2
; RV32-NEXT: vslideup.vi v9, v8, 7
; RV32-NEXT: li a0, 164 ; RV32-NEXT: li a0, 164
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v16, v12, v21, v0.t ; RV32-NEXT: vrgatherei16.vv v16, v12, v9, v0.t
; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: vmv.v.v v8, v16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_vv_v8i64: ; RV64-LABEL: vrgather_shuffle_vv_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: li a0, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.s.x v16, a0
; RV64-NEXT: vmv.v.i v20, 2
; RV64-NEXT: lui a0, %hi(.LCPI11_0) ; RV64-NEXT: lui a0, %hi(.LCPI11_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI11_0)
; RV64-NEXT: vle64.v v24, (a0) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vslideup.vi v20, v16, 7 ; RV64-NEXT: vle64.v v20, (a0)
; RV64-NEXT: vrgather.vv v16, v8, v24 ; RV64-NEXT: vmv4r.v v16, v8
; RV64-NEXT: vrgather.vv v8, v16, v20
; RV64-NEXT: li a0, 5
; RV64-NEXT: vmv.s.x v20, a0
; RV64-NEXT: vmv.v.i v16, 2
; RV64-NEXT: vslideup.vi v16, v20, 7
; RV64-NEXT: li a0, 164 ; RV64-NEXT: li a0, 164
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vrgather.vv v16, v12, v20, v0.t ; RV64-NEXT: vrgather.vv v8, v12, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13> %s = shufflevector <8 x i64> %x, <8 x i64> %y, <8 x i32> <i32 1, i32 2, i32 10, i32 5, i32 1, i32 10, i32 3, i32 13>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_xv_v8i64: ; RV32-LABEL: vrgather_shuffle_xv_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: lui a0, %hi(.LCPI12_0) ; RV32-NEXT: lui a0, %hi(.LCPI12_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV32-NEXT: vle16.v v17, (a0) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vmv.v.i v20, -1 ; RV32-NEXT: vmv.v.i v20, -1
; RV32-NEXT: vrgatherei16.vv v12, v20, v16 ; RV32-NEXT: vrgatherei16.vv v12, v20, v16
; RV32-NEXT: lui a0, %hi(.LCPI12_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1)
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: li a0, 113 ; RV32-NEXT: li a0, 113
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_xv_v8i64: ; RV64-LABEL: vrgather_shuffle_xv_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI12_0) ; RV64-NEXT: lui a0, %hi(.LCPI12_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI12_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vle64.v v16, (a0) ; RV64-NEXT: vle64.v v16, (a0)
; RV64-NEXT: li a0, 113 ; RV64-NEXT: li a0, 113
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vmv.v.i v12, -1 ; RV64-NEXT: vmv.v.i v12, -1
; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t ; RV64-NEXT: vrgather.vv v12, v8, v16, v0.t
; RV64-NEXT: vmv.v.v v8, v12 ; RV64-NEXT: vmv.v.v v8, v12
; RV64-NEXT: ret ; RV64-NEXT: ret
%s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3> %s = shufflevector <8 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <8 x i64> %x, <8 x i32> <i32 8, i32 3, i32 6, i32 5, i32 8, i32 12, i32 14, i32 3>
ret <8 x i64> %s ret <8 x i64> %s
} }
define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) { define <8 x i64> @vrgather_shuffle_vx_v8i64(<8 x i64> %x) {
; RV32-LABEL: vrgather_shuffle_vx_v8i64: ; RV32-LABEL: vrgather_shuffle_vx_v8i64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: lui a0, %hi(.LCPI13_0) ; RV32-NEXT: lui a0, %hi(.LCPI13_0)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV32-NEXT: vle16.v v17, (a0) ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV32-NEXT: vle16.v v16, (a0)
; RV32-NEXT: vrgatherei16.vv v12, v8, v16 ; RV32-NEXT: vrgatherei16.vv v12, v8, v16
; RV32-NEXT: lui a0, %hi(.LCPI13_1)
; RV32-NEXT: addi a0, a0, %lo(.LCPI13_1)
; RV32-NEXT: vle16.v v8, (a0)
; RV32-NEXT: li a0, 140 ; RV32-NEXT: li a0, 140
; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV32-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV32-NEXT: vmv.v.i v8, 5 ; RV32-NEXT: vmv.v.i v16, 5
; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t ; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: vmv.v.v v8, v12
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vrgather_shuffle_vx_v8i64: ; RV64-LABEL: vrgather_shuffle_vx_v8i64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: lui a0, %hi(.LCPI13_0) ; RV64-NEXT: lui a0, %hi(.LCPI13_0)
; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0) ; RV64-NEXT: addi a0, a0, %lo(.LCPI13_0)
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
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; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4> %shuff = shufflevector <8 x i8> %v, <8 x i8> poison, <8 x i32> <i32 4, i32 3, i32 4, i32 4, i32 4, i32 4, i32 4, i32 4>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0: ; CHECK-LABEL: splat_ve2_we0:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: li a0, 66 ; CHECK-NEXT: li a0, 66
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t ; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
Show All 14 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 4, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i0we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i0we4: ; CHECK-LABEL: splat_ve2_we0_ins_i0we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: li a0, 67
; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v8, 4 ; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 12, i32 8, i32 2, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
Show All 30 Lines; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: splat_ve2_we0_ins_i2we4: ; CHECK-LABEL: splat_ve2_we0_ins_i2we4:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; CHECK-NEXT: vmv.v.i v10, 4 ; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vmv.v.i v8, 4
; CHECK-NEXT: vmv.v.i v11, 0 ; CHECK-NEXT: vmv.v.i v11, 0
; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma
; CHECK-NEXT: vslideup.vi v11, v10, 2 ; CHECK-NEXT: vslideup.vi v11, v8, 2
; CHECK-NEXT: li a0, 70 ; CHECK-NEXT: li a0, 70
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vrgather.vi v10, v8, 2
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 12, i32 2, i32 2, i32 2, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) {
; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV32-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vmv.v.i v10, 6
; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV32-NEXT: vslideup.vi v11, v10, 5
; RV32-NEXT: lui a0, 8256 ; RV32-NEXT: lui a0, 8256
; RV32-NEXT: addi a0, a0, 2 ; RV32-NEXT: addi a0, a0, 2
; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV32-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV32-NEXT: vmv.v.x v12, a0 ; RV32-NEXT: vmv.v.x v11, a0
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV32-NEXT: vrgather.vv v10, v8, v11
; RV32-NEXT: vmv.v.i v8, 6
; RV32-NEXT: vmv.v.i v11, 0
; RV32-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV32-NEXT: vslideup.vi v11, v8, 5
; RV32-NEXT: li a0, 98 ; RV32-NEXT: li a0, 98
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vrgather.vv v10, v8, v12 ; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV32-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV32-NEXT: vmv1r.v v8, v10 ; RV32-NEXT: vmv1r.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6: ; RV64-LABEL: splat_ve2_we0_ins_i2ve4_i5we6:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vmv.v.i v10, 6
; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV64-NEXT: vslideup.vi v11, v10, 5
; RV64-NEXT: lui a0, 8256 ; RV64-NEXT: lui a0, 8256
; RV64-NEXT: addiw a0, a0, 2 ; RV64-NEXT: addiw a0, a0, 2
; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; RV64-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
; RV64-NEXT: vmv.v.x v12, a0 ; RV64-NEXT: vmv.v.x v11, a0
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64-NEXT: vrgather.vv v10, v8, v11
; RV64-NEXT: vmv.v.i v8, 6
; RV64-NEXT: vmv.v.i v11, 0
; RV64-NEXT: vsetivli zero, 6, e8, mf2, tu, ma
; RV64-NEXT: vslideup.vi v11, v8, 5
; RV64-NEXT: li a0, 98 ; RV64-NEXT: li a0, 98
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vrgather.vv v10, v8, v12 ; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV64-NEXT: vrgather.vv v10, v9, v11, v0.t
; RV64-NEXT: vmv1r.v v8, v10 ; RV64-NEXT: vmv1r.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2> %shuff = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 2, i32 2, i32 14, i32 8, i32 2>
ret <8 x i8> %shuff ret <8 x i8> %shuff
} }
define <8 x i8> @widen_splat_ve3(<4 x i8> %v) { define <8 x i8> @widen_splat_ve3(<4 x i8> %v) {
▲ Show 20 Lines • Show All 226 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 10, i32 6, i32 12, i32 13, i32 14> %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 8, i32 4, i32 10, i32 6, i32 12, i32 13, i32 14>
ret <8 x i8> %res ret <8 x i8> %res
} }
; This shouldn't generate a vmerge because the elements of %w are not consecutive ; This shouldn't generate a vmerge because the elements of %w are not consecutive
define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) { define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) {
; CHECK-LABEL: unmergable: ; CHECK-LABEL: unmergable:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu
; CHECK-NEXT: vle8.v v11, (a0)
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vadd.vi v12, v10, 2 ; CHECK-NEXT: vadd.vi v11, v10, 2
; CHECK-NEXT: lui a0, %hi(.LCPI46_0)
; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0)
; CHECK-NEXT: vle8.v v12, (a0)
; CHECK-NEXT: li a0, 234 ; CHECK-NEXT: li a0, 234
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v11
; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v12, v0.t
; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: vmv1r.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 9, i32 4, i32 11, i32 6, i32 13, i32 8, i32 15> %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> <i32 2, i32 9, i32 4, i32 11, i32 6, i32 13, i32 8, i32 15>
ret <8 x i8> %res ret <8 x i8> %res
} }

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,243 Lines • ▼ Show 20 Lines
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vle16.v v8, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI67_0) ; CHECK-NEXT: lui a1, %hi(.LCPI67_0)
; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0) ; CHECK-NEXT: addi a1, a1, %lo(.LCPI67_0)
; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; CHECK-NEXT: vle16.v v9, (a1) ; CHECK-NEXT: vle16.v v9, (a1)
; CHECK-NEXT: vdivu.vv v9, v8, v9 ; CHECK-NEXT: vdivu.vv v9, v8, v9
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vid.v v10 ; CHECK-NEXT: vid.v v10
; CHECK-NEXT: vadd.vi v10, v10, 12 ; CHECK-NEXT: vadd.vi v10, v10, 12
; CHECK-NEXT: vsetivli zero, 2, e16, m1, ta, ma
; CHECK-NEXT: vslidedown.vi v8, v8, 4
; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
; CHECK-NEXT: vdivu.vv v8, v8, v10 ; CHECK-NEXT: vdivu.vv v8, v8, v10
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vslideup.vi v9, v8, 4 ; CHECK-NEXT: vslideup.vi v9, v8, 4
; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 6, e16, m1, ta, ma
; CHECK-NEXT: vse16.v v9, (a0) ; CHECK-NEXT: vse16.v v9, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <6 x i16>, ptr %x %a = load <6 x i16>, ptr %x
%b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13> %b = udiv <6 x i16> %a, <i16 7, i16 9, i16 10, i16 11, i16 12, i16 13>
▲ Show 20 Lines • Show All 4,453 Lines • ▼ Show 20 Lines
; LMULMAX1-RV64-NEXT: vid.v v12 ; LMULMAX1-RV64-NEXT: vid.v v12
; LMULMAX1-RV64-NEXT: vrsub.vi v13, v12, 0 ; LMULMAX1-RV64-NEXT: vrsub.vi v13, v12, 0
; LMULMAX1-RV64-NEXT: vmacc.vv v11, v13, v9 ; LMULMAX1-RV64-NEXT: vmacc.vv v11, v13, v9
; LMULMAX1-RV64-NEXT: li a2, 63 ; LMULMAX1-RV64-NEXT: li a2, 63
; LMULMAX1-RV64-NEXT: vsrl.vx v9, v11, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v9, v11, a2
; LMULMAX1-RV64-NEXT: vsra.vv v11, v11, v12 ; LMULMAX1-RV64-NEXT: vsra.vv v11, v11, v12
; LMULMAX1-RV64-NEXT: vadd.vv v9, v11, v9 ; LMULMAX1-RV64-NEXT: vadd.vv v9, v11, v9
; LMULMAX1-RV64-NEXT: vmulh.vv v10, v8, v10 ; LMULMAX1-RV64-NEXT: vmulh.vv v10, v8, v10
; LMULMAX1-RV64-NEXT: vmacc.vv v10, v13, v8 ; LMULMAX1-RV64-NEXT: vmacc.vv v10, v8, v13
; LMULMAX1-RV64-NEXT: vsrl.vx v8, v10, a2 ; LMULMAX1-RV64-NEXT: vsrl.vx v8, v10, a2
; LMULMAX1-RV64-NEXT: vsra.vv v10, v10, v12 ; LMULMAX1-RV64-NEXT: vsra.vv v10, v10, v12
; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8 ; LMULMAX1-RV64-NEXT: vadd.vv v8, v10, v8
; LMULMAX1-RV64-NEXT: vse64.v v8, (a0) ; LMULMAX1-RV64-NEXT: vse64.v v8, (a0)
; LMULMAX1-RV64-NEXT: vse64.v v9, (a1) ; LMULMAX1-RV64-NEXT: vse64.v v9, (a1)
; LMULMAX1-RV64-NEXT: ret ; LMULMAX1-RV64-NEXT: ret
%a = load <4 x i64>, ptr %x %a = load <4 x i64>, ptr %x
%b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3> %b = sdiv <4 x i64> %a, <i64 3, i64 -3, i64 3, i64 -3>
▲ Show 20 Lines • Show All 2,743 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll

Show First 20 Lines • Show All 650 Lines • ▼ Show 20 Lines
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: load_factor6_too_big: ; RV64-LABEL: load_factor6_too_big:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 86 ; RV64-NEXT: li a3, 92
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: sub sp, sp, a2 ; RV64-NEXT: sub sp, sp, a2
; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xd6, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 86 * vlenb ; RV64-NEXT: .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0xdc, 0x00, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 92 * vlenb
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: addi a2, a1, 256 ; RV64-NEXT: addi a2, a1, 256
; RV64-NEXT: vle64.v v16, (a2) ; RV64-NEXT: vle64.v v16, (a2)
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 53 ; RV64-NEXT: li a3, 68
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: addi a2, a1, 128 ; RV64-NEXT: addi a2, a1, 128
; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: vle64.v v8, (a2)
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 77 ; RV64-NEXT: li a3, 84
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vle64.v v8, (a1) ; RV64-NEXT: vle64.v v24, (a1)
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vrgather.vi v8, v16, 4 ; RV64-NEXT: vrgather.vi v8, v16, 4
; RV64-NEXT: li a1, 128 ; RV64-NEXT: li a1, 128
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v1, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
; RV64-NEXT: vslidedown.vi v24, v16, 8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma
; RV64-NEXT: vmv1r.v v0, v1 ; RV64-NEXT: vslidedown.vi v16, v16, 8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: li a2, 52
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v1, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vi v8, v24, 2, v0.t ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: vrgather.vi v8, v16, 2, v0.t
; RV64-NEXT: vmv.v.v v4, v8 ; RV64-NEXT: vmv.v.v v4, v8
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: li a1, 6 ; RV64-NEXT: li a1, 6
; RV64-NEXT: vid.v v16 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vmul.vx v24, v16, a1 ; RV64-NEXT: vmul.vx v8, v8, a1
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: li a1, 56 ; RV64-NEXT: li a1, 56
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 69 ; RV64-NEXT: li a3, 60
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v24, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vv v16, v24, v8
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 76
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v8, v8, -16
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 44
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vv v16, v8, v24
; RV64-NEXT: vadd.vi v24, v24, -16
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 37 ; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v4, v16 ; RV64-NEXT: vmv.v.v v4, v16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 25 ; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v12, v8, 5 ; RV64-NEXT: vrgather.vi v16, v0, 5
; RV64-NEXT: vmv1r.v v0, v1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v12, v24, 3, v0.t ; RV64-NEXT: vrgather.vi v16, v24, 3, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 41 ; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v0, v8, 1 ; RV64-NEXT: vadd.vi v0, v8, 1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v0 ; RV64-NEXT: vrgather.vv v16, v24, v0
; RV64-NEXT: vadd.vi v24, v8, -15 ; RV64-NEXT: vadd.vi v24, v8, -15
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 37 ; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 41 ; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 41 ; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; RV64-NEXT: vmv.v.i v8, 6 ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29 ; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.s.x v12, zero ; RV64-NEXT: vmv.v.v v20, v16
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 3 ; RV64-NEXT: li a2, 44
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vslideup.vi v8, v12, 5 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v12, v16, v8 ; RV64-NEXT: vadd.vi v8, v24, 2
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: li a2, 60
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v0, v8
; RV64-NEXT: li a1, 24
; RV64-NEXT: vadd.vi v8, v24, -14
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vi v12, v16, 4, v0.t ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 37 ; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: vmv.v.i v12, 6
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v8, v0, 2 ; RV64-NEXT: vmv.s.x v8, zero
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vrgather.vv v16, v24, v8 ; RV64-NEXT: vslideup.vi v12, v8, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 4 ; RV64-NEXT: li a2, 68
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: li a1, 24 ; RV64-NEXT: vrgather.vv v20, v0, v12
; RV64-NEXT: vadd.vi v8, v0, -14
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 4 ; RV64-NEXT: li a2, 52
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v24, v16, v8, v0.t ; RV64-NEXT: vrgather.vi v20, v8, 4, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: vmv.v.v v20, v16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 37 ; RV64-NEXT: slli a1, a1, 5
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vmv.v.v v8, v24 ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 37 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vadd.vi v0, v8, 3
; RV64-NEXT: li a1, 1
; RV64-NEXT: vmv.v.i v8, 7
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 4
; RV64-NEXT: add a2, a3, a2
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs4r.v v8, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vmv.s.x v12, a1
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 13 ; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vslideup.vi v8, v12, 5 ; RV64-NEXT: vrgather.vv v16, v24, v0
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vmv.v.v v24, v16
; RV64-NEXT: vadd.vi v16, v8, -13
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 24
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v12, v16, v8
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v12, v16, 5, v0.t ; RV64-NEXT: vrgather.vv v24, v8, v16, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: li a2, 24
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: li a1, 1
; RV64-NEXT: vmv.v.i v20, 7
; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 20
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs4r.v v20, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vmv.s.x v8, a1
; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v24, v0, 3 ; RV64-NEXT: vslideup.vi v20, v8, 5
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v16, v24 ; RV64-NEXT: vrgather.vv v8, v24, v20
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vadd.vi v16, v0, -13
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: vrgather.vi v8, v24, 5, v0.t
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: li a2, 24
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v8 ; RV64-NEXT: vmv.v.v v8, v16
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 5 ; RV64-NEXT: li a2, 24
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 3 ; RV64-NEXT: li a2, 12
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29 ; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v20, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vslideup.vi v16, v8, 6 ; RV64-NEXT: vslideup.vi v20, v8, 6
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: li a1, 192 ; RV64-NEXT: li a1, 192
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 53 ; RV64-NEXT: li a3, 68
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl8r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v20, v8, 2 ; RV64-NEXT: vrgather.vi v8, v24, 2
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 3 ; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v20, v8, v16, v0.t ; RV64-NEXT: vrgather.vv v8, v24, v20, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v24, v0, 4 ; RV64-NEXT: vadd.vi v0, v24, 4
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v16, v24 ; RV64-NEXT: vrgather.vv v8, v16, v0
; RV64-NEXT: li a1, 28 ; RV64-NEXT: li a1, 28
; RV64-NEXT: vadd.vi v16, v0, -12 ; RV64-NEXT: vadd.vi v16, v24, -12
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: addi a2, sp, 16
; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a1 ; RV64-NEXT: vmv.v.x v0, a1
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t ; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v16, v24, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v8 ; RV64-NEXT: vmv.v.v v12, v8
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 29 ; RV64-NEXT: li a2, 40
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 7, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 13 ; RV64-NEXT: slli a1, a1, 3
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 4 ; RV64-NEXT: li a2, 20
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vslideup.vi v24, v8, 6 ; RV64-NEXT: vslideup.vi v4, v8, 6
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vi v16, v8, 3 ; RV64-NEXT: vrgather.vi v8, v16, 3
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 3 ; RV64-NEXT: slli a1, a1, 4
; RV64-NEXT: add a1, a2, a1
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 45 ; RV64-NEXT: li a2, 52
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v8, v24, v0.t ; RV64-NEXT: vrgather.vv v8, v16, v4, v0.t
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 4 ; RV64-NEXT: li a2, 20
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, mu
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v24, v8, 5 ; RV64-NEXT: vadd.vi v0, v16, 5
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 60
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v8, v0, v24 ; RV64-NEXT: vrgather.vv v8, v16, v0
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 61 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vadd.vi v8, v24, -11 ; RV64-NEXT: vadd.vi v24, v24, -11
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill
; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 12
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill
; RV64-NEXT: addi a1, sp, 16
; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 77 ; RV64-NEXT: li a2, 84
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 69 ; RV64-NEXT: li a2, 76
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 53 ; RV64-NEXT: li a2, 68
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vrgather.vv v16, v24, v8, v0.t ; RV64-NEXT: vrgather.vv v8, v24, v16, v0.t
; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: slli a2, a1, 4 ; RV64-NEXT: li a2, 20
; RV64-NEXT: add a1, a2, a1 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vmv.v.v v12, v16 ; RV64-NEXT: vmv.v.v v12, v8
; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 25 ; RV64-NEXT: li a2, 36
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v16, (a0)
; RV64-NEXT: addi a1, a0, 320 ; RV64-NEXT: addi a1, a0, 320
; RV64-NEXT: vse64.v v12, (a1) ; RV64-NEXT: vse64.v v12, (a1)
; RV64-NEXT: addi a1, a0, 256 ; RV64-NEXT: addi a1, a0, 256
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 29 ; RV64-NEXT: li a3, 40
; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 192 ; RV64-NEXT: addi a1, a0, 192
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a3, a2, 5 ; RV64-NEXT: li a3, 24
; RV64-NEXT: add a2, a3, a2 ; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: addi a1, a0, 128
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: li a3, 37 ; RV64-NEXT: slli a2, a2, 5
; RV64-NEXT: mul a2, a2, a3
; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: add a2, sp, a2
; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: addi a2, a2, 16
; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: vse64.v v8, (a1)
; RV64-NEXT: addi a0, a0, 64 ; RV64-NEXT: addi a0, a0, 64
; RV64-NEXT: csrr a1, vlenb ; RV64-NEXT: csrr a1, vlenb
; RV64-NEXT: li a2, 41 ; RV64-NEXT: li a2, 44
; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: mul a1, a1, a2
; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: add a1, sp, a1
; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: addi a1, a1, 16
; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload
; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: vse64.v v8, (a0)
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: li a1, 86 ; RV64-NEXT: li a1, 92
; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: mul a0, a0, a1
; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: add sp, sp, a0
; RV64-NEXT: addi sp, sp, 16 ; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret ; RV64-NEXT: ret
%interleaved.vec = load <48 x i64>, ptr %ptr %interleaved.vec = load <48 x i64>, ptr %ptr
%v0 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 18, i32 24, i32 30, i32 36, i32 42> %v0 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 0, i32 6, i32 12, i32 18, i32 24, i32 30, i32 36, i32 42>
%v1 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 19, i32 25, i32 31, i32 37, i32 43> %v1 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 1, i32 7, i32 13, i32 19, i32 25, i32 31, i32 37, i32 43>
%v2 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 2, i32 8, i32 14, i32 20, i32 26, i32 32, i32 38, i32 44> %v2 = shufflevector <48 x i64> %interleaved.vec, <48 x i64> poison, <8 x i32> <i32 2, i32 8, i32 14, i32 20, i32 26, i32 32, i32 38, i32 44>
▲ Show 20 Lines • Show All 83 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll

Show All 36 Lines
} }
define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) { define <16 x i8> @trn1.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
; RV32-LABEL: trn1.v16i8: ; RV32-LABEL: trn1.v16i8:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vid.v v11 ; RV32-NEXT: vid.v v11
; RV32-NEXT: vrgather.vv v10, v8, v11 ; RV32-NEXT: vrgather.vv v10, v8, v11
; RV32-NEXT: vadd.vi v8, v11, -1
; RV32-NEXT: lui a0, 11 ; RV32-NEXT: lui a0, 11
; RV32-NEXT: addi a0, a0, -1366 ; RV32-NEXT: addi a0, a0, -1366
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vadd.vi v8, v11, -1
; RV32-NEXT: vrgather.vv v10, v9, v8, v0.t ; RV32-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV32-NEXT: vmv.v.v v8, v10 ; RV32-NEXT: vmv.v.v v8, v10
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: trn1.v16i8: ; RV64-LABEL: trn1.v16i8:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vid.v v11 ; RV64-NEXT: vid.v v11
; RV64-NEXT: vrgather.vv v10, v8, v11 ; RV64-NEXT: vrgather.vv v10, v8, v11
; RV64-NEXT: vadd.vi v8, v11, -1
; RV64-NEXT: lui a0, 11 ; RV64-NEXT: lui a0, 11
; RV64-NEXT: addiw a0, a0, -1366 ; RV64-NEXT: addiw a0, a0, -1366
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vadd.vi v8, v11, -1
; RV64-NEXT: vrgather.vv v10, v9, v8, v0.t ; RV64-NEXT: vrgather.vv v10, v9, v8, v0.t
; RV64-NEXT: vmv.v.v v8, v10 ; RV64-NEXT: vmv.v.v v8, v10
; RV64-NEXT: ret ; RV64-NEXT: ret
%tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30> %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 16, i32 2, i32 18, i32 4, i32 20, i32 6, i32 22, i32 8, i32 24, i32 10, i32 26, i32 12, i32 28, i32 14, i32 30>
ret <16 x i8> %tmp0 ret <16 x i8> %tmp0
} }
define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) { define <16 x i8> @trn2.v16i8(<16 x i8> %v0, <16 x i8> %v1) {
▲ Show 20 Lines • Show All 308 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll

Show First 20 Lines • Show All 2,293 Lines • ▼ Show 20 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsll.vi v24, v8, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: bltu a1, a3, .LBB93_2
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB93_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16 ; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB93_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB93_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: addi sp, sp, -16
; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: .cfi_def_cfa_offset 16
; RV64-NEXT: csrr a2, vlenb ; RV64-NEXT: csrr a2, vlenb
; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: slli a2, a2, 3
Show All 36 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i32> %idxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_sext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsll.vi v24, v8, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: bltu a1, a3, .LBB94_2
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB94_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16 ; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB94_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB94_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_sext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
Show All 22 Lines; RV64-NEXT: ret
%ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs %ptrs = getelementptr inbounds double, ptr %base, <32 x i64> %eidxs
%v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl) %v = call <32 x double> @llvm.vp.gather.v32f64.v32p0(<32 x ptr> %ptrs, <32 x i1> %m, i32 %evl)
ret <32 x double> %v ret <32 x double> %v
} }
define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) { define <32 x double> @vpgather_baseidx_zext_v32i32_v32f64(ptr %base, <32 x i32> %idxs, <32 x i1> %m, i32 zeroext %evl) {
; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV32-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV32: # %bb.0: ; RV32: # %bb.0:
; RV32-NEXT: vmv1r.v v1, v0
; RV32-NEXT: li a2, 32 ; RV32-NEXT: li a2, 32
; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma
; RV32-NEXT: vsll.vi v24, v8, 3 ; RV32-NEXT: li a3, 16
; RV32-NEXT: addi a2, a1, -16 ; RV32-NEXT: vsll.vi v16, v8, 3
; RV32-NEXT: sltu a3, a1, a2 ; RV32-NEXT: mv a2, a1
; RV32-NEXT: addi a3, a3, -1 ; RV32-NEXT: bltu a1, a3, .LBB95_2
; RV32-NEXT: and a2, a3, a2 ; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a2, 16
; RV32-NEXT: .LBB95_2:
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v8, (a0), v16, v0.t
; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV32-NEXT: vslidedown.vi v8, v24, 16 ; RV32-NEXT: vslidedown.vi v24, v16, 16
; RV32-NEXT: addi a2, a1, -16
; RV32-NEXT: sltu a1, a1, a2
; RV32-NEXT: addi a1, a1, -1
; RV32-NEXT: and a1, a1, a2
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetvli zero, a2, e64, m8, ta, ma
; RV32-NEXT: vluxei32.v v16, (a0), v8, v0.t
; RV32-NEXT: li a2, 16
; RV32-NEXT: bltu a1, a2, .LBB95_2
; RV32-NEXT: # %bb.1:
; RV32-NEXT: li a1, 16
; RV32-NEXT: .LBB95_2:
; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; RV32-NEXT: vsetvli zero, a1, e64, m8, ta, ma
; RV32-NEXT: vmv1r.v v0, v1 ; RV32-NEXT: vluxei32.v v16, (a0), v24, v0.t
; RV32-NEXT: vluxei32.v v8, (a0), v24, v0.t
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64: ; RV64-LABEL: vpgather_baseidx_zext_v32i32_v32f64:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vmv1r.v v24, v0 ; RV64-NEXT: vmv1r.v v24, v0
; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e32, m8, ta, ma
; RV64-NEXT: vslidedown.vi v16, v8, 16 ; RV64-NEXT: vslidedown.vi v16, v8, 16
; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma
▲ Show 20 Lines • Show All 84 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/mask-reg-alloc.mir

Show All 14 Lines bb.0 (%ir-block.0):
liveins: $v0, $v1, $v2, $v3 liveins: $v0, $v1, $v2, $v3
; CHECK-LABEL: name: mask_reg_alloc ; CHECK-LABEL: name: mask_reg_alloc
; CHECK: liveins: $v0, $v1, $v2, $v3 ; CHECK: liveins: $v0, $v1, $v2, $v3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 1, 192 /* e8, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v8 = PseudoVMERGE_VIM_M1 killed renamable $v2, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1 ; CHECK-NEXT: renamable $v0 = COPY killed renamable $v1
; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v9 = PseudoVMERGE_VIM_M1 killed renamable $v3, 1, killed renamable $v0, 1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: renamable $v0 = PseudoVADD_VV_M1 undef renamable $v0, killed renamable $v8, killed renamable $v9, 1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoRET implicit $v0 ; CHECK-NEXT: PseudoRET implicit $v0
%0:vr = COPY $v0 %0:vr = COPY $v0
%1:vr = COPY $v1 %1:vr = COPY $v1
%2:vr = COPY $v2 %2:vr = COPY $v2
%3:vr = COPY $v3 %3:vr = COPY $v3
%4:vmv0 = COPY %0 %4:vmv0 = COPY %0
%5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, 1, 3 %5:vrnov0 = PseudoVMERGE_VIM_M1 killed %2, 1, %4, 1, 3
%6:vmv0 = COPY %1 %6:vmv0 = COPY %1
%7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, 1, 3 %7:vrnov0 = PseudoVMERGE_VIM_M1 killed %3, 1, %6, 1, 3
%8:vr = PseudoVADD_VV_M1 killed %5, killed %7, 1, 3 %pt:vr = IMPLICIT_DEF
%8:vr = PseudoVADD_VV_M1 %pt, killed %5, killed %7, 1, 3, 0
$v0 = COPY %8 $v0 = COPY %8
PseudoRET implicit $v0 PseudoRET implicit $v0
... ...

llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll

Show First 20 Lines • Show All 203 Lines • ▼ Show 20 Lines
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a) %res = call <vscale x 4 x i1> @llvm.experimental.vector.reverse.nxv4i1(<vscale x 4 x i1> %a)
ret <vscale x 4 x i1> %res ret <vscale x 4 x i1> %res
} }
define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) { define <vscale x 8 x i1> @reverse_nxv8i1(<vscale x 8 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v10 ; RV32-BITS-UNKNOWN-NEXT: vid.v v8
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v11, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv8i1: ; RV32-BITS-256-LABEL: reverse_nxv8i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vid.v v9 ; RV32-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-256-NEXT: vid.v v8
; RV32-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-256-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-256-NEXT: vmv.v.i v9, 0
; RV32-BITS-256-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-BITS-256-NEXT: vrgather.vv v10, v9, v8
; RV32-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v10, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv8i1: ; RV32-BITS-512-LABEL: reverse_nxv8i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vid.v v9 ; RV32-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV32-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV32-BITS-512-NEXT: vid.v v8
; RV32-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-512-NEXT: vmv.v.i v9, 0
; RV32-BITS-512-NEXT: vmerge.vim v9, v9, 1, v0
; RV32-BITS-512-NEXT: vrgather.vv v10, v9, v8
; RV32-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v10, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv8i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v10 ; RV64-BITS-UNKNOWN-NEXT: vid.v v8
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v10, v10, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m1, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v9, v8, v10 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v10, 0
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v9, 1 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v10, v10, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v11, v10, v8
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v11, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv8i1: ; RV64-BITS-256-LABEL: reverse_nxv8i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vid.v v9 ; RV64-BITS-256-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV64-BITS-256-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-256-NEXT: vid.v v8
; RV64-BITS-256-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-256-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-256-NEXT: vmv.v.i v9, 0
; RV64-BITS-256-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-BITS-256-NEXT: vrgather.vv v10, v9, v8
; RV64-BITS-256-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v10, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv8i1: ; RV64-BITS-512-LABEL: reverse_nxv8i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m1, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vid.v v9 ; RV64-BITS-512-NEXT: vsetvli a1, zero, e8, m1, ta, ma
; RV64-BITS-512-NEXT: vrsub.vx v9, v9, a0 ; RV64-BITS-512-NEXT: vid.v v8
; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v9 ; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-512-NEXT: vmv.v.i v9, 0
; RV64-BITS-512-NEXT: vmerge.vim v9, v9, 1, v0
; RV64-BITS-512-NEXT: vrgather.vv v10, v9, v8
; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a) %res = call <vscale x 8 x i1> @llvm.experimental.vector.reverse.nxv8i1(<vscale x 8 x i1> %a)
ret <vscale x 8 x i1> %res ret <vscale x 8 x i1> %res
} }
define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) { define <vscale x 16 x i1> @reverse_nxv16i1(<vscale x 16 x i1> %a) {
▲ Show 20 Lines • Show All 190 Lines • ▼ Show 20 Lines
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a) %res = call <vscale x 32 x i1> @llvm.experimental.vector.reverse.nxv32i1(<vscale x 32 x i1> %a)
ret <vscale x 32 x i1> %res ret <vscale x 32 x i1> %res
} }
define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) { define <vscale x 64 x i1> @reverse_nxv64i1(<vscale x 64 x i1> %a) {
; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1: ; RV32-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV32-BITS-UNKNOWN: # %bb.0: ; RV32-BITS-UNKNOWN: # %bb.0:
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vid.v v16 ; RV32-BITS-UNKNOWN-NEXT: vid.v v8
; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV32-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV32-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV32-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16 ; RV32-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v12, v16 ; RV32-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV32-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-UNKNOWN-NEXT: ret ; RV32-BITS-UNKNOWN-NEXT: ret
; ;
; RV32-BITS-256-LABEL: reverse_nxv64i1: ; RV32-BITS-256-LABEL: reverse_nxv64i1:
; RV32-BITS-256: # %bb.0: ; RV32-BITS-256: # %bb.0:
; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-256-NEXT: vmv.v.i v8, 0 ; RV32-BITS-256-NEXT: vmv.v.i v8, 0
; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-256-NEXT: vid.v v16 ; RV32-BITS-256-NEXT: vid.v v16
; RV32-BITS-256-NEXT: csrr a0, vlenb ; RV32-BITS-256-NEXT: csrr a0, vlenb
; RV32-BITS-256-NEXT: slli a0, a0, 3 ; RV32-BITS-256-NEXT: slli a0, a0, 3
; RV32-BITS-256-NEXT: addi a0, a0, -1 ; RV32-BITS-256-NEXT: addi a0, a0, -1
; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16 ; RV32-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV32-BITS-256-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-256-NEXT: vand.vi v8, v24, 1
; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-256-NEXT: ret ; RV32-BITS-256-NEXT: ret
; ;
; RV32-BITS-512-LABEL: reverse_nxv64i1: ; RV32-BITS-512-LABEL: reverse_nxv64i1:
; RV32-BITS-512: # %bb.0: ; RV32-BITS-512: # %bb.0:
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vmv.v.i v8, 0
; RV32-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vid.v v16 ; RV32-BITS-512-NEXT: vid.v v8
; RV32-BITS-512-NEXT: csrr a0, vlenb ; RV32-BITS-512-NEXT: csrr a0, vlenb
; RV32-BITS-512-NEXT: slli a0, a0, 2 ; RV32-BITS-512-NEXT: slli a0, a0, 2
; RV32-BITS-512-NEXT: addi a0, a0, -1 ; RV32-BITS-512-NEXT: addi a0, a0, -1
; RV32-BITS-512-NEXT: vrsub.vx v16, v16, a0 ; RV32-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV32-BITS-512-NEXT: vrgather.vv v28, v8, v16 ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vrgather.vv v24, v12, v16 ; RV32-BITS-512-NEXT: vmv.v.i v16, 0
; RV32-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV32-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV32-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV32-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV32-BITS-512-NEXT: vand.vi v8, v24, 1 ; RV32-BITS-512-NEXT: vand.vi v8, v24, 1
; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV32-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV32-BITS-512-NEXT: ret ; RV32-BITS-512-NEXT: ret
; ;
; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1: ; RV64-BITS-UNKNOWN-LABEL: reverse_nxv64i1:
; RV64-BITS-UNKNOWN: # %bb.0: ; RV64-BITS-UNKNOWN: # %bb.0:
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v8, 0
; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e16, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vid.v v16 ; RV64-BITS-UNKNOWN-NEXT: vid.v v8
; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb ; RV64-BITS-UNKNOWN-NEXT: csrr a0, vlenb
; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2 ; RV64-BITS-UNKNOWN-NEXT: slli a0, a0, 2
; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1 ; RV64-BITS-UNKNOWN-NEXT: addi a0, a0, -1
; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-UNKNOWN-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-UNKNOWN-NEXT: vsetvli zero, zero, e8, m4, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v8, v16 ; RV64-BITS-UNKNOWN-NEXT: vmv.v.i v16, 0
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v12, v16 ; RV64-BITS-UNKNOWN-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v28, v16, v8
; RV64-BITS-UNKNOWN-NEXT: vrgatherei16.vv v24, v20, v8
; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-UNKNOWN-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-UNKNOWN-NEXT: vand.vi v8, v24, 1
; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-UNKNOWN-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-UNKNOWN-NEXT: ret ; RV64-BITS-UNKNOWN-NEXT: ret
; ;
; RV64-BITS-256-LABEL: reverse_nxv64i1: ; RV64-BITS-256-LABEL: reverse_nxv64i1:
; RV64-BITS-256: # %bb.0: ; RV64-BITS-256: # %bb.0:
; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-256-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-256-NEXT: vmv.v.i v8, 0 ; RV64-BITS-256-NEXT: vmv.v.i v8, 0
; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-BITS-256-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-256-NEXT: vid.v v16 ; RV64-BITS-256-NEXT: vid.v v16
; RV64-BITS-256-NEXT: csrr a0, vlenb ; RV64-BITS-256-NEXT: csrr a0, vlenb
; RV64-BITS-256-NEXT: slli a0, a0, 3 ; RV64-BITS-256-NEXT: slli a0, a0, 3
; RV64-BITS-256-NEXT: addi a0, a0, -1 ; RV64-BITS-256-NEXT: addi a0, a0, -1
; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-256-NEXT: vrsub.vx v16, v16, a0
; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16 ; RV64-BITS-256-NEXT: vrgather.vv v24, v8, v16
; RV64-BITS-256-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-256-NEXT: vand.vi v8, v24, 1
; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-256-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-256-NEXT: ret ; RV64-BITS-256-NEXT: ret
; ;
; RV64-BITS-512-LABEL: reverse_nxv64i1: ; RV64-BITS-512-LABEL: reverse_nxv64i1:
; RV64-BITS-512: # %bb.0: ; RV64-BITS-512: # %bb.0:
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vmv.v.i v8, 0
; RV64-BITS-512-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vid.v v16 ; RV64-BITS-512-NEXT: vid.v v8
; RV64-BITS-512-NEXT: csrr a0, vlenb ; RV64-BITS-512-NEXT: csrr a0, vlenb
; RV64-BITS-512-NEXT: slli a0, a0, 2 ; RV64-BITS-512-NEXT: slli a0, a0, 2
; RV64-BITS-512-NEXT: addi a0, a0, -1 ; RV64-BITS-512-NEXT: addi a0, a0, -1
; RV64-BITS-512-NEXT: vrsub.vx v16, v16, a0 ; RV64-BITS-512-NEXT: vrsub.vx v8, v8, a0
; RV64-BITS-512-NEXT: vrgather.vv v28, v8, v16 ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vrgather.vv v24, v12, v16 ; RV64-BITS-512-NEXT: vmv.v.i v16, 0
; RV64-BITS-512-NEXT: vmerge.vim v16, v16, 1, v0
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; RV64-BITS-512-NEXT: vrgather.vv v28, v16, v8
; RV64-BITS-512-NEXT: vrgather.vv v24, v20, v8
; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; RV64-BITS-512-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; RV64-BITS-512-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-512-NEXT: vand.vi v8, v24, 1
; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0
; RV64-BITS-512-NEXT: ret ; RV64-BITS-512-NEXT: ret
%res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a) %res = call <vscale x 64 x i1> @llvm.experimental.vector.reverse.nxv64i1(<vscale x 64 x i1> %a)
ret <vscale x 64 x i1> %res ret <vscale x 64 x i1> %res
} }
▲ Show 20 Lines • Show All 1,329 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/reg-coalescing.mir

Show All 10 Lines bb.0:
; CHECK: liveins: $x10 ; CHECK: liveins: $x10
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: undef %1.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: undef %1.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %pt2:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt2:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: %1.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: %1.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %pt3:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt3:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: undef early-clobber %5.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %1.sub_vrm2_0, 0, 1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: undef early-clobber %5.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %5.sub_vrm2_0, %1.sub_vrm2_0, 0, 1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: %5.sub_vrm2_1:vrn2m2 = COPY %1.sub_vrm2_1 ; CHECK-NEXT: %5.sub_vrm2_1:vrn2m2 = COPY %1.sub_vrm2_1
; CHECK-NEXT: PseudoVSUXSEG2EI32_V_M2_M2 %5, $x10, [[PseudoVLE32_V_M2_]], 1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSUXSEG2EI32_V_M2_M2 %5, $x10, [[PseudoVLE32_V_M2_]], 1, 5 /* e32 */, implicit $vl, implicit $vtype
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5, 0 undef %0.sub_vrm2_0:vrn2m2 = PseudoVLE32_V_M2 %pt, $x10, 1, 5, 0
%pt2:vrm2 = IMPLICIT_DEF %pt2:vrm2 = IMPLICIT_DEF
%0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5, 0 %0.sub_vrm2_1:vrn2m2 = PseudoVLE32_V_M2 %pt2, $x10, 1, 5, 0
%pt3:vrm2 = IMPLICIT_DEF %pt3:vrm2 = IMPLICIT_DEF
%1:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5, 0 %1:vrm2 = PseudoVLE32_V_M2 %pt3, $x10, 1, 5, 0
undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 %0.sub_vrm2_0:vrn2m2, 0, 1, 5, implicit $vl, implicit $vtype undef early-clobber %2.sub_vrm2_0:vrn2m2 = PseudoVRGATHER_VI_M2 undef %2.sub_vrm2_0, %0.sub_vrm2_0:vrn2m2, 0, 1, 5, 0, implicit $vl, implicit $vtype
%2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1:vrn2m2 %2.sub_vrm2_1:vrn2m2 = COPY %0.sub_vrm2_1:vrn2m2
PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype PseudoVSUXSEG2EI32_V_M2_M2 %2:vrn2m2, $x10, %1:vrm2, 1, 5, implicit $vl, implicit $vtype
... ...

llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll

Show All 9 Lines
; SPILL-O0-LABEL: foo: ; SPILL-O0-LABEL: foo:
; SPILL-O0: # %bb.0: ; SPILL-O0: # %bb.0:
; SPILL-O0-NEXT: addi sp, sp, -32 ; SPILL-O0-NEXT: addi sp, sp, -32
; SPILL-O0-NEXT: sw ra, 28(sp) # 4-byte Folded Spill ; SPILL-O0-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: slli a1, a1, 1 ; SPILL-O0-NEXT: slli a1, a1, 1
; SPILL-O0-NEXT: sub sp, sp, a1 ; SPILL-O0-NEXT: sub sp, sp, a1
; SPILL-O0-NEXT: sw a0, 8(sp) # 4-byte Folded Spill ; SPILL-O0-NEXT: sw a0, 8(sp) # 4-byte Folded Spill
; SPILL-O0-NEXT: vmv1r.v v10, v9
; SPILL-O0-NEXT: vmv1r.v v9, v8
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16 ; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: vfadd.vv v8, v8, v9 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: addi a0, sp, 16 ; SPILL-O0-NEXT: addi a0, sp, 16
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str) ; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str) ; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts@plt ; SPILL-O0-NEXT: call puts@plt
; SPILL-O0-NEXT: addi a1, sp, 16 ; SPILL-O0-NEXT: addi a1, sp, 16
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 16 ; SPILL-O0-NEXT: addi a1, a1, 16
; SPILL-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10 ; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload ; SPILL-O0-NEXT: lw a0, 8(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: vfadd.vv v8, v8, v9 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: csrr a0, vlenb ; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1 ; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0 ; SPILL-O0-NEXT: add sp, sp, a0
; SPILL-O0-NEXT: lw ra, 28(sp) # 4-byte Folded Reload ; SPILL-O0-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; SPILL-O0-NEXT: addi sp, sp, 32 ; SPILL-O0-NEXT: addi sp, sp, 32
; SPILL-O0-NEXT: ret ; SPILL-O0-NEXT: ret
; ;
; SPILL-O2-LABEL: foo: ; SPILL-O2-LABEL: foo:
▲ Show 20 Lines • Show All 43 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll

Show All 12 Lines
; SPILL-O0-LABEL: foo: ; SPILL-O0-LABEL: foo:
; SPILL-O0: # %bb.0: ; SPILL-O0: # %bb.0:
; SPILL-O0-NEXT: addi sp, sp, -48 ; SPILL-O0-NEXT: addi sp, sp, -48
; SPILL-O0-NEXT: sd ra, 40(sp) # 8-byte Folded Spill ; SPILL-O0-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: slli a1, a1, 1 ; SPILL-O0-NEXT: slli a1, a1, 1
; SPILL-O0-NEXT: sub sp, sp, a1 ; SPILL-O0-NEXT: sub sp, sp, a1
; SPILL-O0-NEXT: sd a0, 16(sp) # 8-byte Folded Spill ; SPILL-O0-NEXT: sd a0, 16(sp) # 8-byte Folded Spill
; SPILL-O0-NEXT: vmv1r.v v10, v9
; SPILL-O0-NEXT: vmv1r.v v9, v8
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 32 ; SPILL-O0-NEXT: addi a1, a1, 32
; SPILL-O0-NEXT: vs1r.v v8, (a1) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v9, (a1) # Unknown-size Folded Spill
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: vfadd.vv v8, v8, v9 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: addi a0, sp, 32 ; SPILL-O0-NEXT: addi a0, sp, 32
; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; SPILL-O0-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill
; SPILL-O0-NEXT: lui a0, %hi(.L.str) ; SPILL-O0-NEXT: lui a0, %hi(.L.str)
; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str) ; SPILL-O0-NEXT: addi a0, a0, %lo(.L.str)
; SPILL-O0-NEXT: call puts@plt ; SPILL-O0-NEXT: call puts@plt
; SPILL-O0-NEXT: addi a1, sp, 32 ; SPILL-O0-NEXT: addi a1, sp, 32
; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v10, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: csrr a1, vlenb ; SPILL-O0-NEXT: csrr a1, vlenb
; SPILL-O0-NEXT: add a1, sp, a1 ; SPILL-O0-NEXT: add a1, sp, a1
; SPILL-O0-NEXT: addi a1, a1, 32 ; SPILL-O0-NEXT: addi a1, a1, 32
; SPILL-O0-NEXT: vl1r.v v8, (a1) # Unknown-size Folded Reload ; SPILL-O0-NEXT: vl1r.v v9, (a1) # Unknown-size Folded Reload
; SPILL-O0-NEXT: # kill: def $x11 killed $x10 ; SPILL-O0-NEXT: # kill: def $x11 killed $x10
; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload ; SPILL-O0-NEXT: ld a0, 16(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: # implicit-def: $v8
; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; SPILL-O0-NEXT: vsetvli zero, a0, e64, m1, ta, ma
; SPILL-O0-NEXT: vfadd.vv v8, v8, v9 ; SPILL-O0-NEXT: vfadd.vv v8, v9, v10
; SPILL-O0-NEXT: csrr a0, vlenb ; SPILL-O0-NEXT: csrr a0, vlenb
; SPILL-O0-NEXT: slli a0, a0, 1 ; SPILL-O0-NEXT: slli a0, a0, 1
; SPILL-O0-NEXT: add sp, sp, a0 ; SPILL-O0-NEXT: add sp, sp, a0
; SPILL-O0-NEXT: ld ra, 40(sp) # 8-byte Folded Reload ; SPILL-O0-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; SPILL-O0-NEXT: addi sp, sp, 48 ; SPILL-O0-NEXT: addi sp, sp, 48
; SPILL-O0-NEXT: ret ; SPILL-O0-NEXT: ret
; ;
; SPILL-O2-LABEL: foo: ; SPILL-O2-LABEL: foo:
▲ Show 20 Lines • Show All 71 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Lines
define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) { define <16 x i8> @v8i8_2(<8 x i8> %a, <8 x i8> %b) {
; CHECK-LABEL: v8i8_2: ; CHECK-LABEL: v8i8_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vid.v v11
; CHECK-NEXT: vrsub.vi v12, v11, 15 ; CHECK-NEXT: vrsub.vi v12, v11, 15
; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v8, v12
; CHECK-NEXT: vrsub.vi v8, v11, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; CHECK-NEXT: vrsub.vi v8, v11, 7
; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i8 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i8 = shufflevector <8 x i8> %a, <8 x i8> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i8> %v16i8 ret <16 x i8> %v16i8
} }
define <16 x i8> @v16i8(<16 x i8> %a) { define <16 x i8> @v16i8(<16 x i8> %a) {
▲ Show 20 Lines • Show All 125 Lines • ▼ Show 20 Lines
define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) { define <16 x i16> @v8i16_2(<8 x i16> %a, <8 x i16> %b) {
; CHECK-LABEL: v8i16_2: ; CHECK-LABEL: v8i16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15 ; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i16 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i16 = shufflevector <8 x i16> %a, <8 x i16> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i16> %v16i16 ret <16 x i16> %v16i16
} }
define <16 x i16> @v16i16(<16 x i16> %a) { define <16 x i16> @v16i16(<16 x i16> %a) {
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines
define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) { define <16 x i32> @v8i32_2(<8 x i32> %a, <8 x i32> %b) {
; CHECK-LABEL: v8i32_2: ; CHECK-LABEL: v8i32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10 ; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vid.v v20 ; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15 ; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24 ; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t ; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16i32 = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16i32 = shufflevector <8 x i32> %a, <8 x i32> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x i32> %v16i32 ret <16 x i32> %v16i32
} }
define <16 x i32> @v16i32(<16 x i32> %a) { define <16 x i32> @v16i32(<16 x i32> %a) {
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define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) { define <16 x half> @v8f16_2(<8 x half> %a, <8 x half> %b) {
; CHECK-LABEL: v8f16_2: ; CHECK-LABEL: v8f16_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v12, v9 ; CHECK-NEXT: vmv1r.v v12, v9
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
; CHECK-NEXT: vid.v v14 ; CHECK-NEXT: vid.v v14
; CHECK-NEXT: vrsub.vi v16, v14, 15 ; CHECK-NEXT: vrsub.vi v16, v14, 15
; CHECK-NEXT: vrgather.vv v10, v8, v16 ; CHECK-NEXT: vrgather.vv v10, v8, v16
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, mu
; CHECK-NEXT: vrsub.vi v8, v14, 7
; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t ; CHECK-NEXT: vrgather.vv v10, v12, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v8, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16f16 = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16f16 = shufflevector <8 x half> %a, <8 x half> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x half> %v16f16 ret <16 x half> %v16f16
} }
define <16 x half> @v16f16(<16 x half> %a) { define <16 x half> @v16f16(<16 x half> %a) {
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define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) { define <16 x float> @v8f32_2(<8 x float> %a, <8 x float> %b) {
; CHECK-LABEL: v8f32_2: ; CHECK-LABEL: v8f32_2:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv2r.v v16, v10 ; CHECK-NEXT: vmv2r.v v16, v10
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, ma
; CHECK-NEXT: vid.v v20 ; CHECK-NEXT: vid.v v20
; CHECK-NEXT: vrsub.vi v24, v20, 15 ; CHECK-NEXT: vrsub.vi v24, v20, 15
; CHECK-NEXT: vrgather.vv v12, v8, v24 ; CHECK-NEXT: vrgather.vv v12, v8, v24
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: li a0, 255 ; CHECK-NEXT: li a0, 255
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; CHECK-NEXT: vmv.v.x v0, a0 ; CHECK-NEXT: vmv.v.x v0, a0
; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; CHECK-NEXT: vsetivli zero, 16, e32, m4, ta, mu
; CHECK-NEXT: vrsub.vi v8, v20, 7
; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t ; CHECK-NEXT: vrgather.vv v12, v16, v8, v0.t
; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v8, v12
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0> %v16f32 = shufflevector <8 x float> %a, <8 x float> %b, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
ret <16 x float> %v16f32 ret <16 x float> %v16f32
} }
define <2 x double> @v2f64(<2 x double> %a) { define <2 x double> @v2f64(<2 x double> %a) {
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llvm/test/CodeGen/RISCV/rvv/sshl_sat_vec.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s
declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>) declare <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64>, <2 x i64>)
declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>) declare <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>)
declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>) declare <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16>, <8 x i16>)
declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>) declare <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8>, <16 x i8>)
define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind { define <2 x i64> @vec_v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
; CHECK-LABEL: vec_v2i64: ; CHECK-LABEL: vec_v2i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a1 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsll.vv v11, v8, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9 ; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: li a0, -1
; CHECK-NEXT: srli a1, a0, 1
; CHECK-NEXT: vmv.v.x v11, a1
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: slli a0, a0, 63 ; CHECK-NEXT: slli a0, a0, 63
; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y) %tmp = call <2 x i64> @llvm.sshl.sat.v2i64(<2 x i64> %x, <2 x i64> %y)
ret <2 x i64> %tmp ret <2 x i64> %tmp
} }
define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind { define <4 x i32> @vec_v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {
; CHECK-LABEL: vec_v4i32: ; CHECK-LABEL: vec_v4i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsll.vv v11, v8, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9 ; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: lui a0, 524288
; CHECK-NEXT: addiw a0, a0, -1
; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 1 ; CHECK-NEXT: li a0, 1
; CHECK-NEXT: slli a0, a0, 31 ; CHECK-NEXT: slli a0, a0, 31
; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y) %tmp = call <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32> %x, <4 x i32> %y)
ret <4 x i32> %tmp ret <4 x i32> %tmp
} }
define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind { define <8 x i16> @vec_v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {
; CHECK-LABEL: vec_v8i16: ; CHECK-LABEL: vec_v8i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vsll.vv v10, v8, v9 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsra.vv v9, v10, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: vmv.v.x v9, a1 ; CHECK-NEXT: lui a0, 8
; CHECK-NEXT: vmerge.vxm v9, v9, a0, v0 ; CHECK-NEXT: addiw a1, a0, -1
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: vmerge.vvm v8, v10, v9, v0 ; CHECK-NEXT: vmv.v.x v8, a1
; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y) %tmp = call <8 x i16> @llvm.sshl.sat.v8i16(<8 x i16> %x, <8 x i16> %y)
ret <8 x i16> %tmp ret <8 x i16> %tmp
} }
define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind { define <16 x i8> @vec_v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
; CHECK-LABEL: vec_v16i8: ; CHECK-LABEL: vec_v16i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; CHECK-NEXT: vmv.v.x v10, a0 ; CHECK-NEXT: vsll.vv v10, v8, v9
; CHECK-NEXT: vsll.vv v11, v8, v9 ; CHECK-NEXT: vsra.vv v9, v10, v9
; CHECK-NEXT: vsra.vv v9, v11, v9
; CHECK-NEXT: vmsne.vv v9, v8, v9 ; CHECK-NEXT: vmsne.vv v9, v8, v9
; CHECK-NEXT: li a0, 127
; CHECK-NEXT: vmv.v.x v11, a0
; CHECK-NEXT: vmsle.vi v0, v8, -1 ; CHECK-NEXT: vmsle.vi v0, v8, -1
; CHECK-NEXT: li a0, 128 ; CHECK-NEXT: li a0, 128
; CHECK-NEXT: vmerge.vxm v8, v10, a0, v0 ; CHECK-NEXT: vmerge.vxm v8, v11, a0, v0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vmerge.vvm v8, v11, v8, v0 ; CHECK-NEXT: vmerge.vvm v8, v10, v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y) %tmp = call <16 x i8> @llvm.sshl.sat.v16i8(<16 x i8> %x, <16 x i8> %y)
ret <16 x i8> %tmp ret <16 x i8> %tmp
} }
declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>) declare <vscale x 2 x i64> @llvm.sshl.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>) declare <vscale x 4 x i32> @llvm.sshl.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>) declare <vscale x 8 x i16> @llvm.sshl.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
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llvm/test/CodeGen/RISCV/rvv/stepvector.ll

Show First 20 Lines • Show All 574 Lines • ▼ Show 20 Lines
; RV32-LABEL: add_stepvector_nxv16i64: ; RV32-LABEL: add_stepvector_nxv16i64:
; RV32: # %bb.0: # %entry ; RV32: # %bb.0: # %entry
; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: .cfi_def_cfa_offset 16
; RV32-NEXT: sw zero, 12(sp) ; RV32-NEXT: sw zero, 12(sp)
; RV32-NEXT: csrr a0, vlenb ; RV32-NEXT: csrr a0, vlenb
; RV32-NEXT: slli a0, a0, 1 ; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: sw a0, 8(sp) ; RV32-NEXT: sw a0, 8(sp)
; RV32-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV32-NEXT: addi a0, sp, 8 ; RV32-NEXT: addi a0, sp, 8
; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV32-NEXT: vlse64.v v16, (a0), zero ; RV32-NEXT: vlse64.v v16, (a0), zero
; RV32-NEXT: vid.v v8 ; RV32-NEXT: vid.v v8
; RV32-NEXT: vadd.vv v8, v8, v8 ; RV32-NEXT: vadd.vv v8, v8, v8
; RV32-NEXT: vadd.vv v16, v8, v16 ; RV32-NEXT: vadd.vv v16, v8, v16
; RV32-NEXT: addi sp, sp, 16 ; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: add_stepvector_nxv16i64: ; RV64-LABEL: add_stepvector_nxv16i64:
; RV64: # %bb.0: # %entry ; RV64: # %bb.0: # %entry
; RV64-NEXT: csrr a0, vlenb ; RV64-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma
; RV64-NEXT: vid.v v8 ; RV64-NEXT: vid.v v8
; RV64-NEXT: vadd.vv v8, v8, v8 ; RV64-NEXT: vadd.vv v8, v8, v8
; RV64-NEXT: csrr a0, vlenb
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: vadd.vx v16, v8, a0 ; RV64-NEXT: vadd.vx v16, v8, a0
; RV64-NEXT: ret ; RV64-NEXT: ret
entry: entry:
%0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %0 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64() %1 = call <vscale x 16 x i64> @llvm.experimental.stepvector.nxv16i64()
%2 = add <vscale x 16 x i64> %0, %1 %2 = add <vscale x 16 x i64> %0, %1
ret <vscale x 16 x i64> %2 ret <vscale x 16 x i64> %2
} }
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llvm/test/CodeGen/RISCV/rvv/subregister-undef-early-clobber.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=riscv-init-undef -o - | FileCheck %s # RUN: llc %s -mtriple=riscv64 -mattr=+v -riscv-enable-subreg-liveness -run-pass=riscv-init-undef -o - | FileCheck %s
... ...
--- ---
name: test_M4_sub_vrm1_0 name: test_M4_sub_vrm1_0
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm1_0 ; CHECK-LABEL: name: test_M4_sub_vrm1_0
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_0 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_0
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5/* e32 */, 0, implicit $vl, implicit $vtype
craig.topperUnsubmitted
Not Done
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Should this be IMPLICIT_DEF instead? I see some other IMPLICIT_DEFs and no undefs in the existing code.

craig.topper: Should this be IMPLICIT_DEF instead? I see some other IMPLICIT_DEFs and no undefs in the…
reamesAuthorUnsubmitted
Done
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Looks like it yeah. I got confused because this is post InsertVSETVLI. Seeing implicit vtype and implicit vl almost always means your post regalloc, and I apparently didn't look close enough. Update pending.

reames: Looks like it yeah. I got confused because this is post InsertVSETVLI. Seeing implicit vtype…
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M4_sub_vrm1_1 name: test_M4_sub_vrm1_1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm1_1 ; CHECK-LABEL: name: test_M4_sub_vrm1_1
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_1 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_1
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M4_sub_vrm1_2 name: test_M4_sub_vrm1_2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm1_2 ; CHECK-LABEL: name: test_M4_sub_vrm1_2
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_2 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_2
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M4_sub_vrm1_3 name: test_M4_sub_vrm1_3
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm1_3 ; CHECK-LABEL: name: test_M4_sub_vrm1_3
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_3 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm1_3
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M4_sub_vrm2_0 name: test_M4_sub_vrm2_0
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm2_0 ; CHECK-LABEL: name: test_M4_sub_vrm2_0
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_1
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_0
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M4_sub_vrm2_1 name: test_M4_sub_vrm2_1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M4_sub_vrm2_1 ; CHECK-LABEL: name: test_M4_sub_vrm2_1
; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm4 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm4 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: early-clobber %5:vrm4 = PseudoVRGATHER_VI_M4 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoRVVInitUndefM2_1:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_1]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_2:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm4 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM2_2]], %subreg.sub_vrm2_0
; CHECK-NEXT: early-clobber %6:vrm4 = PseudoVRGATHER_VI_M4 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M4 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M4 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm4 = IMPLICIT_DEF %1:vrm4 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_1 %6:vrm4 = INSERT_SUBREG %1:vrm4, %5, %subreg.sub_vrm2_1
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm4 = IMPLICIT_DEF
early-clobber %0:vrm4 = PseudoVRGATHER_VI_M4 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M4 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_0 name: test_M8_sub_vrm1_0
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_0 ; CHECK-LABEL: name: test_M8_sub_vrm1_0
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_0
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_1
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_0 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_0
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_1 name: test_M8_sub_vrm1_1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_1 ; CHECK-LABEL: name: test_M8_sub_vrm1_1
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_0
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_1 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_1
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_2 name: test_M8_sub_vrm1_2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_2 ; CHECK-LABEL: name: test_M8_sub_vrm1_2
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_2
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_3
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_2 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_2
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_3 name: test_M8_sub_vrm1_3
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_3 ; CHECK-LABEL: name: test_M8_sub_vrm1_3
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_3
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_2
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_3 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_3
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_4 name: test_M8_sub_vrm1_4
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_4 ; CHECK-LABEL: name: test_M8_sub_vrm1_4
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_4
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_5 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_5
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_4 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_4
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_5 name: test_M8_sub_vrm1_5
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_5 ; CHECK-LABEL: name: test_M8_sub_vrm1_5
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_5
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_4 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_4
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_5 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_5
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_6 name: test_M8_sub_vrm1_6
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_6 ; CHECK-LABEL: name: test_M8_sub_vrm1_6
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_6
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_7 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_7
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_6 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_6
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm1_7 name: test_M8_sub_vrm1_7
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm1_7 ; CHECK-LABEL: name: test_M8_sub_vrm1_7
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M1_]], %subreg.sub_vrm1_7
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1 ; CHECK-NEXT: [[PseudoRVVInitUndefM1_:%[0-9]+]]:vr = PseudoRVVInitUndefM1
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG2]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_6 ; CHECK-NEXT: [[INSERT_SUBREG5:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG4]], [[PseudoRVVInitUndefM1_]], %subreg.sub_vrm1_6
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG5]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0 %5:vr = PseudoVLE32_V_M1 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_7 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm1_7
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm2_0 name: test_M8_sub_vrm2_0
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm2_0 ; CHECK-LABEL: name: test_M8_sub_vrm2_0
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_1
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_0 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_0
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm2_1 name: test_M8_sub_vrm2_1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm2_1 ; CHECK-LABEL: name: test_M8_sub_vrm2_1
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_0
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_1 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_1
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm2_2 name: test_M8_sub_vrm2_2
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm2_2 ; CHECK-LABEL: name: test_M8_sub_vrm2_2
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_2
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_3
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_2 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_2
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm2_3 name: test_M8_sub_vrm2_3
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm2_3 ; CHECK-LABEL: name: test_M8_sub_vrm2_3
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm2 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M2_:%[0-9]+]]:vrm2 = PseudoVLE32_V_M2 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M2_]], %subreg.sub_vrm2_3
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2 ; CHECK-NEXT: [[PseudoRVVInitUndefM2_:%[0-9]+]]:vrm2 = PseudoRVVInitUndefM2
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2 ; CHECK-NEXT: [[INSERT_SUBREG4:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG3]], [[PseudoRVVInitUndefM2_]], %subreg.sub_vrm2_2
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG2]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG4]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm2 = IMPLICIT_DEF %pt:vrm2 = IMPLICIT_DEF
%5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0 %5:vrm2 = PseudoVLE32_V_M2 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_3 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm2_3
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm4_0 name: test_M8_sub_vrm4_0
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm4_0 ; CHECK-LABEL: name: test_M8_sub_vrm4_0
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_1
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm4 = IMPLICIT_DEF %pt:vrm4 = IMPLICIT_DEF
%5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_0 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_0
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
--- ---
name: test_M8_sub_vrm4_1 name: test_M8_sub_vrm4_1
body: | body: |
bb.0.entry: bb.0.entry:
; CHECK-LABEL: name: test_M8_sub_vrm4_1 ; CHECK-LABEL: name: test_M8_sub_vrm4_1
; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF ; CHECK: [[DEF:%[0-9]+]]:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, 8
; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF ; CHECK-NEXT: %pt:vrm4 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */ ; CHECK-NEXT: [[PseudoVLE32_V_M4_:%[0-9]+]]:vrm4 = PseudoVLE32_V_M4 %pt, killed [[ADDI]], 0, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:vrm8 = INSERT_SUBREG [[DEF]], [[PseudoVLE32_V_M4_]], %subreg.sub_vrm4_1
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: %pt2:vrm8 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4 ; CHECK-NEXT: [[PseudoRVVInitUndefM4_:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0 ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:vrm8 = INSERT_SUBREG %pt2, [[PseudoRVVInitUndefM4_]], %subreg.sub_vrm4_0
; CHECK-NEXT: early-clobber %5:vrm8 = PseudoVRGATHER_VI_M8 killed [[INSERT_SUBREG1]], 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoRVVInitUndefM4_1:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG1]], [[PseudoRVVInitUndefM4_1]], %subreg.sub_vrm4_1
; CHECK-NEXT: [[PseudoRVVInitUndefM4_2:%[0-9]+]]:vrm4 = PseudoRVVInitUndefM4
; CHECK-NEXT: [[INSERT_SUBREG3:%[0-9]+]]:vrm8 = INSERT_SUBREG [[INSERT_SUBREG]], [[PseudoRVVInitUndefM4_2]], %subreg.sub_vrm4_0
; CHECK-NEXT: early-clobber %6:vrm8 = PseudoVRGATHER_VI_M8 [[INSERT_SUBREG2]], killed [[INSERT_SUBREG3]], 0, 0, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI $x0, 0
; CHECK-NEXT: PseudoVSE32_V_M8 killed %5, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_M8 killed %6, killed [[ADDI1]], 0, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: $x10 = COPY [[COPY]] ; CHECK-NEXT: $x10 = COPY [[COPY]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
%1:vrm8 = IMPLICIT_DEF %1:vrm8 = IMPLICIT_DEF
%7:gpr = ADDI $x0, 8 %7:gpr = ADDI $x0, 8
%pt:vrm4 = IMPLICIT_DEF %pt:vrm4 = IMPLICIT_DEF
%5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0 %5:vrm4 = PseudoVLE32_V_M4 %pt, killed %7:gpr, 0, 5, 0
%6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_1 %6:vrm8 = INSERT_SUBREG %1:vrm8, %5, %subreg.sub_vrm4_1
dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETIVLI 0, 210 /* e32, m4, ta, ma */, implicit-def $vl, implicit-def $vtype
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 killed %6, 0, 0, 5 /* e32 */, implicit $vl, implicit $vtype %pt2:vrm8 = IMPLICIT_DEF
early-clobber %0:vrm8 = PseudoVRGATHER_VI_M8 %pt2, killed %6, 0, 0, 5 /* e32 */, 0, implicit $vl, implicit $vtype
%2:gpr = ADDI $x0, 0 %2:gpr = ADDI $x0, 0
PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype PseudoVSE32_V_M8 killed %0, killed %2, 0, 5 /* e32 */, implicit $vl, implicit $vtype
%3:gpr = COPY $x0 %3:gpr = COPY $x0
$x10 = COPY %3 $x10 = COPY %3
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll

Show All 11 Lines
; RV32-NEXT: vmerge.vim v10, v8, 1, v0 ; RV32-NEXT: vmerge.vim v10, v8, 1, v0
; RV32-NEXT: vid.v v9 ; RV32-NEXT: vid.v v9
; RV32-NEXT: vadd.vv v11, v9, v9 ; RV32-NEXT: vadd.vv v11, v9, v9
; RV32-NEXT: vrgather.vv v9, v10, v11 ; RV32-NEXT: vrgather.vv v9, v10, v11
; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV32-NEXT: vslidedown.vi v0, v0, 2 ; RV32-NEXT: vslidedown.vi v0, v0, 2
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV32-NEXT: vmerge.vim v8, v8, 1, v0 ; RV32-NEXT: vmerge.vim v8, v8, 1, v0
; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: lui a0, 16 ; RV32-NEXT: lui a0, 16
; RV32-NEXT: addi a0, a0, -256 ; RV32-NEXT: addi a0, a0, -256
; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV32-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV32-NEXT: vmv.v.x v0, a0 ; RV32-NEXT: vmv.v.x v0, a0
; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV32-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV32-NEXT: vadd.vi v12, v11, -16
; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t ; RV32-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV32-NEXT: vmsne.vi v9, v9, 0 ; RV32-NEXT: vmsne.vi v9, v9, 0
; RV32-NEXT: vadd.vi v12, v11, 1 ; RV32-NEXT: vadd.vi v12, v11, 1
; RV32-NEXT: vrgather.vv v13, v10, v12 ; RV32-NEXT: vrgather.vv v13, v10, v12
; RV32-NEXT: vadd.vi v10, v11, -15 ; RV32-NEXT: vadd.vi v10, v11, -15
; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t ; RV32-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV32-NEXT: vmsne.vi v8, v13, 0 ; RV32-NEXT: vmsne.vi v8, v13, 0
; RV32-NEXT: vmv.v.v v0, v9 ; RV32-NEXT: vmv.v.v v0, v9
; RV32-NEXT: ret ; RV32-NEXT: ret
; ;
; RV64-LABEL: vector_deinterleave_v16i1_v32i1: ; RV64-LABEL: vector_deinterleave_v16i1_v32i1:
; RV64: # %bb.0: ; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmv.v.i v8, 0 ; RV64-NEXT: vmv.v.i v8, 0
; RV64-NEXT: vmerge.vim v10, v8, 1, v0 ; RV64-NEXT: vmerge.vim v10, v8, 1, v0
; RV64-NEXT: vid.v v9 ; RV64-NEXT: vid.v v9
; RV64-NEXT: vadd.vv v11, v9, v9 ; RV64-NEXT: vadd.vv v11, v9, v9
; RV64-NEXT: vrgather.vv v9, v10, v11 ; RV64-NEXT: vrgather.vv v9, v10, v11
; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
; RV64-NEXT: vslidedown.vi v0, v0, 2 ; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, ma
; RV64-NEXT: vmerge.vim v8, v8, 1, v0 ; RV64-NEXT: vmerge.vim v8, v8, 1, v0
; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: lui a0, 16 ; RV64-NEXT: lui a0, 16
; RV64-NEXT: addiw a0, a0, -256 ; RV64-NEXT: addiw a0, a0, -256
; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; RV64-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
; RV64-NEXT: vmv.v.x v0, a0 ; RV64-NEXT: vmv.v.x v0, a0
; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu ; RV64-NEXT: vsetivli zero, 16, e8, m1, ta, mu
; RV64-NEXT: vadd.vi v12, v11, -16
; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t ; RV64-NEXT: vrgather.vv v9, v8, v12, v0.t
; RV64-NEXT: vmsne.vi v9, v9, 0 ; RV64-NEXT: vmsne.vi v9, v9, 0
; RV64-NEXT: vadd.vi v12, v11, 1 ; RV64-NEXT: vadd.vi v12, v11, 1
; RV64-NEXT: vrgather.vv v13, v10, v12 ; RV64-NEXT: vrgather.vv v13, v10, v12
; RV64-NEXT: vadd.vi v10, v11, -15 ; RV64-NEXT: vadd.vi v10, v11, -15
; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t ; RV64-NEXT: vrgather.vv v13, v8, v10, v0.t
; RV64-NEXT: vmsne.vi v8, v13, 0 ; RV64-NEXT: vmsne.vi v8, v13, 0
; RV64-NEXT: vmv.v.v v0, v9 ; RV64-NEXT: vmv.v.v v0, v9
Show All 40 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec) %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec)
ret {<4 x i32>, <4 x i32>} %retval ret {<4 x i32>, <4 x i32>} %retval
} }
define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) { define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_v2i64_v4i64: ; CHECK-LABEL: vector_deinterleave_v2i64_v4i64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2 ; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2 ; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v10, v12, 1, v0.t
; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vmv.v.v v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec) %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec)
ret {<2 x i64>, <2 x i64>} %retval ret {<2 x i64>, <2 x i64>} %retval
} }
declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>) declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>)
declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>)
declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>)
▲ Show 20 Lines • Show All 63 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec) %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec)
ret {<4 x float>, <4 x float>} %retval ret {<4 x float>, <4 x float>} %retval
} }
define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) { define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_v2f64_v4f64: ; CHECK-LABEL: vector_deinterleave_v2f64_v4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vrgather.vi v10, v8, 1
; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma ; CHECK-NEXT: vsetivli zero, 2, e64, m2, ta, ma
; CHECK-NEXT: vslidedown.vi v10, v8, 2 ; CHECK-NEXT: vslidedown.vi v12, v8, 2
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
; CHECK-NEXT: vmv.v.i v0, 2 ; CHECK-NEXT: vmv.v.i v0, 2
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vrgather.vi v9, v8, 1 ; CHECK-NEXT: vrgather.vi v10, v12, 1, v0.t
; CHECK-NEXT: vrgather.vi v9, v10, 1, v0.t ; CHECK-NEXT: vslideup.vi v8, v12, 1
; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: vmv.v.v v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec) %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec)
ret {<2 x double>, <2 x double>} %retval ret {<2 x double>, <2 x double>} %retval
} }
declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>)
declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>)
declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>) declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>)
declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>)
declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>)
declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>)

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll

Show First 20 Lines • Show All 107 Lines • ▼ Show 20 Lines
; CHECK-NEXT: mul a1, a1, a2 ; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: sub sp, sp, a1 ; CHECK-NEXT: sub sp, sp, a1
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb ; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x18, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 24 * vlenb
; CHECK-NEXT: csrr a1, vlenb ; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3 ; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add a1, a0, a1 ; CHECK-NEXT: add a1, a0, a1
; CHECK-NEXT: vl8re64.v v16, (a1) ; CHECK-NEXT: vl8re64.v v16, (a1)
; CHECK-NEXT: vl8re64.v v24, (a0) ; CHECK-NEXT: vl8re64.v v24, (a0)
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
; CHECK-NEXT: vid.v v8 ; CHECK-NEXT: vid.v v8
; CHECK-NEXT: vadd.vv v0, v8, v8 ; CHECK-NEXT: vadd.vv v0, v8, v8
; CHECK-NEXT: vrgather.vv v8, v24, v0 ; CHECK-NEXT: vrgather.vv v8, v16, v0
; CHECK-NEXT: vrgather.vv v24, v16, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill ; CHECK-NEXT: vs8r.v v8, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vrgather.vv v8, v24, v0
; CHECK-NEXT: vadd.vi v0, v0, 1 ; CHECK-NEXT: vadd.vi v0, v0, 1
; CHECK-NEXT: vrgather.vv v24, v16, v0 ; CHECK-NEXT: vrgather.vv v24, v16, v0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v24, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vrgather.vv v16, v24, v0 ; CHECK-NEXT: vrgather.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4 ; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v12, v24 ; CHECK-NEXT: vmv4r.v v12, v24
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v20, v24 ; CHECK-NEXT: vmv4r.v v20, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 24 ; CHECK-NEXT: li a1, 24
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll

Show First 20 Lines • Show All 85 Lines • ▼ Show 20 Lines
declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>) declare {<vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.experimental.vector.deinterleave2.nxv32i8(<vscale x 32 x i8>)
declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>) declare {<vscale x 8 x i16>, <vscale x 8 x i16>} @llvm.experimental.vector.deinterleave2.nxv16i16(<vscale x 16 x i16>)
declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>) declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.experimental.vector.deinterleave2.nxv8i32(<vscale x 8 x i32>)
declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>) declare {<vscale x 2 x i64>, <vscale x 2 x i64>} @llvm.experimental.vector.deinterleave2.nxv4i64(<vscale x 4 x i64>)
define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) { define {<vscale x 64 x i1>, <vscale x 64 x i1>} @vector_deinterleave_nxv64i1_nxv128i1(<vscale x 128 x i1> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1: ; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv1r.v v28, v8 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x02, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 2 * vlenb
; CHECK-NEXT: vmv1r.v v9, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv.v.i v8, 0 ; CHECK-NEXT: vmv.v.i v24, 0
; CHECK-NEXT: vmerge.vim v16, v8, 1, v0 ; CHECK-NEXT: vmv1r.v v0, v8
; CHECK-NEXT: vmerge.vim v16, v24, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 0 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmv1r.v v0, v28 ; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vmerge.vim v24, v24, 1, v0
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v28, v8, 0 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: vmsne.vi v0, v8, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vs1r.v v0, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v24, v16, 8 ; CHECK-NEXT: vnsrl.wi v4, v16, 8
; CHECK-NEXT: vnsrl.wi v28, v8, 8 ; CHECK-NEXT: vnsrl.wi v0, v24, 8
; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma
; CHECK-NEXT: vmsne.vi v8, v24, 0 ; CHECK-NEXT: vmsne.vi v8, v0, 0
; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl1r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec) %retval = call {<vscale x 64 x i1>, <vscale x 64 x i1>} @llvm.experimental.vector.deinterleave2.nxv128i1(<vscale x 128 x i1> %vec)
ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval ret {<vscale x 64 x i1>, <vscale x 64 x i1>} %retval
} }
define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) { define {<vscale x 64 x i8>, <vscale x 64 x i8>} @vector_deinterleave_nxv64i8_nxv128i8(<vscale x 128 x i8> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8: ; CHECK-LABEL: vector_deinterleave_nxv64i8_nxv128i8:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v12, v16, 0 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 8 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 8 ; CHECK-NEXT: vnsrl.wi v4, v16, 8
; CHECK-NEXT: vnsrl.wi v0, v24, 8
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec) %retval = call {<vscale x 64 x i8>, <vscale x 64 x i8>} @llvm.experimental.vector.deinterleave2.nxv128i8(<vscale x 128 x i8> %vec)
ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval ret {<vscale x 64 x i8>, <vscale x 64 x i8>} %retval
} }
define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) { define {<vscale x 32 x i16>, <vscale x 32 x i16>} @vector_deinterleave_nxv32i16_nxv64i16(<vscale x 64 x i16> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16: ; CHECK-LABEL: vector_deinterleave_nxv32i16_nxv64i16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v12, v16, 0 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 16 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vnsrl.wi v4, v16, 16
; CHECK-NEXT: vnsrl.wi v0, v24, 16
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec) %retval = call {<vscale x 32 x i16>, <vscale x 32 x i16>} @llvm.experimental.vector.deinterleave2.nxv64i16(<vscale x 64 x i16> %vec)
ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval ret {<vscale x 32 x i16>, <vscale x 32 x i16>} %retval
} }
define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) { define {<vscale x 16 x i32>, <vscale x 16 x i32>} @vector_deinterleave_nxv16i32_nxvv32i32(<vscale x 32 x i32> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32: ; CHECK-LABEL: vector_deinterleave_nxv16i32_nxvv32i32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wx v20, v24, a0 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
; CHECK-NEXT: vnsrl.wx v16, v8, a0 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vnsrl.wi v4, v24, 0 ; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: vmv8r.v v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec) %retval = call {<vscale x 16 x i32>, <vscale x 16 x i32>} @llvm.experimental.vector.deinterleave2.nxv32i32(<vscale x 32 x i32> %vec)
ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval ret {<vscale x 16 x i32>, <vscale x 16 x i32>} %retval
} }
define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) { define {<vscale x 8 x i64>, <vscale x 8 x i64>} @vector_deinterleave_nxv8i64_nxv16i64(<vscale x 16 x i64> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64: ; CHECK-LABEL: vector_deinterleave_nxv8i64_nxv16i64:
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; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vrgather.vv v16, v24, v0 ; CHECK-NEXT: vrgather.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: vmv4r.v v24, v16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v12, v16 ; CHECK-NEXT: vmv4r.v v12, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v28, v16 ; CHECK-NEXT: vmv4r.v v20, v24
; CHECK-NEXT: vmv8r.v v16, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec) %retval = call {<vscale x 8 x i64>, <vscale x 8 x i64>} @llvm.experimental.vector.deinterleave2.nxv16i64(<vscale x 16 x i64> %vec)
ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval ret {<vscale x 8 x i64>, <vscale x 8 x i64>} %retval
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declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>) declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.experimental.vector.deinterleave2.nxv8f32(<vscale x 8 x float>)
declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>) declare {<vscale x 2 x double>, <vscale x 2 x double>} @llvm.experimental.vector.deinterleave2.nxv4f64(<vscale x 4 x double>)
define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) { define {<vscale x 32 x half>, <vscale x 32 x half>} @vector_deinterleave_nxv32f16_nxv64f16(<vscale x 64 x half> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16: ; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v8 ; CHECK-NEXT: vmv8r.v v24, v8
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v12, v16, 0 ; CHECK-NEXT: vnsrl.wi v12, v16, 0
; CHECK-NEXT: vnsrl.wi v0, v24, 16 ; CHECK-NEXT: vnsrl.wi v8, v24, 0
; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vnsrl.wi v4, v16, 16
; CHECK-NEXT: vnsrl.wi v0, v24, 16
; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: vmv8r.v v16, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec) %retval = call {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half> %vec)
ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval ret {<vscale x 32 x half>, <vscale x 32 x half>} %retval
} }
define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) { define {<vscale x 16 x float>, <vscale x 16 x float>} @vector_deinterleave_nxv16f32_nxv32f32(<vscale x 32 x float> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32: ; CHECK-LABEL: vector_deinterleave_nxv16f32_nxv32f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vmv8r.v v24, v16 ; CHECK-NEXT: vmv8r.v v24, v16
; CHECK-NEXT: li a0, 32 ; CHECK-NEXT: li a0, 32
; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma
; CHECK-NEXT: vnsrl.wx v20, v24, a0 ; CHECK-NEXT: vnsrl.wx v20, v24, a0
; CHECK-NEXT: vnsrl.wx v16, v8, a0 ; CHECK-NEXT: vnsrl.wx v16, v8, a0
; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vnsrl.wi v4, v24, 0 ; CHECK-NEXT: vnsrl.wi v4, v24, 0
; CHECK-NEXT: vnsrl.wi v0, v8, 0
; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: vmv8r.v v8, v0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec) %retval = call {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float> %vec)
ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval ret {<vscale x 16 x float>, <vscale x 16 x float>} %retval
} }
define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) { define {<vscale x 8 x double>, <vscale x 8 x double>} @vector_deinterleave_nxv8f64_nxv16f64(<vscale x 16 x double> %vec) {
; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64: ; CHECK-LABEL: vector_deinterleave_nxv8f64_nxv16f64:
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; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3 ; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v0, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vrgather.vv v16, v24, v0 ; CHECK-NEXT: vrgather.vv v16, v24, v0
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: vmv4r.v v24, v16
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vs8r.v v16, (a0) # Unknown-size Folded Spill
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 5 ; CHECK-NEXT: slli a0, a0, 5
; CHECK-NEXT: add a0, sp, a0 ; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16 ; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v12, v16 ; CHECK-NEXT: vmv4r.v v12, v16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 4
; CHECK-NEXT: add a0, sp, a0
; CHECK-NEXT: addi a0, a0, 16
; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: addi a0, sp, 16 ; CHECK-NEXT: addi a0, sp, 16
; CHECK-NEXT: vl8r.v v24, (a0) # Unknown-size Folded Reload ; CHECK-NEXT: vl8r.v v16, (a0) # Unknown-size Folded Reload
; CHECK-NEXT: vmv4r.v v28, v16 ; CHECK-NEXT: vmv4r.v v20, v24
; CHECK-NEXT: vmv8r.v v16, v24
; CHECK-NEXT: csrr a0, vlenb ; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: li a1, 40 ; CHECK-NEXT: li a1, 40
; CHECK-NEXT: mul a0, a0, a1 ; CHECK-NEXT: mul a0, a0, a1
; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec) %retval = call {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double> %vec)
ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval ret {<vscale x 8 x double>, <vscale x 8 x double>} %retval
} }
declare {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half>) declare {<vscale x 32 x half>, <vscale x 32 x half>} @llvm.experimental.vector.deinterleave2.nxv64f16(<vscale x 64 x half>)
declare {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float>) declare {<vscale x 16 x float>, <vscale x 16 x float>} @llvm.experimental.vector.deinterleave2.nxv32f32(<vscale x 32 x float>)
declare {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double>) declare {<vscale x 8 x double>, <vscale x 8 x double>} @llvm.experimental.vector.deinterleave2.nxv16f64(<vscale x 16 x double>)

llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Lines bb.0:
liveins: $x16, $x17 liveins: $x16, $x17
; 73 = e16,m2 ; 73 = e16,m2
; CHECK-LABEL: name: copy_subregister ; CHECK-LABEL: name: copy_subregister
; CHECK: liveins: $x16, $x17 ; CHECK: liveins: $x16, $x17
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: $x15 = PseudoVSETIVLI 4, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x15 = PseudoVSETIVLI 4, 73 /* e16, m2, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 $v26m2, $v8m2, $noreg, 4 /* e16 */, implicit $vl, implicit $vtype ; CHECK-NEXT: early-clobber $v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg, 4 /* e16 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2 ; CHECK-NEXT: $v12m2 = VMV2R_V $v28m2
$x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype $x15 = PseudoVSETIVLI 4, 73, implicit-def $vl, implicit-def $vtype
$v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4, 0, implicit $vl, implicit $vtype $v26m2 = PseudoVLE16_V_M2 undef $v26m2, killed $x16, $noreg, 4, 0, implicit $vl, implicit $vtype
$v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4, 0, implicit $vl, implicit $vtype $v8m2 = PseudoVLE16_V_M2 undef $v8m2, killed $x17, $noreg, 4, 0, implicit $vl, implicit $vtype
$v28m4 = PseudoVWADD_VV_M2 $v26m2, $v8m2, $noreg, 4, implicit $vl, implicit $vtype
$v28m4 = PseudoVWADD_VV_M2 undef $v28m4, $v26m2, $v8m2, $noreg, 4, 0, implicit $vl, implicit $vtype
$v12m2 = COPY $v28m2 $v12m2 = COPY $v28m2
... ...
--- ---
name: copy_with_different_vlmax name: copy_with_different_vlmax
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $x14, $x16 liveins: $x14, $x16
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llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

Show First 20 Lines • Show All 200 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2 ; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: bb.2.if.else:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt3:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 %pt3, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
; CHECK-NEXT: $v8 = COPY [[PHI]] ; CHECK-NEXT: $v8 = COPY [[PHI]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $x11, $v8, $x12 liveins: $x10, $x11, $v8, $x12
%7:gprnox0 = COPY $x12 %7:gprnox0 = COPY $x12
%6:vr = COPY $v8 %6:vr = COPY $v8
%5:gpr = COPY $x11 %5:gpr = COPY $x11
%4:gpr = COPY $x10 %4:gpr = COPY $x10
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%0:vr = PseudoVLE64_V_M1 %pt, %5, %7, 6, 0 %0:vr = PseudoVLE64_V_M1 %pt, %5, %7, 6, 0
%8:gpr = COPY $x0 %8:gpr = COPY $x0
BEQ %4, %8, %bb.2 BEQ %4, %8, %bb.2
PseudoBR %bb.1 PseudoBR %bb.1
bb.1.if.then: bb.1.if.then:
%1:vr = PseudoVADD_VV_M1 %0, %6, %7, 6 %pt2:vr = IMPLICIT_DEF
%1:vr = PseudoVADD_VV_M1 %pt2, %0, %6, %7, 6, 0
PseudoBR %bb.3 PseudoBR %bb.3
bb.2.if.else: bb.2.if.else:
%2:vr = PseudoVSUB_VV_M1 %0, %6, %7, 6 %pt3:vr = IMPLICIT_DEF
%2:vr = PseudoVSUB_VV_M1 %pt3, %0, %6, %7, 6, 0
bb.3.if.end: bb.3.if.end:
%3:vr = PHI %1, %bb.1, %2, %bb.2 %3:vr = PHI %1, %bb.1, %2, %bb.2
$v8 = COPY %3 $v8 = COPY %3
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
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; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2 ; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: bb.2.if.else:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 %pt2, [[COPY1]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: [[PseudoVMV_X_S_M1_:%[0-9]+]]:gpr = PseudoVMV_X_S_M1 [[PHI]], 6 /* e64 */, implicit $vtype
; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]] ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S_M1_]]
; CHECK-NEXT: PseudoRET implicit $x10 ; CHECK-NEXT: PseudoRET implicit $x10
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $v8, $v9, $x11 liveins: $x10, $v8, $v9, $x11
%6:gprnox0 = COPY $x11 %6:gprnox0 = COPY $x11
%5:vr = COPY $v9 %5:vr = COPY $v9
%4:vr = COPY $v8 %4:vr = COPY $v8
%3:gpr = COPY $x10 %3:gpr = COPY $x10
%7:gpr = COPY $x0 %7:gpr = COPY $x0
BEQ %3, %7, %bb.2 BEQ %3, %7, %bb.2
PseudoBR %bb.1 PseudoBR %bb.1
bb.1.if.then: bb.1.if.then:
%0:vr = PseudoVADD_VV_M1 %4, %5, %6, 6 %pt:vr = IMPLICIT_DEF
%0:vr = PseudoVADD_VV_M1 %pt, %4, %5, %6, 6, 0
PseudoBR %bb.3 PseudoBR %bb.3
bb.2.if.else: bb.2.if.else:
%1:vr = PseudoVSUB_VV_M1 %5, %5, %6, 6 %pt2:vr = IMPLICIT_DEF
%1:vr = PseudoVSUB_VV_M1 %pt2, %5, %5, %6, 6, 0
bb.3.if.end: bb.3.if.end:
%2:vr = PHI %0, %bb.1, %1, %bb.2 %2:vr = PHI %0, %bb.1, %1, %bb.2
%8:gpr = PseudoVMV_X_S_M1 %2, 6 %8:gpr = PseudoVMV_X_S_M1 %2, 6
$x10 = COPY %8 $x10 = COPY %8
PseudoRET implicit $x10 PseudoRET implicit $x10
... ...
Show All 32 Linesbody: |
; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2 ; CHECK-NEXT: BEQ [[COPY3]], [[COPY4]], %bb.2
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.if.then: ; CHECK-NEXT: bb.1.if.then:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoBR %bb.3 ; CHECK-NEXT: PseudoBR %bb.3
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.else: ; CHECK-NEXT: bb.2.if.else:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVSUB_VV_M1_:%[0-9]+]]:vr = PseudoVSUB_VV_M1 %pt2, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3.if.end: ; CHECK-NEXT: bb.3.if.end:
; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vr = PHI [[PseudoVADD_VV_M1_]], %bb.1, [[PseudoVSUB_VV_M1_]], %bb.2
; CHECK-NEXT: $v8 = COPY [[PHI]] ; CHECK-NEXT: $v8 = COPY [[PHI]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
bb.0.entry: bb.0.entry:
successors: %bb.2(0x30000000), %bb.1(0x50000000) successors: %bb.2(0x30000000), %bb.1(0x50000000)
liveins: $x10, $v8, $v9, $x11 liveins: $x10, $v8, $v9, $x11
%7:gprnox0 = COPY $x11 %7:gprnox0 = COPY $x11
%6:vr = COPY $v9 %6:vr = COPY $v9
%5:vr = COPY $v8 %5:vr = COPY $v8
%4:gpr = COPY $x10 %4:gpr = COPY $x10
%0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype %0:gprnox0 = PseudoVSETVLI %7, 88, implicit-def dead $vl, implicit-def dead $vtype
%8:gpr = COPY $x0 %8:gpr = COPY $x0
BEQ %4, %8, %bb.2 BEQ %4, %8, %bb.2
PseudoBR %bb.1 PseudoBR %bb.1
bb.1.if.then: bb.1.if.then:
%1:vr = PseudoVADD_VV_M1 %5, %6, %0, 6 %pt:vr = IMPLICIT_DEF
%1:vr = PseudoVADD_VV_M1 %pt, %5, %6, %0, 6, 0
PseudoBR %bb.3 PseudoBR %bb.3
bb.2.if.else: bb.2.if.else:
%2:vr = PseudoVSUB_VV_M1 %5, %6, %0, 6 %pt2:vr = IMPLICIT_DEF
%2:vr = PseudoVSUB_VV_M1 %pt2, %5, %6, %0, 6, 0
bb.3.if.end: bb.3.if.end:
%3:vr = PHI %1, %bb.1, %2, %bb.2 %3:vr = PHI %1, %bb.1, %2, %bb.2
$v8 = COPY %3 $v8 = COPY %3
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
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; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU [[COPY1]], 0 ; CHECK-NEXT: [[LWU:%[0-9]+]]:gpr = LWU [[COPY1]], 0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[DEF]], %bb.1, [[LWU]], %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[DEF]], %bb.1, [[LWU]], %bb.2
; CHECK-NEXT: %pt3:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 215 /* e32, mf2, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 [[PseudoVLE32_V_MF2_MASK]], [[PHI]], -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 %pt3, [[PseudoVLE32_V_MF2_MASK]], [[PHI]], -1, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]] ; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]]
; CHECK-NEXT: PseudoRET implicit $v0 ; CHECK-NEXT: PseudoRET implicit $v0
bb.0: bb.0:
successors: %bb.1(0x80000000) successors: %bb.1(0x80000000)
liveins: $x10, $x11 liveins: $x10, $x11
%0:gpr = COPY $x11 %0:gpr = COPY $x11
%1:gpr = COPY $x10 %1:gpr = COPY $x10
Show All 16 Linesbody: |
bb.2: bb.2:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
%9:gpr = LWU %1, 0 %9:gpr = LWU %1, 0
bb.3: bb.3:
%10:gpr = PHI %2, %bb.1, %9, %bb.2 %10:gpr = PHI %2, %bb.1, %9, %bb.2
%11:vr = nsw PseudoVADD_VX_MF2 %6, %10, -1, 5 %pt3:vr = IMPLICIT_DEF
%11:vr = nsw PseudoVADD_VX_MF2 %pt3, %6, %10, -1, 5, 0
$v0 = COPY %11 $v0 = COPY %11
PseudoRET implicit $v0 PseudoRET implicit $v0
... ...
--- ---
name: vsetvli_loop_store name: vsetvli_loop_store
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: gpr, preferred-register: '' } - { id: 0, class: gpr, preferred-register: '' }
Show All 21 Linesbody: |
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.1
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 %pt2, [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1 ; CHECK-NEXT: BLTU [[ADDI]], [[COPY1]], %bb.1
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
bb.0: bb.0:
liveins: $x10, $x11 liveins: $x10, $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%1:gpr = PseudoReadVLENB %1:gpr = PseudoReadVLENB
%2:gpr = SRLI %1:gpr, 3 %2:gpr = SRLI %1:gpr, 3
%3:gpr = COPY $x11 %3:gpr = COPY $x11
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%4:vr = PseudoVID_V_M1 %pt, -1, 6, 0 %4:vr = PseudoVID_V_M1 %pt, -1, 6, 0
%5:gpr = COPY $x0 %5:gpr = COPY $x0
bb.1: bb.1:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
%6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.1 %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.1
%7:vr = PseudoVADD_VX_M1 %4:vr, %6:gpr, -1, 6 %pt2:vr = IMPLICIT_DEF
%7:vr = PseudoVADD_VX_M1 %pt2, %4:vr, %6:gpr, -1, 6, 0
%8:gpr = MUL %6:gpr, %2:gpr %8:gpr = MUL %6:gpr, %2:gpr
%9:gpr = ADD %0:gpr, %8:gpr %9:gpr = ADD %0:gpr, %8:gpr
PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5 PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5
%10:gpr = ADDI %6:gpr, 1 %10:gpr = ADDI %6:gpr, 1
BLTU %10:gpr, %3:gpr, %bb.1 BLTU %10:gpr, %3:gpr, %bb.1
PseudoBR %bb.2 PseudoBR %bb.2
bb.2: bb.2:
Show All 29 Linesbody: |
; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead [[PseudoVSETVLIX0_:%[0-9]+]]:gpr = PseudoVSETVLIX0 $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVID_V_M1_:%[0-9]+]]:vr = PseudoVID_V_M1 %pt, -1, 6 /* e64 */, 3 /* ta, ma */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x80000000) ; CHECK-NEXT: successors: %bb.2(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY2]], %bb.0, %10, %bb.2
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 %pt2, [[PseudoVID_V_M1_]], [[PHI]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]] ; CHECK-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[PHI]], [[SRLI]]
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[MUL]]
; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE32_V_MF2 killed [[PseudoVADD_VX_M1_]], killed [[ADD]], -1, 5 /* e32 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[PHI]], 1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
Show All 11 Lines bb.0:
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%4:vr = PseudoVID_V_M1 %pt, -1, 6, 3 %4:vr = PseudoVID_V_M1 %pt, -1, 6, 3
%5:gpr = COPY $x0 %5:gpr = COPY $x0
bb.1: bb.1:
successors: %bb.3 successors: %bb.3
%6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.3 %6:gpr = PHI %5:gpr, %bb.0, %10:gpr, %bb.3
%7:vr = PseudoVADD_VX_M1 %4:vr, %6:gpr, -1, 6 %pt2:vr = IMPLICIT_DEF
%7:vr = PseudoVADD_VX_M1 %pt2, %4:vr, %6:gpr, -1, 6, 0
%8:gpr = MUL %6:gpr, %2:gpr %8:gpr = MUL %6:gpr, %2:gpr
%9:gpr = ADD %0:gpr, %8:gpr %9:gpr = ADD %0:gpr, %8:gpr
PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5 PseudoVSE32_V_MF2 killed %7:vr, killed %9:gpr, -1, 5
%10:gpr = ADDI %6:gpr, 1 %10:gpr = ADDI %6:gpr, 1
bb.3: bb.3:
successors: %bb.1, %bb.2 successors: %bb.1, %bb.2
BLTU %10:gpr, %3:gpr, %bb.1 BLTU %10:gpr, %3:gpr, %bb.1
▲ Show 20 Lines • Show All 58 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: bb.1.vector.body: ; CHECK-NEXT: bb.1.vector.body:
; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY1]], %bb.0, %5, %bb.1
; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gpr = PHI [[ADDIW]], %bb.0, %4, %bb.1
; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vr = PHI [[COPY3]], %bb.0, %16, %bb.1
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, [[PHI]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4) ; CHECK-NEXT: [[PseudoVLE32_V_M1_:%[0-9]+]]:vr = PseudoVLE32_V_M1 %pt, [[PHI]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.lsr.iv12, align 4)
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5 /* e32 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, killed [[PseudoVLE32_V_M1_]], [[PHI2]], 4, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = nsw ADDI [[PHI1]], -4
; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI [[PHI]], 16
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1 ; CHECK-NEXT: BNE [[ADDI]], [[COPY4]], %bb.1
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.middle.block: ; CHECK-NEXT: bb.2.middle.block:
; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY $x0
Show All 19 Linesbody: |
bb.1.vector.body: bb.1.vector.body:
successors: %bb.2(0x04000000), %bb.1(0x7c000000) successors: %bb.2(0x04000000), %bb.1(0x7c000000)
%0:gpr = PHI %6, %bb.0, %5, %bb.1 %0:gpr = PHI %6, %bb.0, %5, %bb.1
%1:gpr = PHI %9, %bb.0, %4, %bb.1 %1:gpr = PHI %9, %bb.0, %4, %bb.1
%2:vr = PHI %10, %bb.0, %16, %bb.1 %2:vr = PHI %10, %bb.0, %16, %bb.1
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%14:vr = PseudoVLE32_V_M1 %pt, %0, 4, 5, 0 :: (load (s128) from %ir.lsr.iv12, align 4) %14:vr = PseudoVLE32_V_M1 %pt, %0, 4, 5, 0 :: (load (s128) from %ir.lsr.iv12, align 4)
%16:vr = PseudoVADD_VV_M1 killed %14, %2, 4, 5 %pt2:vr = IMPLICIT_DEF
%16:vr = PseudoVADD_VV_M1 %pt2, killed %14, %2, 4, 5, 0
%4:gpr = nsw ADDI %1, -4 %4:gpr = nsw ADDI %1, -4
%5:gpr = ADDI %0, 16 %5:gpr = ADDI %0, 16
%18:gpr = COPY $x0 %18:gpr = COPY $x0
BNE %4, %18, %bb.1 BNE %4, %18, %bb.1
PseudoBR %bb.2 PseudoBR %bb.2
bb.2.middle.block: bb.2.middle.block:
%19:gpr = COPY $x0 %19:gpr = COPY $x0
▲ Show 20 Lines • Show All 110 Lines • ▼ Show 20 Linesbody: |
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: PseudoBR %bb.1 ; CHECK-NEXT: PseudoBR %bb.1
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1: ; CHECK-NEXT: bb.1:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %12, %bb.3 ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.0, %12, %bb.3
; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[PHI]] ; CHECK-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY2]], [[PHI]]
; CHECK-NEXT: %pta:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 [[PseudoVID_V_M1_]], killed [[ADD]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VX_M1_:%[0-9]+]]:vr = PseudoVADD_VX_M1 %pta, [[PseudoVID_V_M1_]], killed [[ADD]], -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVMSLTU_VX_M1_:%[0-9]+]]:vr = PseudoVMSLTU_VX_M1 [[PseudoVADD_VX_M1_]], [[COPY1]], -1, 6 /* e64 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVCPOP_M_B1_:%[0-9]+]]:gpr = PseudoVCPOP_M_B1 [[PseudoVMSLTU_VX_M1_]], -1, 0 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY $x0
; CHECK-NEXT: BEQ killed [[PseudoVCPOP_M_B1_]], [[COPY4]], %bb.3 ; CHECK-NEXT: BEQ killed [[PseudoVCPOP_M_B1_]], [[COPY4]], %bb.3
; CHECK-NEXT: PseudoBR %bb.2 ; CHECK-NEXT: PseudoBR %bb.2
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2: ; CHECK-NEXT: bb.2:
; CHECK-NEXT: successors: %bb.3(0x80000000) ; CHECK-NEXT: successors: %bb.3(0x80000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[PHI]] ; CHECK-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD %src, [[PHI]]
; CHECK-NEXT: %pt2:vrnov0 = IMPLICIT_DEF ; CHECK-NEXT: %pt2:vrnov0 = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 %pt2, killed [[ADD1]], -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE8_V_MF8_:%[0-9]+]]:vrnov0 = PseudoVLE8_V_MF8 %pt2, killed [[ADD1]], -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: %ptb:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VI_MF8_:%[0-9]+]]:vrnov0 = PseudoVADD_VI_MF8 %ptb, [[PseudoVLE8_V_MF8_]], 4, -1, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[PHI]] ; CHECK-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD %dst, [[PHI]]
; CHECK-NEXT: PseudoVSE8_V_MF8 killed [[PseudoVADD_VI_MF8_]], killed [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype ; CHECK-NEXT: PseudoVSE8_V_MF8 killed [[PseudoVADD_VI_MF8_]], killed [[ADD2]], -1, 3 /* e8 */, implicit $vl, implicit $vtype
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3: ; CHECK-NEXT: bb.3:
; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000) ; CHECK-NEXT: successors: %bb.1(0x7c000000), %bb.4(0x04000000)
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PHI]], %inc ; CHECK-NEXT: [[ADD3:%[0-9]+]]:gpr = ADD [[PHI]], %inc
; CHECK-NEXT: BLTU [[ADD3]], %tc, %bb.1 ; CHECK-NEXT: BLTU [[ADD3]], %tc, %bb.1
Show All 18 Lines bb.0:
%59:gpr = COPY $x0 %59:gpr = COPY $x0
PseudoBR %bb.1 PseudoBR %bb.1
bb.1: bb.1:
successors: %bb.2(0x40000000), %bb.3(0x40000000) successors: %bb.2(0x40000000), %bb.3(0x40000000)
%26:gpr = PHI %59, %bb.0, %28, %bb.3 %26:gpr = PHI %59, %bb.0, %28, %bb.3
%61:gpr = ADD %12, %26 %61:gpr = ADD %12, %26
%27:vr = PseudoVADD_VX_M1 %10, killed %61, -1, 6 %pta:vr = IMPLICIT_DEF
%27:vr = PseudoVADD_VX_M1 %pta, %10, killed %61, -1, 6, 0
%62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6 %62:vr = PseudoVMSLTU_VX_M1 %27, %11, -1, 6
%63:gpr = PseudoVCPOP_M_B1 %62, -1, 0 %63:gpr = PseudoVCPOP_M_B1 %62, -1, 0
%64:gpr = COPY $x0 %64:gpr = COPY $x0
BEQ killed %63, %64, %bb.3 BEQ killed %63, %64, %bb.3
PseudoBR %bb.2 PseudoBR %bb.2
bb.2: bb.2:
successors: %bb.3(0x80000000) successors: %bb.3(0x80000000)
%66:gpr = ADD %src, %26 %66:gpr = ADD %src, %26
%pt2:vrnov0 = IMPLICIT_DEF %pt2:vrnov0 = IMPLICIT_DEF
%67:vrnov0 = PseudoVLE8_V_MF8 %pt2, killed %66, -1, 3, 0 %67:vrnov0 = PseudoVLE8_V_MF8 %pt2, killed %66, -1, 3, 0
%76:vrnov0 = PseudoVADD_VI_MF8 %67, 4, -1, 3 %ptb:vr = IMPLICIT_DEF
%76:vrnov0 = PseudoVADD_VI_MF8 %ptb, %67, 4, -1, 3, 0
%77:gpr = ADD %dst, %26 %77:gpr = ADD %dst, %26
PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3 PseudoVSE8_V_MF8 killed %76, killed %77, -1, 3
bb.3: bb.3:
successors: %bb.1(0x7c000000), %bb.4(0x04000000) successors: %bb.1(0x7c000000), %bb.4(0x04000000)
%28:gpr = ADD %26, %inc %28:gpr = ADD %26, %inc
BLTU %28, %tc, %bb.1 BLTU %28, %tc, %bb.1
PseudoBR %bb.4 PseudoBR %bb.4
bb.4: bb.4:
PseudoRET PseudoRET
... ...

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir

Show First 20 Lines • Show All 115 Lines • ▼ Show 20 Lines bb.0.entry:
liveins: $v8, $v9, $x10 liveins: $v8, $v9, $x10
; CHECK-LABEL: name: add ; CHECK-LABEL: name: add
; CHECK: liveins: $v8, $v9, $x10 ; CHECK: liveins: $v8, $v9, $x10
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%2:gprnox0 = COPY $x10 %2:gprnox0 = COPY $x10
%1:vr = COPY $v9 %1:vr = COPY $v9
%0:vr = COPY $v8 %0:vr = COPY $v8
%3:vr = PseudoVADD_VV_M1 %0, %1, %2, 6 %pt:vr = IMPLICIT_DEF
%3:vr = PseudoVADD_VV_M1 %pt, %0, %1, %2, 6, 0
$v8 = COPY %3 $v8 = COPY %3
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
name: load_add name: load_add
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
Show All 18 Lines bb.0.entry:
; CHECK: liveins: $x10, $v8, $x11 ; CHECK: liveins: $x10, $v8, $x11
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%2:gprnox0 = COPY $x11 %2:gprnox0 = COPY $x11
%1:vr = COPY $v8 %1:vr = COPY $v8
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%3:vr = PseudoVLE64_V_M1 %pt, %0, %2, 6, 0 %3:vr = PseudoVLE64_V_M1 %pt, %0, %2, 6, 0
%4:vr = PseudoVADD_VV_M1 killed %3, %1, %2, 6 %pt2:vr = IMPLICIT_DEF
%4:vr = PseudoVADD_VV_M1 %pt2, killed %3, %1, %2, 6, 0
$v8 = COPY %4 $v8 = COPY %4
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
name: load_zext name: load_zext
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
▲ Show 20 Lines • Show All 89 Lines • ▼ Show 20 Lines bb.0 (%ir-block.0):
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x)
; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt2, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y) ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt2, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y)
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE64_V_M1_]], killed [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt3:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt3, killed [[PseudoVLE64_V_M1_]], killed [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: PseudoVSE64_V_M1 killed [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) ; CHECK-NEXT: PseudoVSE64_V_M1 killed [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x)
; CHECK-NEXT: PseudoRET ; CHECK-NEXT: PseudoRET
%1:gpr = COPY $x11 %1:gpr = COPY $x11
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%pt2:vr = IMPLICIT_DEF %pt2:vr = IMPLICIT_DEF
%2:vr = PseudoVLE64_V_M1 %pt, %0, 2, 6, 0 :: (load (s128) from %ir.x) %2:vr = PseudoVLE64_V_M1 %pt, %0, 2, 6, 0 :: (load (s128) from %ir.x)
%3:vr = PseudoVLE64_V_M1 %pt2, %1, 2, 6, 0 :: (load (s128) from %ir.y) %3:vr = PseudoVLE64_V_M1 %pt2, %1, 2, 6, 0 :: (load (s128) from %ir.y)
%4:vr = PseudoVADD_VV_M1 killed %2, killed %3, 2, 6 %pt3:vr = IMPLICIT_DEF
%4:vr = PseudoVADD_VV_M1 %pt3, killed %2, killed %3, 2, 6, 0
PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store (s128) into %ir.x) PseudoVSE64_V_M1 killed %4, %0, 2, 6 :: (store (s128) into %ir.x)
PseudoRET PseudoRET
... ...
--- ---
name: vreduce_add_v2i64 name: vreduce_add_v2i64
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines bb.0.entry:
; CHECK-LABEL: name: vsetvli_add ; CHECK-LABEL: name: vsetvli_add
; CHECK: liveins: $v8, $v9, $x10 ; CHECK: liveins: $v8, $v9, $x10
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x10
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v9
; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $x0 = PseudoVSETVLI [[COPY]], 88 /* e64, m1, ta, mu */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt, [[COPY2]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%2:gprnox0 = COPY $x10 %2:gprnox0 = COPY $x10
%1:vr = COPY $v9 %1:vr = COPY $v9
%0:vr = COPY $v8 %0:vr = COPY $v8
%3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype %3:gprnox0 = PseudoVSETVLI %2, 88, implicit-def dead $vl, implicit-def dead $vtype
%4:vr = PseudoVADD_VV_M1 %0, %1, killed %3, 6 %pt:vr = IMPLICIT_DEF
%4:vr = PseudoVADD_VV_M1 %pt, %0, %1, killed %3, 6, 0
$v8 = COPY %4 $v8 = COPY %4
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
name: load_add_inlineasm name: load_add_inlineasm
alignment: 4 alignment: 4
tracksRegLiveness: true tracksRegLiveness: true
Show All 19 Lines bb.0.entry:
; CHECK-NEXT: {{ $}} ; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gprnox0 = COPY $x11
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vr = COPY $v8
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x10
; CHECK-NEXT: %pt:vr = IMPLICIT_DEF ; CHECK-NEXT: %pt:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */ ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF
; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype
; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype
; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]]
; CHECK-NEXT: PseudoRET implicit $v8 ; CHECK-NEXT: PseudoRET implicit $v8
%2:gprnox0 = COPY $x11 %2:gprnox0 = COPY $x11
%1:vr = COPY $v8 %1:vr = COPY $v8
%0:gpr = COPY $x10 %0:gpr = COPY $x10
%pt:vr = IMPLICIT_DEF %pt:vr = IMPLICIT_DEF
%3:vr = PseudoVLE64_V_M1 %pt, %0, %2, 6, 0 %3:vr = PseudoVLE64_V_M1 %pt, %0, %2, 6, 0
INLINEASM &"", 1 /* sideeffect attdialect */ INLINEASM &"", 1 /* sideeffect attdialect */
%4:vr = PseudoVADD_VV_M1 killed %3, %1, %2, 6 %pt2:vr = IMPLICIT_DEF
%4:vr = PseudoVADD_VV_M1 %pt2, killed %3, %1, %2, 6, 0
$v8 = COPY %4 $v8 = COPY %4
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...
--- ---
name: vmv_v_i_different_lmuls name: vmv_v_i_different_lmuls
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
Show All 17 Lines

llvm/test/CodeGen/RISCV/rvv/vxrm.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
craig.topperUnsubmitted
Not Done
ReplyInline Actions

Is this test no longer generated by the script?

craig.topper: Is this test no longer generated by the script?
reamesAuthorUnsubmitted
Done
ReplyInline Actions

From what I could tell, it wasn't before. It just had the header. Or at least, auto-update didn't appear to work in any meaningful way.

reames: From what I could tell, it wasn't before. It just had the header. Or at least, auto-update…
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR # RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -stop-after prologepilog -o - %s | FileCheck %s --check-prefix=MIR
# RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM # RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=ASM
--- ---
name: verify_vxrm name: verify_vxrm
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0.entry: bb.0.entry:
liveins: $v8, $v9, $x10 liveins: $v8, $v9, $x10
; MIR-LABEL: name: verify_vxrm ; MIR-LABEL: name: verify_vxrm
; MIR: liveins: $v8, $v9, $x10 ; MIR: liveins: $v8, $v9, $x10
; MIR-NEXT: {{ $}} ; MIR-NEXT: {{ $}}
; MIR-NEXT: dead $x0 = PseudoVSETVLI renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype ; MIR-NEXT: dead $x0 = PseudoVSETVLI renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm
; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 renamable $v8, renamable $v9, 0, $noreg, 3 /* e8 */, implicit $vl, implicit $vtype, implicit $vxrm ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef $v8, renamable $v8, renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $vxrm
; MIR-NEXT: PseudoRET implicit $v8 ; MIR-NEXT: PseudoRET implicit $v8
; ASM-LABEL: verify_vxrm: ; ASM-LABEL: verify_vxrm:
; ASM: # %bb.0: ; ASM: # %bb.0:
; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
; ASM-NEXT: csrwi vxrm, 0 ; ASM-NEXT: csrwi vxrm, 0
; ASM-NEXT: vaadd.vv v8, v8, v9 ; ASM-NEXT: vaadd.vv v8, v8, v9
; ASM-NEXT: ret ; ASM-NEXT: ret
%0:vr = COPY $v8 %0:vr = COPY $v8
%1:vr = COPY $v9 %1:vr = COPY $v9
dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype
renamable $v8 = PseudoVAADD_VV_MF8 killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */ %pt:vr = IMPLICIT_DEF
renamable $v8 = PseudoVAADD_VV_MF8 %pt, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0
PseudoRET implicit $v8 PseudoRET implicit $v8
... ...

llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll

Show First 20 Lines • Show All 716 Lines • ▼ Show 20 Lines
; RV32MV-NEXT: lw s2, 32(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s3, 28(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32MV-NEXT: lw s4, 24(sp) # 4-byte Folded Reload ; RV32MV-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32MV-NEXT: addi sp, sp, 48 ; RV32MV-NEXT: addi sp, sp, 48
; RV32MV-NEXT: ret ; RV32MV-NEXT: ret
; ;
; RV64MV-LABEL: test_srem_vec: ; RV64MV-LABEL: test_srem_vec:
; RV64MV: # %bb.0: ; RV64MV: # %bb.0:
; RV64MV-NEXT: ld a1, 0(a0) ; RV64MV-NEXT: lbu a1, 12(a0)
; RV64MV-NEXT: lwu a2, 8(a0) ; RV64MV-NEXT: lwu a2, 8(a0)
; RV64MV-NEXT: srli a3, a1, 2 ; RV64MV-NEXT: slli a1, a1, 32
; RV64MV-NEXT: lbu a4, 12(a0) ; RV64MV-NEXT: ld a3, 0(a0)
; RV64MV-NEXT: slli a5, a2, 62 ; RV64MV-NEXT: or a1, a2, a1
; RV64MV-NEXT: or a3, a5, a3 ; RV64MV-NEXT: slli a1, a1, 29
; RV64MV-NEXT: srai a3, a3, 31 ; RV64MV-NEXT: srai a1, a1, 31
; RV64MV-NEXT: slli a4, a4, 32 ; RV64MV-NEXT: srli a4, a3, 2
; RV64MV-NEXT: slli a2, a2, 62
; RV64MV-NEXT: or a2, a2, a4 ; RV64MV-NEXT: or a2, a2, a4
; RV64MV-NEXT: slli a2, a2, 29
; RV64MV-NEXT: lui a4, %hi(.LCPI3_0) ; RV64MV-NEXT: lui a4, %hi(.LCPI3_0)
; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4) ; RV64MV-NEXT: ld a4, %lo(.LCPI3_0)(a4)
; RV64MV-NEXT: srai a2, a2, 31 ; RV64MV-NEXT: srai a2, a2, 31
; RV64MV-NEXT: slli a1, a1, 31 ; RV64MV-NEXT: slli a3, a3, 31
; RV64MV-NEXT: srai a1, a1, 31 ; RV64MV-NEXT: srai a3, a3, 31
; RV64MV-NEXT: mulh a4, a2, a4 ; RV64MV-NEXT: mulh a4, a2, a4
; RV64MV-NEXT: srli a5, a4, 63 ; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: srai a4, a4, 1 ; RV64MV-NEXT: srai a4, a4, 1
; RV64MV-NEXT: add a4, a4, a5 ; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: lui a5, %hi(.LCPI3_1) ; RV64MV-NEXT: lui a5, %hi(.LCPI3_1)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5) ; RV64MV-NEXT: ld a5, %lo(.LCPI3_1)(a5)
; RV64MV-NEXT: add a2, a2, a4 ; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: slli a4, a4, 2
; RV64MV-NEXT: add a2, a2, a4
; RV64MV-NEXT: mulh a4, a3, a5
; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: srai a4, a4, 1
; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: lui a5, %hi(.LCPI3_2)
; RV64MV-NEXT: ld a5, %lo(.LCPI3_2)(a5)
; RV64MV-NEXT: add a3, a3, a4
; RV64MV-NEXT: slli a4, a4, 3 ; RV64MV-NEXT: slli a4, a4, 3
; RV64MV-NEXT: sub a3, a3, a4 ; RV64MV-NEXT: sub a2, a2, a4
; RV64MV-NEXT: mulh a4, a1, a5 ; RV64MV-NEXT: mulh a4, a3, a5
; RV64MV-NEXT: srli a5, a4, 63 ; RV64MV-NEXT: srli a5, a4, 63
; RV64MV-NEXT: add a4, a4, a5 ; RV64MV-NEXT: add a4, a4, a5
; RV64MV-NEXT: li a5, 6 ; RV64MV-NEXT: li a5, 6
; RV64MV-NEXT: mul a4, a4, a5 ; RV64MV-NEXT: mul a4, a4, a5
; RV64MV-NEXT: sub a1, a1, a4 ; RV64MV-NEXT: sub a3, a3, a4
; RV64MV-NEXT: lui a4, %hi(.LCPI3_2)
; RV64MV-NEXT: ld a4, %lo(.LCPI3_2)(a4)
; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma ; RV64MV-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64MV-NEXT: vslide1down.vx v8, v8, a1
; RV64MV-NEXT: vslide1down.vx v8, v8, a3 ; RV64MV-NEXT: vslide1down.vx v8, v8, a3
; RV64MV-NEXT: vslide1down.vx v8, v8, a2 ; RV64MV-NEXT: vslide1down.vx v8, v8, a2
; RV64MV-NEXT: mulh a2, a1, a4
; RV64MV-NEXT: srli a3, a2, 63
; RV64MV-NEXT: srai a2, a2, 1
; RV64MV-NEXT: add a2, a2, a3
; RV64MV-NEXT: slli a3, a2, 2
; RV64MV-NEXT: add a1, a1, a2
; RV64MV-NEXT: add a1, a1, a3
; RV64MV-NEXT: vslide1down.vx v8, v8, a1
; RV64MV-NEXT: vslidedown.vi v8, v8, 1 ; RV64MV-NEXT: vslidedown.vi v8, v8, 1
; RV64MV-NEXT: lui a1, %hi(.LCPI3_3) ; RV64MV-NEXT: lui a1, %hi(.LCPI3_3)
; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3) ; RV64MV-NEXT: addi a1, a1, %lo(.LCPI3_3)
; RV64MV-NEXT: vle64.v v10, (a1) ; RV64MV-NEXT: vle64.v v10, (a1)
; RV64MV-NEXT: li a1, -1 ; RV64MV-NEXT: li a1, -1
; RV64MV-NEXT: srli a1, a1, 31 ; RV64MV-NEXT: srli a1, a1, 31
; RV64MV-NEXT: vand.vx v8, v8, a1 ; RV64MV-NEXT: vand.vx v8, v8, a1
; RV64MV-NEXT: vmsne.vv v0, v8, v10 ; RV64MV-NEXT: vmsne.vv v0, v8, v10
Show All 28 Lines