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Differential D154142

[llvm-mca][RISCV] Add RISCV-SEW instrument
ClosedPublic

Authored by michaelmaitland on Jun 29 2023, 12:59 PM.

Details

Reviewers
myhsu
craig.topper
reames
andreadb
Commits
rG3d7d463f73ba: [llvm-mca][RISCV] Add RISCV-SEW instrument
Summary

Now that RISCV pseudo instructions now account for SEW in some cases,
it useful that RISCV SEW instruments exist so that llvm-mca can use
the SEW specific scheduler classes.

Diff Detail

Event Timeline

michaelmaitland created this revision.Jun 29 2023, 12:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2023, 12:59 PM
Herald added subscribers: jobnoorman, luke, VincentWu and 29 others. · View Herald Transcript
michaelmaitland requested review of this revision.Jun 29 2023, 12:59 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 29 2023, 12:59 PM
Herald added subscribers: llvm-commits, wangpc, eopXD, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B242215: Diff 535965.Jun 29 2023, 1:00 PM
michaelmaitland updated this revision to Diff 535972.Jun 29 2023, 1:09 PM

Fix error case tests

Harbormaster completed remote builds in B242219: Diff 535972.Jun 29 2023, 1:09 PM
michaelmaitland added a parent revision: D154136: [RISCV] Add SEW to RISCVInversePseudoTable.Jun 29 2023, 1:14 PM
myhsu added inline comments.Jun 29 2023, 9:26 PM
llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h
46

maybe adding explicit?

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
7

is there any specific reason to test with the same LMUL here?

andreadb added a comment.Jun 30 2023, 3:14 AM

I've only left a minor comment. Otherwise, patch looks good to me.

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp
201

I don't expect different instruments to have the same DESC_NAME. This should probably be an "else if".

michaelmaitland updated this revision to Diff 536219.Jun 30 2023, 6:52 AM
michaelmaitland marked 2 inline comments as done.
  • Add explicit
  • change if -> else if
llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
7

We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use the same LMUL to show that the MCA reports changed based on SEW changing.

The reason we need to provide an LMUL to test SEW is because vdiv.vv depends on both LMUL and SEW. We could not resolve the correct SchedClassID without both. I thought about having a LMUL-SEW instrument instead of a SEW instrument, but it becomes trickier to replace an active LMUL instrument with the LMUL from the LMUL-SEW instrument. It was simpler to just use two instruments. I am open to improving this in the future.

Harbormaster completed remote builds in B242402: Diff 536219.Jun 30 2023, 6:52 AM
michaelmaitland updated this revision to Diff 536222.Jun 30 2023, 6:56 AM

Last update reverted some tests by accident. This update un-reverts them.

Harbormaster completed remote builds in B242403: Diff 536222.Jun 30 2023, 6:57 AM
andreadb accepted this revision.Jun 30 2023, 7:16 AM

LGTM

This revision is now accepted and ready to land.Jun 30 2023, 7:16 AM
michaelmaitland updated this revision to Diff 536271.Jun 30 2023, 8:35 AM

Represent SEW as bits<3> as per change in D154136

Harbormaster completed remote builds in B242440: Diff 536271.Jun 30 2023, 9:58 AM
myhsu added inline comments.Jun 30 2023, 1:44 PM
llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
7

the same LMUL to show that the MCA reports changed based on SEW changing.

Ahh that makes sense, thanks

We could not resolve the correct SchedClassID without both.

Does the current implementation effectively falls back to a default LMUL? If that's the case I think it's good enough as a baseline. That said, having a LMUL-SEW instrument would definitely be a nice addition.

michaelmaitland added inline comments.Jun 30 2023, 1:47 PM
llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
7

It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided, but I’ll add a test that gives coverage of lmul but no sew for an instruction that needs sew + lmul.

michaelmaitland updated this revision to Diff 536416.Jun 30 2023, 1:59 PM

Add test case to verify when an instruction needs LMUL+SEW but only SEW provided that it falls back to WorstCase behavior

michaelmaitland marked an inline comment as done.Jun 30 2023, 2:00 PM
michaelmaitland added inline comments.
llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
7

I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

Harbormaster completed remote builds in B242548: Diff 536416.Jun 30 2023, 2:39 PM
michaelmaitland updated this revision to Diff 537914.Jul 6 2023, 3:44 PM

Add create instruments from vsetvli using SEW.

Harbormaster completed remote builds in B243606: Diff 537914.Jul 6 2023, 3:45 PM
michaelmaitland planned changes to this revision.Jul 6 2023, 4:04 PM
michaelmaitland added inline comments.
llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s
31

It looks like we're defaulting to worst case when SEW is provided, but the sched resource does not depend on SEW. This is occurring in many of the test cases. I need to fix.

michaelmaitland updated this revision to Diff 537919.Jul 6 2023, 4:07 PM

Handle when SEW instrument exists, but Sched class depends only on LMUL.

This revision is now accepted and ready to land.Jul 6 2023, 4:07 PM
Harbormaster completed remote builds in B243611: Diff 537919.Jul 6 2023, 4:08 PM
craig.topper added a comment.Jul 14 2023, 9:50 AM

LGTM

craig.topper accepted this revision.Jul 14 2023, 9:50 AM
This revision was landed with ongoing or failed builds.Jul 14 2023, 12:12 PM
Closed by commit rG3d7d463f73ba: [llvm-mca][RISCV] Add RISCV-SEW instrument (authored by michaelmaitland). · Explain Why
This revision was automatically updated to reflect the committed changes.
michaelmaitland added a commit: rG3d7d463f73ba: [llvm-mca][RISCV] Add RISCV-SEW instrument.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
MCA/
14 lines
143 lines
test/
tools/
llvm-mca/
RISCV/
different-lmul-instruments.s
different-instruments.s
26 lines
different-sew-instruments.s
vsetvli-lmul-instrument.s
46 lines
lmul-instrument-at-start.s
instrument-at-start.s
8 lines
lmul-instrument-in-middle.s
instrument-in-middle.s
8 lines
lmul-instrument-in-region.s
instrument-in-region.s
8 lines
lmul-instrument-straddles-region.s
instrument-straddles-region.s
8 lines
multiple-same-lmul-instruments.s
multiple-same-instruments.s
50 lines
91 lines
needs-sew-but-only-lmul.s
instrument-in-region.s
38 lines
8 lines
riscv-lmul-instrument-no-data-is-err.s
riscv-instrument-no-data-is-err.s
10 lines
riscv-sew-instrument-no-data-is-err.s
riscv-instrument-no-data-is-err.s
8 lines
sew-instrument-at-start.s
instrument-at-start.s
25 lines
sew-instrument-in-middle.s
no-vsetvli-to-start.s
48 lines
sew-instrument-in-region.s
instrument-in-region.s
33 lines
sew-instrument-straddles-region.s
instrument-in-region.s
34 lines
6 lines
unknown-sew-is-err.s
unknown-lmul-is-err.s
8 lines
26 lines
vsetivli-lmul-sew-instrument.s
vsetivli-lmul-instrument.s
43 lines
26 lines
vsetvli-lmul-sew-instrument.s
vsetvli-lmul-instrument.s
43 lines

Diff 537914

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h

Show All 25 Lines
namespace llvm { namespace llvm {
namespace mca { namespace mca {
class RISCVLMULInstrument : public Instrument { class RISCVLMULInstrument : public Instrument {
public: public:
static const StringRef DESC_NAME; static const StringRef DESC_NAME;
static bool isDataValid(StringRef Data); static bool isDataValid(StringRef Data);
RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {} explicit RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
~RISCVLMULInstrument() = default; ~RISCVLMULInstrument() = default;
uint8_t getLMUL() const; uint8_t getLMUL() const;
}; };
class RISCVSEWInstrument : public Instrument {
public:
static const StringRef DESC_NAME;
static bool isDataValid(StringRef Data);
explicit RISCVSEWInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
myhsuUnsubmitted
Done
ReplyInline Actions

maybe adding explicit?

myhsu: maybe adding `explicit`?
~RISCVSEWInstrument() = default;
uint8_t getSEW() const;
};
class RISCVInstrumentManager : public InstrumentManager { class RISCVInstrumentManager : public InstrumentManager {
public: public:
RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII) RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
: InstrumentManager(STI, MCII) {} : InstrumentManager(STI, MCII) {}
bool shouldIgnoreInstruments() const override { return false; } bool shouldIgnoreInstruments() const override { return false; }
bool supportsInstrumentType(StringRef Type) const override; bool supportsInstrumentType(StringRef Type) const override;
Show All 16 Lines

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

Show First 20 Lines • Show All 63 Lines • ▼ Show 20 Lines return StringSwitch<uint8_t>(getData())
.Case("M2", 0b001) .Case("M2", 0b001)
.Case("M4", 0b010) .Case("M4", 0b010)
.Case("M8", 0b011) .Case("M8", 0b011)
.Case("MF2", 0b101) .Case("MF2", 0b101)
.Case("MF4", 0b110) .Case("MF4", 0b110)
.Case("MF8", 0b111); .Case("MF8", 0b111);
} }
const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW";
bool RISCVSEWInstrument::isDataValid(llvm::StringRef Data) {
// Return true if not one of the valid SEW strings
return StringSwitch<bool>(Data)
.Cases("E8", "E16", "E32", "E64", true)
.Default(false);
}
uint8_t RISCVSEWInstrument::getSEW() const {
// assertion prevents us from needing llvm_unreachable in the StringSwitch
// below
assert(isDataValid(getData()) && "Cannot get SEW because invalid Data value");
// These are the LMUL values that are used in RISC-V tablegen
return StringSwitch<uint8_t>(getData())
.Case("E8", 0b001)
.Case("E16", 0b010)
.Case("E32", 0b011)
.Case("E64", 0b100);
}
bool RISCVInstrumentManager::supportsInstrumentType( bool RISCVInstrumentManager::supportsInstrumentType(
llvm::StringRef Type) const { llvm::StringRef Type) const {
// Currently, only support for RISCVLMULInstrument type return Type == RISCVLMULInstrument::DESC_NAME ||
return Type == RISCVLMULInstrument::DESC_NAME; Type == RISCVSEWInstrument::DESC_NAME;
} }
UniqueInstrument UniqueInstrument
RISCVInstrumentManager::createInstrument(llvm::StringRef Desc, RISCVInstrumentManager::createInstrument(llvm::StringRef Desc,
llvm::StringRef Data) { llvm::StringRef Data) {
if (Desc != RISCVLMULInstrument::DESC_NAME) { if (Desc == RISCVLMULInstrument::DESC_NAME) {
LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc
<< '\n');
return nullptr;
}
if (!RISCVLMULInstrument::isDataValid(Data)) { if (!RISCVLMULInstrument::isDataValid(Data)) {
LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": " LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
<< Data << '\n'); << Data << '\n');
return nullptr; return nullptr;
} }
return std::make_unique<RISCVLMULInstrument>(Data); return std::make_unique<RISCVLMULInstrument>(Data);
} }
if (Desc == RISCVSEWInstrument::DESC_NAME) {
if (!RISCVSEWInstrument::isDataValid(Data)) {
LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
<< Data << '\n');
return nullptr;
}
return std::make_unique<RISCVSEWInstrument>(Data);
}
LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc << '\n');
return nullptr;
}
SmallVector<UniqueInstrument> SmallVector<UniqueInstrument>
RISCVInstrumentManager::createInstruments(const MCInst &Inst) { RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
if (Inst.getOpcode() == RISCV::VSETVLI || if (Inst.getOpcode() == RISCV::VSETVLI ||
Inst.getOpcode() == RISCV::VSETIVLI) { Inst.getOpcode() == RISCV::VSETIVLI) {
LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: " LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: "
<< Inst << "\n"); << Inst << "\n");
unsigned VTypeI = Inst.getOperand(2).getImm(); unsigned VTypeI = Inst.getOperand(2).getImm();
RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI); RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
Show All 22 Lines case RISCVII::LMUL_F8:
LMUL = "MF8"; LMUL = "MF8";
break; break;
case RISCVII::LMUL_RESERVED: case RISCVII::LMUL_RESERVED:
llvm_unreachable("Cannot create instrument for LMUL_RESERVED"); llvm_unreachable("Cannot create instrument for LMUL_RESERVED");
} }
SmallVector<UniqueInstrument> Instruments; SmallVector<UniqueInstrument> Instruments;
Instruments.emplace_back( Instruments.emplace_back(
createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL)); createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL));
unsigned SEW = RISCVVType::getSEW(VTypeI);
StringRef SEWStr;
switch (SEW) {
case 8:
SEWStr = "E8";
break;
case 16:
SEWStr = "E16";
break;
case 32:
SEWStr = "E32";
break;
case 64:
SEWStr = "E64";
break;
default:
llvm_unreachable("Cannot create instrument for SEW");
}
Instruments.emplace_back(
createInstrument(RISCVSEWInstrument::DESC_NAME, SEWStr));
return Instruments; return Instruments;
} }
return SmallVector<UniqueInstrument>(); return SmallVector<UniqueInstrument>();
} }
unsigned RISCVInstrumentManager::getSchedClassID( unsigned RISCVInstrumentManager::getSchedClassID(
const MCInstrInfo &MCII, const MCInst &MCI, const MCInstrInfo &MCII, const MCInst &MCI,
const llvm::SmallVector<Instrument *> &IVec) const { const llvm::SmallVector<Instrument *> &IVec) const {
unsigned short Opcode = MCI.getOpcode(); unsigned short Opcode = MCI.getOpcode();
unsigned SchedClassID = MCII.get(Opcode).getSchedClass(); unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
for (const auto &I : IVec) { // Unpack all possible RISCV instruments from IVec.
// Unknown Instrument kind RISCVLMULInstrument *LI = nullptr;
if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) { RISCVSEWInstrument *SI = nullptr;
uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL(); for (auto &I : IVec) {
if (I->getDesc() == RISCVLMULInstrument::DESC_NAME)
LI = static_cast<RISCVLMULInstrument *>(I);
else if (I->getDesc() == RISCVSEWInstrument::DESC_NAME)
andreadbUnsubmitted
Done
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I don't expect different instruments to have the same DESC_NAME. This should probably be an "else if".

andreadb: I don't expect different instruments to have the same DESC_NAME. This should probably be an…
SI = static_cast<RISCVSEWInstrument *>(I);
}
// Need LMUL or LMUL, SEW in order to override opcode. If no LMUL is provided,
// then no option to override.
if (!LI) {
LLVM_DEBUG(
dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
return SchedClassID;
}
uint8_t LMUL = LI->getLMUL();
// getBaseInfo works with (Opcode, LMUL, 0) if no SEW instrument,
// or (Opcode, LMUL, SEW) if SEW instrument is active.
uint8_t SEW = SI ? SI->getSEW() : 0;
const RISCVVInversePseudosTable::PseudoInfo *RVV = const RISCVVInversePseudosTable::PseudoInfo *RVV =
RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0); RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
// Not a RVV instr // Not a RVV instr
if (!RVV) { if (!RVV) {
LLVM_DEBUG( LLVM_DEBUG(
dbgs() dbgs() << "RVCB: Could not find PseudoInstruction for Opcode "
<< "RVCB: Could not find PseudoInstruction for Opcode " << MCII.getName(Opcode)
<< MCII.getName(Opcode) << ", LMUL=" << I->getData() << ", LMUL=" << (LI ? LI->getData() : "Unspecified")
<< ", SEW=" << (SI ? SI->getData() : "Unspecified")
<< ". Ignoring instrumentation and using original SchedClassID=" << ". Ignoring instrumentation and using original SchedClassID="
<< SchedClassID << '\n'); << SchedClassID << '\n');
return SchedClassID; return SchedClassID;
} }
// Override using pseudo // Override using pseudo
LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode " LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
<< MCII.getName(Opcode) << ", LMUL=" << I->getData() << MCII.getName(Opcode) << ", LMUL=" << LI->getData()
<< ", SEW=" << (SI ? SI->getData() : "Unspecified")
<< ". Overriding original SchedClassID=" << SchedClassID << ". Overriding original SchedClassID=" << SchedClassID
<< " with " << MCII.getName(RVV->Pseudo) << '\n'); << " with " << MCII.getName(RVV->Pseudo) << '\n');
return MCII.get(RVV->Pseudo).getSchedClass(); return MCII.get(RVV->Pseudo).getSchedClass();
} }
}
// Unknown Instrument kind
LLVM_DEBUG(
dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
return SchedClassID;
}
} // namespace mca } // namespace mca
} // namespace llvm } // namespace llvm
using namespace llvm; using namespace llvm;
using namespace mca; using namespace mca;
static InstrumentManager * static InstrumentManager *
Show All 12 Lines

llvm/test/tools/llvm-mca/RISCV/different-instruments.s

  • This file was moved to llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s.

llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/different-instruments.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu vsetvli zero, a0, e8, m8, tu, mu
# LLVM-MCA-RISCV-LMUL M8 # LLVM-MCA-RISCV-LMUL M8
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
myhsuUnsubmitted
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is there any specific reason to test with the same LMUL here?

myhsu: is there any specific reason to test with the same LMUL here?
michaelmaitlandAuthorUnsubmitted
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We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use the same LMUL to show that the MCA reports changed based on SEW changing.

The reason we need to provide an LMUL to test SEW is because vdiv.vv depends on both LMUL and SEW. We could not resolve the correct SchedClassID without both. I thought about having a LMUL-SEW instrument instead of a SEW instrument, but it becomes trickier to replace an active LMUL instrument with the LMUL from the LMUL-SEW instrument. It was simpler to just use two instruments. I am open to improving this in the future.

michaelmaitland: We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use…
myhsuUnsubmitted
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the same LMUL to show that the MCA reports changed based on SEW changing.

Ahh that makes sense, thanks

We could not resolve the correct SchedClassID without both.

Does the current implementation effectively falls back to a default LMUL? If that's the case I think it's good enough as a baseline. That said, having a LMUL-SEW instrument would definitely be a nice addition.

myhsu: > the same LMUL to show that the MCA reports changed based on SEW changing. Ahh that makes…
michaelmaitlandAuthorUnsubmitted
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It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided, but I’ll add a test that gives coverage of lmul but no sew for an instruction that needs sew + lmul.

michaelmaitland: It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided…
michaelmaitlandAuthorUnsubmitted
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I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

michaelmaitland: I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 24
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.17
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.17
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 32.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
michaelmaitlandAuthorUnsubmitted
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It looks like we're defaulting to worst case when SEW is provided, but the sched resource does not depend on SEW. This is occurring in many of the test cases. I need to fix.

michaelmaitland: It looks like we're defaulting to worst case when SEW is provided, but the sched resource does…
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 32.00 32.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789 0123
# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: [0,2] . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,3] . . . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
vadd.vv v12, v12, v12 # LLVM-MCA-RISCV-LMUL M1
vsetvli zero, a0, e8, m8, tu, mu # LLVM-MCA-RISCV-SEW E8
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
myhsuUnsubmitted
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is there any specific reason to test with the same LMUL here?

myhsu: is there any specific reason to test with the same LMUL here?
michaelmaitlandAuthorUnsubmitted
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We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use the same LMUL to show that the MCA reports changed based on SEW changing.

The reason we need to provide an LMUL to test SEW is because vdiv.vv depends on both LMUL and SEW. We could not resolve the correct SchedClassID without both. I thought about having a LMUL-SEW instrument instead of a SEW instrument, but it becomes trickier to replace an active LMUL instrument with the LMUL from the LMUL-SEW instrument. It was simpler to just use two instruments. I am open to improving this in the future.

michaelmaitland: We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use…
myhsuUnsubmitted
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the same LMUL to show that the MCA reports changed based on SEW changing.

Ahh that makes sense, thanks

We could not resolve the correct SchedClassID without both.

Does the current implementation effectively falls back to a default LMUL? If that's the case I think it's good enough as a baseline. That said, having a LMUL-SEW instrument would definitely be a nice addition.

myhsu: > the same LMUL to show that the MCA reports changed based on SEW changing. Ahh that makes…
michaelmaitlandAuthorUnsubmitted
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It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided, but I’ll add a test that gives coverage of lmul but no sew for an instruction that needs sew + lmul.

michaelmaitland: It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided…
michaelmaitlandAuthorUnsubmitted
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I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

michaelmaitland: I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
vsetvli zero, a0, e64, m1, tu, mu
# LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 358
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 354.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 354.00 354.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: Index 0123
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s

  • This file was deleted after being copied to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s, llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s.
The contents of this file were not changed.

llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s

  • This file was moved to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s.

llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s

  • This file was deleted after being copied to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s, llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s, llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s, llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s.
The contents of this file were not changed.

llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s

  • This file was moved to llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s.

llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 16.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 16.00 16.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
Show All 9 Lines

llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/instrument-in-middle.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, mf8, tu, mu vsetvli zero, a0, e8, mf8, tu, mu
# LLVM-MCA-RISCV-LMUL MF8 # LLVM-MCA-RISCV-LMUL MF8
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21 # CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total uOps: 3 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14 # CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 17.0 # CHECK-NEXT: Block RThroughput: 32.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 17.00 17.00 - - # CHECK-NEXT: - - 1.00 - 32.00 32.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, mf8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0 # CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 # CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, mf8, tu, mu # CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
Show All 12 Lines

llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s.
Show All 11 Lines
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 16.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 16.00 16.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
Show All 9 Lines

llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/instrument-straddles-region.s.
Show All 12 Lines
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 8
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 16.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 16.00 16.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 01234567
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
Show All 9 Lines

llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s

  • This file was moved to llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s.

llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/multiple-same-instruments.s.
Show All 9 Lines
vsub.vv v12, v12, v12 vsub.vv v12, v12, v12
vsetvli zero, a0, e8, m4, tu, mu vsetvli zero, a0, e8, m4, tu, mu
# LLVM-MCA-RISCV-LMUL M4 # LLVM-MCA-RISCV-LMUL M4
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsub.vv v12, v12, v12 vsub.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8 # CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 28 # CHECK-NEXT: Total Cycles: 72
# CHECK-NEXT: Total uOps: 8 # CHECK-NEXT: Total uOps: 8
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.29 # CHECK-NEXT: uOps Per Cycle: 0.11
# CHECK-NEXT: IPC: 0.29 # CHECK-NEXT: IPC: 0.11
# CHECK-NEXT: Block RThroughput: 22.0 # CHECK-NEXT: Block RThroughput: 80.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vsub.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 22.00 22.00 - - # CHECK-NEXT: - - 3.00 - 80.00 80.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vsub.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789 0123456789 0123456789 01
# CHECK-NEXT: Index 0123456789 01234567 # CHECK-NEXT: Index 0123456789 0123456789 0123456789 0123456789
# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . . . . . . . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE . . . . . . . . . . . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: [0,2] . DeeE . . . . . . . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,3] . . . . DeeeE . . . . . . . . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12 # CHECK-NEXT: [0,4] . . . . . . . DeeeE. . . . . . .. vsub.vv v12, v12, v12
# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu # CHECK-NEXT: [0,5] . . . . . . . .DeeE. . . . . . .. vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12 # CHECK-NEXT: [0,6] . . . . . . . . . . .DeeeE . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12 # CHECK-NEXT: [0,7] . . . . . . . . . . . . . . DeeeE vsub.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
Show All 9 Lines

llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s

  • This file was added.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e64, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1
# LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
vsetvli zero, a0, e64, m1, tu, mu
# LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
vdivu.vv v8, v8, v12
vsetvli zero, a0, e32, m1, tu, mu
# LLVM-MCA-RISCV-SEW E32
vdiv.vv v8, v8, v12
vdivu.vv v8, v8, v12
# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 570
# CHECK-NEXT: Total uOps: 8
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 566.0
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12
# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 566.00 566.00 - -
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 114.00 114.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: - - - - 112.00 112.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 112.00 112.00 - - vdivu.vv v8, v8, v12
# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
# CHECK: [0,0] DeeE vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 4. 1 0.0 0.0 0.0 vdivu.vv v8, v8, v12
# CHECK-NEXT: 5. 1 0.0 0.0 0.0 vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: 6. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 7. 1 0.0 0.0 0.0 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
# LLVM-MCA-BEGIN foo # Test LMUL but no SEW falls back to worst case.
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
# LLVM-MCA-END foo # LLVM-MCA-RISCV-SEW E8
vdiv.vv v8, v8, v12
# CHECK: [0] Code Region - foo
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 484
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 480.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 480.00 480.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 0123
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s

  • This file was copied to llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21 # CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total uOps: 3 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14 # CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 32.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 18.00 18.00 - - # CHECK-NEXT: - - 1.00 - 32.00 32.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0 # CHECK-NEXT: Index 0123456789 0
# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12 # CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
Show All 12 Lines

llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s

  • This file was deleted after being copied to llvm/test/tools/llvm-mca/RISCV/riscv-lmul-instrument-no-data-is-err.s, llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s.
The contents of this file were not changed.

llvm/test/tools/llvm-mca/RISCV/riscv-lmul-instrument-no-data-is-err.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL # LLVM-MCA-RISCV-LMUL
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: error: Failed to create RISCV-LMUL instrument with no data # CHECK: error: Failed to create RISCV-LMUL instrument with no data
# CHECK: # LLVM-MCA-RISCV-LMUL # CHECK: # LLVM-MCA-RISCV-LMUL
# CHECK: ^ # CHECK: ^
# CHECK: error: There was an error parsing comments. # CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/riscv-instrument-no-data-is-err.s.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL # LLVM-MCA-RISCV-SEW
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
# CHECK: error: Failed to create RISCV-LMUL instrument with no data # CHECK: error: Failed to create RISCV-SEW instrument with no data
# CHECK: # LLVM-MCA-RISCV-LMUL # CHECK: # LLVM-MCA-RISCV-SEW
# CHECK: ^ # CHECK: ^
# CHECK: error: There was an error parsing comments. # CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/instrument-at-start.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 # LLVM-MCA-RISCV-SEW E8
vdiv.vv v8, v8, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 244
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 240.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 240.00 240.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 0123
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vadd.vv v12, v12, v12 # llvm-mca should use `WorstCase` SEW if there is no instrument that specifies
vsetvli zero, a0, e8, m1, tu, mu # which SEW to use. On sifive-x280, `WorstCase` SEW is the smallest SEW, so
vadd.vv v12, v12, v12 # the first vadd.vv should use E8 and the second should use E64.
vdiv.vv v8, v8, v12
vsetvli zero, a0, e8, m8, tu, mu
# LLVM-MCA-RISCV-LMUL M8
# LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3 # CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21 # CHECK-NEXT: Total Cycles: 2833
# CHECK-NEXT: Total uOps: 3 # CHECK-NEXT: Total uOps: 3
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14 # CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.14 # CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 2832.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 1920 1920.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 912 912.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 18.00 18.00 - - # CHECK-NEXT: - - 1.00 - 2832.00 2832.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 1920.00 1920.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 912.00 912.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 0123456789 # CHECK-NEXT: Index 0
# CHECK-NEXT: Index 0123456789 0 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
# LLVM-MCA-BEGIN foo # LLVM-MCA-BEGIN foo
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e64, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 # LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
# LLVM-MCA-END foo # LLVM-MCA-END foo
# CHECK: [0] Code Region - foo # CHECK: [0] Code Region - foo
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 118
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 114.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 114.00 114.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 0123
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s

  • This file was moved from llvm/test/tools/llvm-mca/RISCV/instrument-in-region.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
# LLVM-MCA-BEGIN foo # LLVM-MCA-BEGIN foo
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e64, m1, tu, mu
# LLVM-MCA-RISCV-LMUL M1 # LLVM-MCA-RISCV-LMUL M1
vadd.vv v12, v12, v12 # LLVM-MCA-RISCV-SEW E64
vdiv.vv v8, v8, v12
# LLVM-MCA-END foo # LLVM-MCA-END foo
vdiv.vv v8, v8, v12
# CHECK: [0] Code Region - foo # CHECK: [0] Code Region - foo
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 2 # CHECK-NEXT: Instructions: 2
# CHECK-NEXT: Total Cycles: 8 # CHECK-NEXT: Total Cycles: 118
# CHECK-NEXT: Total uOps: 2 # CHECK-NEXT: Total uOps: 2
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25 # CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.25 # CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 2.0 # CHECK-NEXT: Block RThroughput: 114.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - - # CHECK-NEXT: - - 1.00 - 114.00 114.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: Index 01234567 # CHECK-NEXT: Index 0123
# CHECK: [0,0] DeeE . . vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s

  • This file was copied to llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-V MF9 # LLVM-MCA-RISCV-LMUL MF9
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V # CHECK: error: Failed to create RISCV-LMUL instrument with data: MF9
# CHECK: # LLVM-MCA-RISCV-V MF9 # CHECK: # LLVM-MCA-RISCV-LMUL MF9
# CHECK: ^ # CHECK: ^
# CHECK: error: There was an error parsing comments. # CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s.
# RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
# LLVM-MCA-RISCV-V MF9 # LLVM-MCA-RISCV-SEW E99
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V # CHECK: error: Failed to create RISCV-SEW instrument with data: E99
# CHECK: # LLVM-MCA-RISCV-V MF9 # CHECK: # LLVM-MCA-RISCV-SEW E99
# CHECK: ^ # CHECK: ^
# CHECK: error: There was an error parsing comments. # CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s

  • This file was copied to llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetivli zero, 8, e8, m1, tu, mu vsetivli zero, 8, e8, m1, tu, mu
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetivli zero, 8, e8, m8, tu, mu vsetivli zero, 8, e8, m8, tu, mu
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 24
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.17
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.17
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 32.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 32.00 32.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789 0123
# CHECK: [0,0] DeeE . .. vsetivli zero, 8, e8, m1, tu, mu # CHECK: [0,0] DeeE . . . . . vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE .. vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: [0,2] . DeeE . . . . vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,3] . . . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetivli zero, 8, e8, m1, tu, mu vsetivli zero, 8, e8, m1, tu, mu
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
vsetivli zero, 8, e8, m8, tu, mu vsetivli zero, 8, e32, m8, tu, mu
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 1140
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 1136.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e32, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e32, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: Index 0123
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . .. vsetivli zero, 8, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK-NEXT: [0,2] . DeeE .. vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetivli zero, 8, e32, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s

  • This file was copied to llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s, llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
vsetvli zero, a0, e8, m8, tu, mu vsetvli zero, a0, e8, m8, tu, mu
vadd.vv v12, v12, v12 vadd.vv v12, v12, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 24
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.17
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.17
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 32.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 32.00 32.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 # CHECK-NEXT: Index 0123456789 0123
# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: [0,1] . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: [0,2] . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12 # CHECK-NEXT: [0,3] . . . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>

llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s

  • This file was copied from llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s.
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
vsetvli zero, a0, e8, m1, tu, mu vsetvli zero, a0, e8, m1, tu, mu
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
vsetvli zero, a0, e8, m8, tu, mu vsetvli zero, a0, e32, m8, tu, mu
vadd.vv v12, v12, v12 vdiv.vv v8, v8, v12
# CHECK: Iterations: 1 # CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4 # CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 12 # CHECK-NEXT: Total Cycles: 1140
# CHECK-NEXT: Total uOps: 4 # CHECK-NEXT: Total uOps: 4
# CHECK: Dispatch Width: 2 # CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33 # CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.33 # CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 18.0 # CHECK-NEXT: Block RThroughput: 1136.0
# CHECK: Instruction Info: # CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps # CHECK-NEXT: [1]: #uOps
# CHECK-NEXT: [2]: Latency # CHECK-NEXT: [2]: Latency
# CHECK-NEXT: [3]: RThroughput # CHECK-NEXT: [3]: RThroughput
# CHECK-NEXT: [4]: MayLoad # CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore # CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U) # CHECK-NEXT: [6]: HasSideEffects (U)
# CHECK: [1] [2] [3] [4] [5] [6] Instructions: # CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12 # CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12
# CHECK: Resources: # CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv # CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv # CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA # CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB # CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV # CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA # CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [6] - SiFive7VL # CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS # CHECK-NEXT: [7] - SiFive7VS
# CHECK: Resource pressure per iteration: # CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - - # CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - -
# CHECK: Resource pressure by instruction: # CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions: # CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12 # CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12
# CHECK: Timeline view: # CHECK: Timeline view:
# CHECK-NEXT: 01 # CHECK-NEXT: Index 0123
# CHECK-NEXT: Index 0123456789
# CHECK: [0,0] DeeE . .. vsetvli zero, a0, e8, m1, tu, mu # CHECK: [0,0] DeeE vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE .. vadd.vv v12, v12, v12 # CHECK-NEXT: Truncated display due to cycle limit
# CHECK-NEXT: [0,2] . DeeE .. vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE vadd.vv v12, v12, v12
# CHECK: Average Wait times (based on the timeline view): # CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions # CHECK-NEXT: [0]: Executions
# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
# CHECK: [0] [1] [2] [3] # CHECK: [0] [1] [2] [3]
# CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu # CHECK-NEXT: 0. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 1. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e8, m8, tu, mu # CHECK-NEXT: 2. 1 0.0 0.0 0.0 vsetvli zero, a0, e32, m8, tu, mu
# CHECK-NEXT: 3. 1 0.0 0.0 0.0 vadd.vv v12, v12, v12 # CHECK-NEXT: 3. 1 0.0 0.0 0.0 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 0.0 0.0 0.0 <total> # CHECK-NEXT: 1 0.0 0.0 0.0 <total>
llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s