[llvm-mca][RISCV] Add RISCV-SEW instrument

[michaelmaitland]

Summary

Now that RISCV pseudo instructions now account for SEW in some cases,
it useful that RISCV SEW instruments exist so that llvm-mca can use
the SEW specific scheduler classes.

[michaelmaitland]

Fix error case tests

[myhsu]

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h

46

maybe adding explicit?

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

8

is there any specific reason to test with the same LMUL here?

[andreadb]

I've only left a minor comment. Otherwise, patch looks good to me.

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

201

I don't expect different instruments to have the same DESC_NAME. This should probably be an "else if".

[michaelmaitland]

• Add explicit
• change if -> else if

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

8

We need a LMUL instrument since the vdiv.vv instruction depends on LMUL and SEW. I chose to use the same LMUL to show that the MCA reports changed based on SEW changing.

The reason we need to provide an LMUL to test SEW is because vdiv.vv depends on both LMUL and SEW. We could not resolve the correct SchedClassID without both. I thought about having a LMUL-SEW instrument instead of a SEW instrument, but it becomes trickier to replace an active LMUL instrument with the LMUL from the LMUL-SEW instrument. It was simpler to just use two instruments. I am open to improving this in the future.

[michaelmaitland]

Last update reverted some tests by accident. This update un-reverts them.

[andreadb]

LGTM

[michaelmaitland]

Represent SEW as bits<3> as per change in D154136

[myhsu]

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

8

the same LMUL to show that the MCA reports changed based on SEW changing.

Ahh that makes sense, thanks

We could not resolve the correct SchedClassID without both.

Does the current implementation effectively falls back to a default LMUL? If that's the case I think it's good enough as a baseline. That said, having a LMUL-SEW instrument would definitely be a nice addition.

[michaelmaitland]

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

8

It falls back to the “WorstCase” behavior. We have test coverage of no lmul nor sew provided, but I’ll add a test that gives coverage of lmul but no sew for an instruction that needs sew + lmul.

[michaelmaitland]

Add test case to verify when an instruction needs LMUL+SEW but only SEW provided that it falls back to WorstCase behavior

[michaelmaitland]

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

8

I've addressed this with llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

[michaelmaitland]

Add create instruments from vsetvli using SEW.

[michaelmaitland]

llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s

31

It looks like we're defaulting to worst case when SEW is provided, but the sched resource does not depend on SEW. This is occurring in many of the test cases. I need to fix.

[michaelmaitland]

Handle when SEW instrument exists, but Sched class depends only on LMUL.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.h

 namespace llvm {
 namespace mca {
 
 class RISCVLMULInstrument : public Instrument {
 public:
   static const StringRef DESC_NAME;
   static bool isDataValid(StringRef Data);
 
-  RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
+  explicit RISCVLMULInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
 
   ~RISCVLMULInstrument() = default;
 
   uint8_t getLMUL() const;
 };
 
+class RISCVSEWInstrument : public Instrument {
+public:
+  static const StringRef DESC_NAME;
+  static bool isDataValid(StringRef Data);
+
+  explicit RISCVSEWInstrument(StringRef Data) : Instrument(DESC_NAME, Data) {}
+
+  ~RISCVSEWInstrument() = default;
+
+  uint8_t getSEW() const;
+};
+
 class RISCVInstrumentManager : public InstrumentManager {
 public:
   RISCVInstrumentManager(const MCSubtargetInfo &STI, const MCInstrInfo &MCII)
       : InstrumentManager(STI, MCII) {}
 
   bool shouldIgnoreInstruments() const override { return false; }
   bool supportsInstrumentType(StringRef Type) const override;
 

llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp

return StringSwitch<uint8_t>(getData())
       .Case("M2", 0b001)
       .Case("M4", 0b010)
       .Case("M8", 0b011)
       .Case("MF2", 0b101)
       .Case("MF4", 0b110)
       .Case("MF8", 0b111);
 }
 
+const llvm::StringRef RISCVSEWInstrument::DESC_NAME = "RISCV-SEW";
+
+bool RISCVSEWInstrument::isDataValid(llvm::StringRef Data) {
+  // Return true if not one of the valid SEW strings
+  return StringSwitch<bool>(Data)
+      .Cases("E8", "E16", "E32", "E64", true)
+      .Default(false);
+}
+
+uint8_t RISCVSEWInstrument::getSEW() const {
+  // assertion prevents us from needing llvm_unreachable in the StringSwitch
+  // below
+  assert(isDataValid(getData()) && "Cannot get SEW because invalid Data value");
+  // These are the LMUL values that are used in RISC-V tablegen
+  return StringSwitch<uint8_t>(getData())
+      .Case("E8", 8)
+      .Case("E16", 16)
+      .Case("E32", 32)
+      .Case("E64", 64);
+}
+
 bool RISCVInstrumentManager::supportsInstrumentType(
     llvm::StringRef Type) const {
-  // Currently, only support for RISCVLMULInstrument type
-  return Type == RISCVLMULInstrument::DESC_NAME;
+  return Type == RISCVLMULInstrument::DESC_NAME ||
+         Type == RISCVSEWInstrument::DESC_NAME;
 }
 
 UniqueInstrument
 RISCVInstrumentManager::createInstrument(llvm::StringRef Desc,
                                          llvm::StringRef Data) {
-  if (Desc != RISCVLMULInstrument::DESC_NAME) {
-    LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc
-                      << '\n');
-    return nullptr;
-  }
+  if (Desc == RISCVLMULInstrument::DESC_NAME) {
     if (!RISCVLMULInstrument::isDataValid(Data)) {
       LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
                         << Data << '\n');
       return nullptr;
     }
     return std::make_unique<RISCVLMULInstrument>(Data);
   }
 
+  if (Desc == RISCVSEWInstrument::DESC_NAME) {
+    if (!RISCVSEWInstrument::isDataValid(Data)) {
+      LLVM_DEBUG(dbgs() << "RVCB: Bad data for instrument kind " << Desc << ": "
+                        << Data << '\n');
+      return nullptr;
+    }
+    return std::make_unique<RISCVSEWInstrument>(Data);
+  }
+
+  LLVM_DEBUG(dbgs() << "RVCB: Unknown instrumentation Desc: " << Desc << '\n');
+  return nullptr;
+}
+
 SmallVector<UniqueInstrument>
 RISCVInstrumentManager::createInstruments(const MCInst &Inst) {
   if (Inst.getOpcode() == RISCV::VSETVLI ||
       Inst.getOpcode() == RISCV::VSETIVLI) {
     LLVM_DEBUG(dbgs() << "RVCB: Found VSETVLI and creating instrument for it: "
                       << Inst << "\n");
     unsigned VTypeI = Inst.getOperand(2).getImm();
     RISCVII::VLMUL VLMUL = RISCVVType::getVLMUL(VTypeI);
case RISCVII::LMUL_F8:
       LMUL = "MF8";
       break;
     case RISCVII::LMUL_RESERVED:
       llvm_unreachable("Cannot create instrument for LMUL_RESERVED");
     }
     SmallVector<UniqueInstrument> Instruments;
     Instruments.emplace_back(
         createInstrument(RISCVLMULInstrument::DESC_NAME, LMUL));
+
+    unsigned SEW = RISCVVType::getSEW(VTypeI);
+    StringRef SEWStr;
+    switch (SEW) {
+    case 8:
+      SEWStr = "E8";
+      break;
+    case 16:
+      SEWStr = "E16";
+      break;
+    case 32:
+      SEWStr = "E32";
+      break;
+    case 64:
+      SEWStr = "E64";
+      break;
+    default:
+      llvm_unreachable("Cannot create instrument for SEW");
+    }
+    Instruments.emplace_back(
+        createInstrument(RISCVSEWInstrument::DESC_NAME, SEWStr));
+
     return Instruments;
   }
   return SmallVector<UniqueInstrument>();
 }
 
 unsigned RISCVInstrumentManager::getSchedClassID(
     const MCInstrInfo &MCII, const MCInst &MCI,
     const llvm::SmallVector<Instrument *> &IVec) const {
   unsigned short Opcode = MCI.getOpcode();
   unsigned SchedClassID = MCII.get(Opcode).getSchedClass();
 
-  for (const auto &I : IVec) {
-    // Unknown Instrument kind
-    if (I->getDesc() == RISCVLMULInstrument::DESC_NAME) {
-      uint8_t LMUL = static_cast<RISCVLMULInstrument *>(I)->getLMUL();
-      const RISCVVInversePseudosTable::PseudoInfo *RVV =
-          RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
-      // Not a RVV instr
-      if (!RVV) {
-        LLVM_DEBUG(
-            dbgs()
-            << "RVCB: Could not find PseudoInstruction for Opcode "
-            << MCII.getName(Opcode) << ", LMUL=" << I->getData()
+  // Unpack all possible RISCV instruments from IVec.
+  RISCVLMULInstrument *LI = nullptr;
+  RISCVSEWInstrument *SI = nullptr;
+  for (auto &I : IVec) {
+    if (I->getDesc() == RISCVLMULInstrument::DESC_NAME)
+      LI = static_cast<RISCVLMULInstrument *>(I);
+    else if (I->getDesc() == RISCVSEWInstrument::DESC_NAME)
+      SI = static_cast<RISCVSEWInstrument *>(I);
+  }
+
+  // Need LMUL or LMUL, SEW in order to override opcode. If no LMUL is provided,
+  // then no option to override.
+  if (!LI) {
+    LLVM_DEBUG(
+        dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
+    return SchedClassID;
+  }
+  uint8_t LMUL = LI->getLMUL();
+
+  // getBaseInfo works with (Opcode, LMUL, 0) if no SEW instrument,
+  // or (Opcode, LMUL, SEW) if SEW instrument is active, and depends on LMUL
+  // and SEW, or (Opcode, LMUL, 0) if does not depend on SEW.
+  uint8_t SEW = SI ? SI->getSEW() : 0;
+  // Check if it depends on LMUL and SEW
+      RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, SEW);
+  // Check if it depends only on LMUL
+  if (!RVV)
+    RVV = RISCVVInversePseudosTable::getBaseInfo(Opcode, LMUL, 0);
+
+        dbgs() << "RVCB: Could not find PseudoInstruction for Opcode "
+               << MCII.getName(Opcode)
+               << ", LMUL=" << (LI ? LI->getData() : "Unspecified")
+               << ", SEW=" << (SI ? SI->getData() : "Unspecified")
                << ". Ignoring instrumentation and using original SchedClassID="
                << SchedClassID << '\n');
-        return SchedClassID;
-      }
 
-      // Override using pseudo
-      LLVM_DEBUG(dbgs() << "RVCB: Found Pseudo Instruction for Opcode "
-                        << MCII.getName(Opcode) << ", LMUL=" << I->getData()
-                        << ". Overriding original SchedClassID=" << SchedClassID
-                        << " with " << MCII.getName(RVV->Pseudo) << '\n');
-      return MCII.get(RVV->Pseudo).getSchedClass();
-    }
-  }
-
-  // Unknown Instrument kind
-  LLVM_DEBUG(
-      dbgs() << "RVCB: Did not use instrumentation to override Opcode.\n");
-  return SchedClassID;
-}
+                    << MCII.getName(Opcode) << ", LMUL=" << LI->getData()
+                    << ", SEW=" << (SI ? SI->getData() : "Unspecified")
 
 } // namespace mca
 } // namespace llvm
 
 using namespace llvm;
 using namespace mca;
 
 static InstrumentManager *

llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL M8
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      4
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      358
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.33
-# CHECK-NEXT: IPC:               0.33
-# CHECK-NEXT: Block RThroughput: 18.0
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 354.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  1      4     16.00                       vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     2.00    -     18.00  18.00   -      -
+# CHECK-NEXT:  -      -     2.00    -     354.00 354.00  -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE .    ..   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE  ..   vadd.vv  v12, v12, v12
-# CHECK-NEXT: [0,2]     .   DeeE  ..   vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,3]     .    . DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
-# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s

+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-LMUL M1
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e64, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
+vdivu.vv v8, v8, v12
+vsetvli zero, a0, e32, m1, tu, mu
+# LLVM-MCA-RISCV-SEW E32
+vdiv.vv v8, v8, v12
+vdivu.vv v8, v8, v12
+
+# CHECK:      Iterations:        1
+# CHECK-NEXT: Instructions:      8
+# CHECK-NEXT: Total Cycles:      570
+# CHECK-NEXT: Total uOps:        8
+
+# CHECK:      Dispatch Width:    2
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 566.0
+
+# CHECK:      Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      114   114.00                      vdivu.vv  v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e32, m1, tu, mu
+# CHECK-NEXT:  1      112   112.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      112   112.00                      vdivu.vv  v8, v8, v12
+
+# CHECK:      Resources:
+# CHECK-NEXT: [0]   - SiFive7FDiv
+# CHECK-NEXT: [1]   - SiFive7IDiv
+# CHECK-NEXT: [2]   - SiFive7PipeA
+# CHECK-NEXT: [3]   - SiFive7PipeB
+# CHECK-NEXT: [4]   - SiFive7PipeV
+# CHECK-NEXT: [5]   - SiFive7VA
+# CHECK-NEXT: [6]   - SiFive7VL
+# CHECK-NEXT: [7]   - SiFive7VS
+
+# CHECK:      Resource pressure per iteration:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
+# CHECK-NEXT:  -      -     3.00    -     566.00 566.00  -      -
+
+# CHECK:      Resource pressure by instruction:
+# CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdivu.vv  v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e32, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     112.00 112.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     112.00 112.00  -      -     vdivu.vv  v8, v8, v12
+
+# CHECK:      Timeline view:
+# CHECK-NEXT: Index     0123
+
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
+
+# CHECK:      Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK:            [0]    [1]    [2]    [3]
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 4.     1     0.0    0.0    0.0       vdivu.vv v8, v8, v12
+# CHECK-NEXT: 5.     1     0.0    0.0    0.0       vsetvli  zero, a0, e32, m1, tu, mu
+# CHECK-NEXT: 6.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 7.     1     0.0    0.0    0.0       vdivu.vv v8, v8, v12
+# CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
-# LLVM-MCA-BEGIN foo
+# Test LMUL but no SEW falls back to worst case.
 vsetvli zero, a0, e8, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-# LLVM-MCA-END foo
-
-# CHECK:      [0] Code Region - foo
+vdiv.vv v8, v8, v12
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
-# CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      8
-# CHECK-NEXT: Total uOps:        2
+# CHECK-NEXT: Instructions:      3
+# CHECK-NEXT: Total Cycles:      484
+# CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.25
-# CHECK-NEXT: Block RThroughput: 2.0
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 480.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+# CHECK-NEXT:  -      -     1.00    -     480.00 480.00  -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE . .   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/riscv-sew-instrument-no-data-is-err.s

 # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW
+vdiv.vv v8, v8, v12
 
-# CHECK: error: Failed to create RISCV-LMUL instrument with no data
-# CHECK: # LLVM-MCA-RISCV-LMUL
+# CHECK: error: Failed to create RISCV-SEW instrument with no data
+# CHECK: # LLVM-MCA-RISCV-SEW
 # CHECK:  ^
 # CHECK: error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW E8
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total Cycles:      244
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.25
-# CHECK-NEXT: Block RThroughput: 2.0
+# CHECK-NEXT: uOps Per Cycle:    0.01
+# CHECK-NEXT: IPC:               0.01
+# CHECK-NEXT: Block RThroughput: 240.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+# CHECK-NEXT:  -      -     1.00    -     240.00 240.00  -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE . .   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, mf8, tu, mu
-# LLVM-MCA-RISCV-LMUL MF8
-vadd.vv v12, v12, v12
+# llvm-mca should use `WorstCase` SEW if there is no instrument that specifies
+# which SEW to use. On sifive-x280, `WorstCase` SEW is the smallest SEW, so
+# the first vadd.vv should use E8 and the second should use E64.
+
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e8, m8, tu, mu
+# LLVM-MCA-RISCV-LMUL M8
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      3
-# CHECK-NEXT: Total Cycles:      21
+# CHECK-NEXT: Total Cycles:      2833
 # CHECK-NEXT: Total uOps:        3
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.14
-# CHECK-NEXT: IPC:               0.14
-# CHECK-NEXT: Block RThroughput: 17.0
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 2832.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      4     16.00                       vadd.vv v12, v12, v12
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, mf8, tu, mu
-# CHECK-NEXT:  1      4     1.00                        vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      1920   1920.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  1      912   912.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     1.00    -     17.00  17.00   -      -
+# CHECK-NEXT:  -      -     1.00    -     2832.00 2832.00  -    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
-# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv  v12, v12, v12
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, mf8, tu, mu
-# CHECK-NEXT:  -      -      -      -     1.00   1.00    -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     1920.00 1920.00  -    -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     912.00 912.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0
-
-# CHECK:      [0,0]     DeeeE.    .    .    .   vadd.vv v12, v12, v12
-# CHECK-NEXT: [0,1]     .DeeE.    .    .    .   vsetvli zero, a0, e8, mf8, tu, mu
-# CHECK-NEXT: [0,2]     .    .    .    .DeeeE   vadd.vv v12, v12, v12
+# CHECK-NEXT: Index     0
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, mf8, tu, mu
-# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m8, tu, mu
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
 # LLVM-MCA-BEGIN foo
-vsetvli zero, a0, e8, m1, tu, mu
+vsetvli zero, a0, e64, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
 # LLVM-MCA-END foo
 
 # CHECK:      [0] Code Region - foo
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total Cycles:      118
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.25
-# CHECK-NEXT: Block RThroughput: 2.0
+# CHECK-NEXT: uOps Per Cycle:    0.02
+# CHECK-NEXT: IPC:               0.02
+# CHECK-NEXT: Block RThroughput: 114.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+# CHECK-NEXT:  -      -     1.00    -     114.00 114.00  -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE . .   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
 # LLVM-MCA-BEGIN foo
-vsetvli zero, a0, e8, m1, tu, mu
+vsetvli zero, a0, e64, m1, tu, mu
 # LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW E64
+vdiv.vv v8, v8, v12
 # LLVM-MCA-END foo
+vdiv.vv v8, v8, v12
 
 # CHECK:      [0] Code Region - foo
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      2
-# CHECK-NEXT: Total Cycles:      8
+# CHECK-NEXT: Total Cycles:      118
 # CHECK-NEXT: Total uOps:        2
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.25
-# CHECK-NEXT: IPC:               0.25
-# CHECK-NEXT: Block RThroughput: 2.0
+# CHECK-NEXT: uOps Per Cycle:    0.02
+# CHECK-NEXT: IPC:               0.02
+# CHECK-NEXT: Block RThroughput: 114.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  1      114   114.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     1.00    -     2.00   2.00    -      -
+# CHECK-NEXT:  -      -     1.00    -     114.00 114.00  -      -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e64, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     114.00 114.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT: Index     01234567
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE . .   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e64, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/unknown-lmul-is-err.s

 # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-V MF9
+# LLVM-MCA-RISCV-LMUL MF9
 vadd.vv v12, v12, v12
 
-# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
-# CHECK: # LLVM-MCA-RISCV-V MF9
+# CHECK: error: Failed to create RISCV-LMUL instrument with data: MF9
+# CHECK: # LLVM-MCA-RISCV-LMUL MF9
 # CHECK:  ^
 # CHECK:  error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/unknown-sew-is-err.s

 # RUN: not llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -iterations=1 < %s 2>&1 | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-V MF9
-vadd.vv v12, v12, v12
+# LLVM-MCA-RISCV-SEW E99
+vdiv.vv v8, v8, v12
 
-# CHECK: error: Unknown instrumentation type in LLVM-MCA comment: RISCV-V
-# CHECK: # LLVM-MCA-RISCV-V MF9
+# CHECK: error: Failed to create RISCV-SEW instrument with data: E99
+# CHECK: # LLVM-MCA-RISCV-SEW E99
 # CHECK:  ^
 # CHECK:  error: There was an error parsing comments.

llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
-vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL M8
-vadd.vv v12, v12, v12
+vsetivli zero, 8, e8, m1, tu, mu
+vdiv.vv v8, v8, v12
+vsetivli zero, 8, e32, m8, tu, mu
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      4
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      1140
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.33
-# CHECK-NEXT: IPC:               0.33
-# CHECK-NEXT: Block RThroughput: 18.0
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 1136.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  1      4     16.00                       vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetivli  zero, 8, e8, m1, tu, mu
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetivli  zero, 8, e32, m8, tu, mu
+# CHECK-NEXT:  1      896   896.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     2.00    -     18.00  18.00   -      -
+# CHECK-NEXT:  -      -     2.00    -     1136.00 1136.00  -    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli  zero, 8, e8, m1, tu, mu
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetivli  zero, 8, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     896.00 896.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE .    ..   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE  ..   vadd.vv  v12, v12, v12
-# CHECK-NEXT: [0,2]     .   DeeE  ..   vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,3]     .    . DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetivli zero, 8, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
-# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
-# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetivli zero, 8, e8, m1, tu, mu
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetivli zero, 8, e32, m8, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>

llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s

 # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
 # RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-x280 -timeline -iterations=1 < %s | FileCheck %s
 
 vsetvli zero, a0, e8, m1, tu, mu
-# LLVM-MCA-RISCV-LMUL M1
-vadd.vv v12, v12, v12
-vsetvli zero, a0, e8, m8, tu, mu
-# LLVM-MCA-RISCV-LMUL M8
-vadd.vv v12, v12, v12
+vdiv.vv v8, v8, v12
+vsetvli zero, a0, e32, m8, tu, mu
+vdiv.vv v8, v8, v12
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      4
-# CHECK-NEXT: Total Cycles:      12
+# CHECK-NEXT: Total Cycles:      1140
 # CHECK-NEXT: Total uOps:        4
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.33
-# CHECK-NEXT: IPC:               0.33
-# CHECK-NEXT: Block RThroughput: 18.0
+# CHECK-NEXT: uOps Per Cycle:    0.00
+# CHECK-NEXT: IPC:               0.00
+# CHECK-NEXT: Block RThroughput: 1136.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore
 # CHECK-NEXT: [6]: HasSideEffects (U)
 
 # CHECK:      [1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 # CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  1      4     2.00                        vadd.vv v12, v12, v12
-# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  1      4     16.00                       vadd.vv v12, v12, v12
+# CHECK-NEXT:  1      240   240.00                      vdiv.vv v8, v8, v12
+# CHECK-NEXT:  1      3     1.00                  U     vsetvli zero, a0, e32, m8, tu, mu
+# CHECK-NEXT:  1      896   896.00                      vdiv.vv v8, v8, v12
 
 # CHECK:      Resources:
 # CHECK-NEXT: [0]   - SiFive7FDiv
 # CHECK-NEXT: [1]   - SiFive7IDiv
 # CHECK-NEXT: [2]   - SiFive7PipeA
 # CHECK-NEXT: [3]   - SiFive7PipeB
 # CHECK-NEXT: [4]   - SiFive7PipeV
 # CHECK-NEXT: [5]   - SiFive7VA
 # CHECK-NEXT: [6]   - SiFive7VL
 # CHECK-NEXT: [7]   - SiFive7VS
 
 # CHECK:      Resource pressure per iteration:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]
-# CHECK-NEXT:  -      -     2.00    -     18.00  18.00   -      -
+# CHECK-NEXT:  -      -     2.00    -     1136.00 1136.00  -    -
 
 # CHECK:      Resource pressure by instruction:
 # CHECK-NEXT: [0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    Instructions:
 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m1, tu, mu
-# CHECK-NEXT:  -      -      -      -     2.00   2.00    -      -     vadd.vv v12, v12, v12
-# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e8, m8, tu, mu
-# CHECK-NEXT:  -      -      -      -     16.00  16.00   -      -     vadd.vv v12, v12, v12
+# CHECK-NEXT:  -      -      -      -     240.00 240.00  -      -     vdiv.vv v8, v8, v12
+# CHECK-NEXT:  -      -     1.00    -      -      -      -      -     vsetvli zero, a0, e32, m8, tu, mu
+# CHECK-NEXT:  -      -      -      -     896.00 896.00  -      -     vdiv.vv v8, v8, v12
 
 # CHECK:      Timeline view:
-# CHECK-NEXT:                     01
-# CHECK-NEXT: Index     0123456789
+# CHECK-NEXT: Index     0123
 
-# CHECK:      [0,0]     DeeE .    ..   vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: [0,1]     .  DeeeE  ..   vadd.vv  v12, v12, v12
-# CHECK-NEXT: [0,2]     .   DeeE  ..   vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: [0,3]     .    . DeeeE   vadd.vv  v12, v12, v12
+# CHECK:      [0,0]     DeeE   vsetvli  zero, a0, e8, m1, tu, mu
+# CHECK-NEXT: Truncated display due to cycle limit
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]
 # CHECK-NEXT: 0.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m1, tu, mu
-# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
-# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e8, m8, tu, mu
-# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vadd.vv  v12, v12, v12
+# CHECK-NEXT: 1.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
+# CHECK-NEXT: 2.     1     0.0    0.0    0.0       vsetvli  zero, a0, e32, m8, tu, mu
+# CHECK-NEXT: 3.     1     0.0    0.0    0.0       vdiv.vv  v8, v8, v12
 # CHECK-NEXT:        1     0.0    0.0    0.0       <total>