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Differential D153846

[SelectionDAG] do not fold (sext i32 undef to i64) to 0
AbandonedPublic

Authored by mohammed-nurulhoque on Jun 27 2023, 2:07 AM.

Details

Reviewers
RKSimon
craig.topper
ab
nikic
Summary

When sign-extending i32 undef to i64, previously it was folded to 0. Replace with i64 undef. This eliminates instructions that set undefined ABI registers to 0

Diff Detail

Event Timeline

mohammed-nurulhoque created this revision.Jun 27 2023, 2:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 2:07 AM
Herald added subscribers: luke, frasercrmck, luismarques and 23 others. · View Herald Transcript
mohammed-nurulhoque requested review of this revision.Jun 27 2023, 2:07 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 27 2023, 2:07 AM
Herald added subscribers: llvm-commits, wangpc, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B241402: Diff 534873.Jun 27 2023, 2:07 AM
mohammed-nurulhoque added reviewers: RKSimon, craig.topper, ab.Jun 27 2023, 2:11 AM
mohammed-nurulhoque set the repository for this revision to rG LLVM Github Monorepo.
nikic requested changes to this revision.Jun 27 2023, 2:19 AM
nikic added a subscriber: nikic.

This is not legal, because the result of sext must have the top bits either all zero or all ones, which undef does not guarantee. This change will lead to miscompiles.

This revision now requires changes to proceed.Jun 27 2023, 2:19 AM
Herald added a subscriber: StephenFan. · View Herald TranscriptJun 27 2023, 2:19 AM
mohammed-nurulhoque abandoned this revision.Nov 9 2023, 1:52 AM
Herald added a subscriber: sunshaoce. · View Herald TranscriptNov 9 2023, 1:52 AM

Revision Contents

PathSize
llvm/
lib/
CodeGen/
SelectionDAG/
3 lines
test/
CodeGen/
AArch64/
10 lines
8 lines
34 lines
PowerPC/
4 lines
RISCV/
8 lines
1 line
21 lines
X86/
10 lines

Diff 534873

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,594 Lines • ▼ Show 20 Lines assert((!VT.isVector() ||
VT.getVectorElementCount() == VT.getVectorElementCount() ==
Operand.getValueType().getVectorElementCount()) && Operand.getValueType().getVectorElementCount()) &&
"Vector element count mismatch!"); "Vector element count mismatch!");
assert(Operand.getValueType().bitsLT(VT) && assert(Operand.getValueType().bitsLT(VT) &&
"Invalid sext node, dst < src!"); "Invalid sext node, dst < src!");
if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND)
return getNode(OpOpcode, DL, VT, Operand.getOperand(0)); return getNode(OpOpcode, DL, VT, Operand.getOperand(0));
if (OpOpcode == ISD::UNDEF) if (OpOpcode == ISD::UNDEF)
// sext(undef) = 0, because the top bits will all be the same. return getUNDEF(VT);
return getConstant(0, DL, VT);
break; break;
case ISD::ZERO_EXTEND: case ISD::ZERO_EXTEND:
assert(VT.isInteger() && Operand.getValueType().isInteger() && assert(VT.isInteger() && Operand.getValueType().isInteger() &&
"Invalid ZERO_EXTEND!"); "Invalid ZERO_EXTEND!");
assert(VT.isVector() == Operand.getValueType().isVector() && assert(VT.isVector() == Operand.getValueType().isVector() &&
"ZERO_EXTEND result type type should be vector iff the operand " "ZERO_EXTEND result type type should be vector iff the operand "
"type is vector!"); "type is vector!");
if (Operand.getValueType() == VT) return Operand; // noop extension if (Operand.getValueType() == VT) return Operand; // noop extension
▲ Show 20 Lines • Show All 6,981 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/abd-combine.ll

Show First 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>) %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>, <8 x i16> <i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535, i16 65535>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @abdu_i_const_onehigh() { define <8 x i16> @abdu_i_const_onehigh() {
; CHECK-LABEL: abdu_i_const_onehigh: ; CHECK-LABEL: abdu_i_const_onehigh:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32765 ; CHECK-NEXT: mov w8, #32765 // =0x7ffd
; CHECK-NEXT: dup v0.8h, w8 ; CHECK-NEXT: dup v0.8h, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) %result = call <8 x i16> @llvm.aarch64.neon.uabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @abdu_i_const_oneneg() { define <8 x i16> @abdu_i_const_oneneg() {
; CHECK-LABEL: abdu_i_const_oneneg: ; CHECK-LABEL: abdu_i_const_oneneg:
▲ Show 20 Lines • Show All 128 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0) %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)
%result = trunc <8 x i32> %abs to <8 x i16> %result = trunc <8 x i32> %abs to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @abds_undef(<8 x i16> %src1) { define <8 x i16> @abds_undef(<8 x i16> %src1) {
; CHECK-LABEL: abds_undef: ; CHECK-LABEL: abds_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sshll2 v1.4s, v0.8h, #0 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: sshll v0.4s, v0.4h, #0
; CHECK-NEXT: abs v1.4s, v1.4s
; CHECK-NEXT: abs v0.4s, v0.4s
; CHECK-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32> %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> undef to <8 x i32> %zextsrc2 = sext <8 x i16> undef to <8 x i32>
%sub = sub <8 x i32> %zextsrc1, %zextsrc2 %sub = sub <8 x i32> %zextsrc1, %zextsrc2
%abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0) %abs = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %sub, i1 0)
%result = trunc <8 x i32> %abs to <8 x i16> %result = trunc <8 x i32> %abs to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
▲ Show 20 Lines • Show All 54 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>) %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767, i16 32767>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @abds_i_const_onehigh() { define <8 x i16> @abds_i_const_onehigh() {
; CHECK-LABEL: abds_i_const_onehigh: ; CHECK-LABEL: abds_i_const_onehigh:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #32765 ; CHECK-NEXT: mov w8, #32765 // =0x7ffd
; CHECK-NEXT: dup v0.8h, w8 ; CHECK-NEXT: dup v0.8h, w8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>) %result = call <8 x i16> @llvm.aarch64.neon.sabd.v8i16(<8 x i16> <i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766, i16 32766>, <8 x i16> <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>)
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @abds_i_const_oneneg() { define <8 x i16> @abds_i_const_oneneg() {
; CHECK-LABEL: abds_i_const_oneneg: ; CHECK-LABEL: abds_i_const_oneneg:
▲ Show 20 Lines • Show All 42 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/hadd-combine.ll

Show First 20 Lines • Show All 242 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @hadds_undef(<8 x i16> %src1) { define <8 x i16> @hadds_undef(<8 x i16> %src1) {
; CHECK-LABEL: hadds_undef: ; CHECK-LABEL: hadds_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: sshll v1.4s, v0.4h, #0 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: sshll2 v2.4s, v0.8h, #0
; CHECK-NEXT: shrn v0.4h, v1.4s, #1
; CHECK-NEXT: shrn2 v0.8h, v2.4s, #1
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32> %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> undef to <8 x i32> %zextsrc2 = sext <8 x i16> undef to <8 x i32>
%add = add <8 x i32> %zextsrc2, %zextsrc1 %add = add <8 x i32> %zextsrc2, %zextsrc1
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
▲ Show 20 Lines • Show All 319 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
} }
define <8 x i16> @rhadds_undef(<8 x i16> %src1) { define <8 x i16> @rhadds_undef(<8 x i16> %src1) {
; CHECK-LABEL: rhadds_undef: ; CHECK-LABEL: rhadds_undef:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: movi v1.8h, #1 ; CHECK-NEXT: movi v0.2d, #0000000000000000
; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%zextsrc1 = sext <8 x i16> %src1 to <8 x i32> %zextsrc1 = sext <8 x i16> %src1 to <8 x i32>
%zextsrc2 = sext <8 x i16> undef to <8 x i32> %zextsrc2 = sext <8 x i16> undef to <8 x i32>
%add1 = add <8 x i32> %zextsrc2, %zextsrc1 %add1 = add <8 x i32> %zextsrc2, %zextsrc1
%add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %add = add <8 x i32> %add1, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> %resulti16 = ashr <8 x i32> %add, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
%result = trunc <8 x i32> %resulti16 to <8 x i16> %result = trunc <8 x i32> %resulti16 to <8 x i16>
ret <8 x i16> %result ret <8 x i16> %result
▲ Show 20 Lines • Show All 287 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/neon-dotreduce.ll

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; CHECK-NEXT: ld1 { v2.b }[6], [x9] ; CHECK-NEXT: ld1 { v2.b }[6], [x9]
; CHECK-NEXT: add x9, sp, #200 ; CHECK-NEXT: add x9, sp, #200
; CHECK-NEXT: mov v3.b[6], w6 ; CHECK-NEXT: mov v3.b[6], w6
; CHECK-NEXT: ld1 { v4.b }[5], [x8] ; CHECK-NEXT: ld1 { v4.b }[5], [x8]
; CHECK-NEXT: add x8, sp, #64 ; CHECK-NEXT: add x8, sp, #64
; CHECK-NEXT: sshll v1.8h, v1.8b, #0 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
; CHECK-NEXT: ld1 { v0.b }[7], [x10] ; CHECK-NEXT: ld1 { v0.b }[7], [x10]
; CHECK-NEXT: ld1 { v2.b }[7], [x9] ; CHECK-NEXT: ld1 { v2.b }[7], [x9]
; CHECK-NEXT: add x9, sp, #552 ; CHECK-NEXT: add x9, sp, #680
; CHECK-NEXT: mov v3.b[7], w7 ; CHECK-NEXT: mov v3.b[7], w7
; CHECK-NEXT: add x10, sp, #680 ; CHECK-NEXT: add x10, sp, #552
; CHECK-NEXT: ld1 { v4.b }[6], [x8] ; CHECK-NEXT: ld1 { v4.b }[6], [x8]
; CHECK-NEXT: add x8, sp, #72 ; CHECK-NEXT: add x8, sp, #72
; CHECK-NEXT: movi v6.2d, #0000000000000000 ; CHECK-NEXT: movi v6.2d, #0000000000000000
; CHECK-NEXT: sshll v5.4s, v1.4h, #0 ; CHECK-NEXT: sshll v5.4s, v1.4h, #0
; CHECK-NEXT: ldr b1, [sp, #608] ; CHECK-NEXT: ldr b1, [sp, #608]
; CHECK-NEXT: sshll v0.8h, v0.8b, #0 ; CHECK-NEXT: sshll v0.8h, v0.8b, #0
; CHECK-NEXT: ld1 { v4.b }[7], [x8] ; CHECK-NEXT: ld1 { v4.b }[7], [x8]
; CHECK-NEXT: add x8, sp, #616 ; CHECK-NEXT: add x8, sp, #616
; CHECK-NEXT: sshll v2.8h, v2.8b, #0 ; CHECK-NEXT: sshll v2.8h, v2.8b, #0
; CHECK-NEXT: sshll v7.8h, v3.8b, #0 ; CHECK-NEXT: sshll v7.8h, v3.8b, #0
; CHECK-NEXT: ld1 { v1.b }[1], [x8] ; CHECK-NEXT: ld1 { v1.b }[1], [x8]
; CHECK-NEXT: add x8, sp, #624 ; CHECK-NEXT: add x8, sp, #624
; CHECK-NEXT: sshll v3.8h, v4.8b, #0 ; CHECK-NEXT: sshll v3.8h, v4.8b, #0
; CHECK-NEXT: mov v6.s[0], v5.s[0] ; CHECK-NEXT: mov v6.s[0], v5.s[0]
; CHECK-NEXT: saddl2 v5.4s, v3.8h, v2.8h ; CHECK-NEXT: saddl2 v5.4s, v3.8h, v2.8h
; CHECK-NEXT: saddl2 v16.4s, v7.8h, v0.8h ; CHECK-NEXT: saddl2 v16.4s, v7.8h, v0.8h
; CHECK-NEXT: ld1 { v1.b }[2], [x8] ; CHECK-NEXT: ld1 { v1.b }[2], [x8]
; CHECK-NEXT: add x8, sp, #488 ; CHECK-NEXT: add x8, sp, #488
; CHECK-NEXT: saddw v4.4s, v6.4s, v7.4h ; CHECK-NEXT: saddw v4.4s, v6.4s, v7.4h
; CHECK-NEXT: ldr b6, [sp, #480] ; CHECK-NEXT: ldr b6, [sp, #480]
; CHECK-NEXT: add v5.4s, v16.4s, v5.4s ; CHECK-NEXT: add v5.4s, v16.4s, v5.4s
; CHECK-NEXT: ldr b7, [sp, #544] ; CHECK-NEXT: ldr b7, [sp, #672]
; CHECK-NEXT: ldr b16, [sp, #672] ; CHECK-NEXT: ldr b16, [sp, #544]
; CHECK-NEXT: ld1 { v6.b }[1], [x8] ; CHECK-NEXT: ld1 { v6.b }[1], [x8]
; CHECK-NEXT: add x8, sp, #496 ; CHECK-NEXT: add x8, sp, #496
; CHECK-NEXT: ld1 { v7.b }[1], [x9] ; CHECK-NEXT: ld1 { v7.b }[1], [x9]
; CHECK-NEXT: add x9, sp, #560 ; CHECK-NEXT: add x9, sp, #688
; CHECK-NEXT: ld1 { v16.b }[1], [x10] ; CHECK-NEXT: ld1 { v16.b }[1], [x10]
; CHECK-NEXT: add x10, sp, #688 ; CHECK-NEXT: add x10, sp, #560
; CHECK-NEXT: ld1 { v1.b }[3], [x11] ; CHECK-NEXT: ld1 { v1.b }[3], [x11]
; CHECK-NEXT: add x11, sp, #640 ; CHECK-NEXT: add x11, sp, #640
; CHECK-NEXT: ld1 { v6.b }[2], [x8] ; CHECK-NEXT: ld1 { v6.b }[2], [x8]
; CHECK-NEXT: add x8, sp, #504 ; CHECK-NEXT: add x8, sp, #504
; CHECK-NEXT: ld1 { v7.b }[2], [x9] ; CHECK-NEXT: ld1 { v7.b }[2], [x9]
; CHECK-NEXT: add x9, sp, #568 ; CHECK-NEXT: add x9, sp, #696
; CHECK-NEXT: ld1 { v16.b }[2], [x10] ; CHECK-NEXT: ld1 { v16.b }[2], [x10]
; CHECK-NEXT: add x10, sp, #696 ; CHECK-NEXT: add x10, sp, #568
; CHECK-NEXT: ld1 { v1.b }[4], [x11] ; CHECK-NEXT: ld1 { v1.b }[4], [x11]
; CHECK-NEXT: add x11, sp, #648 ; CHECK-NEXT: add x11, sp, #648
; CHECK-NEXT: ld1 { v6.b }[3], [x8] ; CHECK-NEXT: ld1 { v6.b }[3], [x8]
; CHECK-NEXT: add x8, sp, #512 ; CHECK-NEXT: add x8, sp, #512
; CHECK-NEXT: ld1 { v7.b }[3], [x9] ; CHECK-NEXT: ld1 { v7.b }[3], [x9]
; CHECK-NEXT: add x9, sp, #576 ; CHECK-NEXT: add x9, sp, #704
; CHECK-NEXT: ld1 { v16.b }[3], [x10] ; CHECK-NEXT: ld1 { v16.b }[3], [x10]
; CHECK-NEXT: add x10, sp, #704 ; CHECK-NEXT: add x10, sp, #576
; CHECK-NEXT: ld1 { v1.b }[5], [x11] ; CHECK-NEXT: ld1 { v1.b }[5], [x11]
; CHECK-NEXT: add x11, sp, #656 ; CHECK-NEXT: add x11, sp, #656
; CHECK-NEXT: ld1 { v6.b }[4], [x8] ; CHECK-NEXT: ld1 { v6.b }[4], [x8]
; CHECK-NEXT: add x8, sp, #520 ; CHECK-NEXT: add x8, sp, #520
; CHECK-NEXT: ld1 { v7.b }[4], [x9] ; CHECK-NEXT: ld1 { v7.b }[4], [x9]
; CHECK-NEXT: add x9, sp, #584 ; CHECK-NEXT: add x9, sp, #712
; CHECK-NEXT: ld1 { v16.b }[4], [x10] ; CHECK-NEXT: ld1 { v16.b }[4], [x10]
; CHECK-NEXT: add x10, sp, #712 ; CHECK-NEXT: add x10, sp, #584
; CHECK-NEXT: ld1 { v1.b }[6], [x11] ; CHECK-NEXT: ld1 { v1.b }[6], [x11]
; CHECK-NEXT: add x11, sp, #664 ; CHECK-NEXT: add x11, sp, #664
; CHECK-NEXT: ld1 { v6.b }[5], [x8] ; CHECK-NEXT: ld1 { v6.b }[5], [x8]
; CHECK-NEXT: add x8, sp, #528 ; CHECK-NEXT: add x8, sp, #528
; CHECK-NEXT: ld1 { v7.b }[5], [x9] ; CHECK-NEXT: ld1 { v7.b }[5], [x9]
; CHECK-NEXT: add x9, sp, #592 ; CHECK-NEXT: add x9, sp, #720
; CHECK-NEXT: ld1 { v16.b }[5], [x10] ; CHECK-NEXT: ld1 { v16.b }[5], [x10]
; CHECK-NEXT: add x10, sp, #720 ; CHECK-NEXT: add x10, sp, #592
; CHECK-NEXT: saddl v2.4s, v3.4h, v2.4h ; CHECK-NEXT: saddl v2.4s, v3.4h, v2.4h
; CHECK-NEXT: ldr b3, [sp, #736] ; CHECK-NEXT: ldr b3, [sp, #736]
; CHECK-NEXT: ld1 { v6.b }[6], [x8] ; CHECK-NEXT: ld1 { v6.b }[6], [x8]
; CHECK-NEXT: add x8, sp, #600 ; CHECK-NEXT: add x8, sp, #728
; CHECK-NEXT: saddw v0.4s, v4.4s, v0.4h ; CHECK-NEXT: saddw v0.4s, v4.4s, v0.4h
; CHECK-NEXT: ld1 { v7.b }[6], [x9] ; CHECK-NEXT: ld1 { v7.b }[6], [x9]
; CHECK-NEXT: ld1 { v16.b }[6], [x10] ; CHECK-NEXT: ld1 { v16.b }[6], [x10]
; CHECK-NEXT: add x9, sp, #728 ; CHECK-NEXT: add x9, sp, #600
; CHECK-NEXT: add x10, sp, #536 ; CHECK-NEXT: add x10, sp, #536
; CHECK-NEXT: ld1 { v1.b }[7], [x11] ; CHECK-NEXT: ld1 { v1.b }[7], [x11]
; CHECK-NEXT: movi v4.2d, #0000000000000000 ; CHECK-NEXT: movi v4.2d, #0000000000000000
; CHECK-NEXT: add v0.4s, v0.4s, v2.4s ; CHECK-NEXT: add v0.4s, v0.4s, v2.4s
; CHECK-NEXT: ld1 { v7.b }[7], [x8] ; CHECK-NEXT: ld1 { v7.b }[7], [x8]
; CHECK-NEXT: sshll v2.8h, v3.8b, #0 ; CHECK-NEXT: sshll v2.8h, v3.8b, #0
; CHECK-NEXT: ld1 { v16.b }[7], [x9] ; CHECK-NEXT: ld1 { v16.b }[7], [x9]
; CHECK-NEXT: ld1 { v6.b }[7], [x10] ; CHECK-NEXT: ld1 { v6.b }[7], [x10]
; CHECK-NEXT: sshll v2.4s, v2.4h, #0 ; CHECK-NEXT: sshll v2.4s, v2.4h, #0
; CHECK-NEXT: sshll v1.8h, v1.8b, #0 ; CHECK-NEXT: sshll v1.8h, v1.8b, #0
; CHECK-NEXT: mov v4.s[0], v2.s[0] ; CHECK-NEXT: mov v4.s[0], v2.s[0]
; CHECK-NEXT: sshll v3.8h, v7.8b, #0 ; CHECK-NEXT: sshll v3.8h, v7.8b, #0
; CHECK-NEXT: sshll v7.8h, v16.8b, #0 ; CHECK-NEXT: sshll v7.8h, v16.8b, #0
; CHECK-NEXT: sshll v2.8h, v6.8b, #0 ; CHECK-NEXT: sshll v2.8h, v6.8b, #0
; CHECK-NEXT: saddl2 v6.4s, v7.8h, v3.8h ; CHECK-NEXT: saddl2 v6.4s, v7.8h, v3.8h
; CHECK-NEXT: saddl2 v16.4s, v1.8h, v2.8h ; CHECK-NEXT: saddl2 v16.4s, v2.8h, v1.8h
; CHECK-NEXT: saddw v2.4s, v4.4s, v2.4h ; CHECK-NEXT: saddw v2.4s, v4.4s, v2.4h
; CHECK-NEXT: saddl v3.4s, v7.4h, v3.4h ; CHECK-NEXT: saddl v3.4s, v7.4h, v3.4h
; CHECK-NEXT: add v4.4s, v16.4s, v6.4s ; CHECK-NEXT: add v4.4s, v16.4s, v6.4s
; CHECK-NEXT: saddw v1.4s, v2.4s, v1.4h ; CHECK-NEXT: saddw v1.4s, v2.4s, v1.4h
; CHECK-NEXT: add v2.4s, v3.4s, v4.4s ; CHECK-NEXT: add v2.4s, v3.4s, v4.4s
; CHECK-NEXT: add v0.4s, v0.4s, v5.4s ; CHECK-NEXT: add v0.4s, v0.4s, v5.4s
; CHECK-NEXT: add v1.4s, v1.4s, v2.4s ; CHECK-NEXT: add v1.4s, v1.4s, v2.4s
; CHECK-NEXT: add v0.4s, v0.4s, v1.4s ; CHECK-NEXT: add v0.4s, v0.4s, v1.4s
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llvm/test/CodeGen/PowerPC/p10-spill-crun.ll

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; CHECK-NEXT: cmpdi cr4, r3, 0 ; CHECK-NEXT: cmpdi cr4, r3, 0
; CHECK-NEXT: andi. r3, r28, 4 ; CHECK-NEXT: andi. r3, r28, 4
; CHECK-NEXT: cmpwi cr2, r27, 0 ; CHECK-NEXT: cmpwi cr2, r27, 0
; CHECK-NEXT: mcrf cr3, cr0 ; CHECK-NEXT: mcrf cr3, cr0
; CHECK-NEXT: .p2align 5 ; CHECK-NEXT: .p2align 5
; CHECK-NEXT: .LBB0_8: # %bb27 ; CHECK-NEXT: .LBB0_8: # %bb27
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: mr r3, r30 ; CHECK-NEXT: mr r3, r30
; CHECK-NEXT: li r4, 0
; CHECK-NEXT: bl call_6@notoc ; CHECK-NEXT: bl call_6@notoc
; CHECK-NEXT: bc 4, 4*cr4+eq, .LBB0_18 ; CHECK-NEXT: bc 4, 4*cr4+eq, .LBB0_18
; CHECK-NEXT: # %bb.9: # %bb31 ; CHECK-NEXT: # %bb.9: # %bb31
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: bc 4, 4*cr3+eq, .LBB0_18 ; CHECK-NEXT: bc 4, 4*cr3+eq, .LBB0_18
; CHECK-NEXT: # %bb.10: # %bb33 ; CHECK-NEXT: # %bb.10: # %bb33
; CHECK-NEXT: # ; CHECK-NEXT: #
; CHECK-NEXT: bc 4, 4*cr2+eq, .LBB0_8 ; CHECK-NEXT: bc 4, 4*cr2+eq, .LBB0_8
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; CHECK-NEXT: xxspltidp vs4, -1082130432 ; CHECK-NEXT: xxspltidp vs4, -1082130432
; CHECK-NEXT: extsh r9, r3 ; CHECK-NEXT: extsh r9, r3
; CHECK-NEXT: extsw r6, r28 ; CHECK-NEXT: extsw r6, r28
; CHECK-NEXT: li r5, 0 ; CHECK-NEXT: li r5, 0
; CHECK-NEXT: li r7, 0 ; CHECK-NEXT: li r7, 0
; CHECK-NEXT: std r30, 104(r1) ; CHECK-NEXT: std r30, 104(r1)
; CHECK-NEXT: std r29, 96(r1) ; CHECK-NEXT: std r29, 96(r1)
; CHECK-NEXT: li r8, 0 ; CHECK-NEXT: li r8, 0
; CHECK-NEXT: li r10, 0
; CHECK-NEXT: xxlxor f1, f1, f1 ; CHECK-NEXT: xxlxor f1, f1, f1
; CHECK-NEXT: std r4, 152(r1) ; CHECK-NEXT: std r4, 152(r1)
; CHECK-NEXT: li r4, -1 ; CHECK-NEXT: li r4, -1
; CHECK-NEXT: std r4, 112(r1) ; CHECK-NEXT: std r4, 112(r1)
; CHECK-NEXT: li r4, 1024 ; CHECK-NEXT: li r4, 1024
; CHECK-NEXT: bl call_4@notoc ; CHECK-NEXT: bl call_4@notoc
; CHECK-NEXT: .LBB0_16: # %bb54 ; CHECK-NEXT: .LBB0_16: # %bb54
; CHECK-NEXT: bc 12, 4*cr2+un, .LBB0_19 ; CHECK-NEXT: bc 12, 4*cr2+un, .LBB0_19
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; CHECK-BE-NEXT: cmpdi cr4, r3, 0 ; CHECK-BE-NEXT: cmpdi cr4, r3, 0
; CHECK-BE-NEXT: andi. r3, r28, 4 ; CHECK-BE-NEXT: andi. r3, r28, 4
; CHECK-BE-NEXT: cmpwi cr2, r27, 0 ; CHECK-BE-NEXT: cmpwi cr2, r27, 0
; CHECK-BE-NEXT: mcrf cr3, cr0 ; CHECK-BE-NEXT: mcrf cr3, cr0
; CHECK-BE-NEXT: .p2align 5 ; CHECK-BE-NEXT: .p2align 5
; CHECK-BE-NEXT: .LBB0_8: # %bb27 ; CHECK-BE-NEXT: .LBB0_8: # %bb27
; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: #
; CHECK-BE-NEXT: mr r3, r30 ; CHECK-BE-NEXT: mr r3, r30
; CHECK-BE-NEXT: li r4, 0
; CHECK-BE-NEXT: bl call_6 ; CHECK-BE-NEXT: bl call_6
; CHECK-BE-NEXT: nop ; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: bc 4, 4*cr4+eq, .LBB0_18 ; CHECK-BE-NEXT: bc 4, 4*cr4+eq, .LBB0_18
; CHECK-BE-NEXT: # %bb.9: # %bb31 ; CHECK-BE-NEXT: # %bb.9: # %bb31
; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: #
; CHECK-BE-NEXT: bc 4, 4*cr3+eq, .LBB0_18 ; CHECK-BE-NEXT: bc 4, 4*cr3+eq, .LBB0_18
; CHECK-BE-NEXT: # %bb.10: # %bb33 ; CHECK-BE-NEXT: # %bb.10: # %bb33
; CHECK-BE-NEXT: # ; CHECK-BE-NEXT: #
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; CHECK-BE-NEXT: xxspltidp vs4, -1082130432 ; CHECK-BE-NEXT: xxspltidp vs4, -1082130432
; CHECK-BE-NEXT: extsh r9, r3 ; CHECK-BE-NEXT: extsh r9, r3
; CHECK-BE-NEXT: extsw r6, r28 ; CHECK-BE-NEXT: extsw r6, r28
; CHECK-BE-NEXT: li r5, 0 ; CHECK-BE-NEXT: li r5, 0
; CHECK-BE-NEXT: li r7, 0 ; CHECK-BE-NEXT: li r7, 0
; CHECK-BE-NEXT: std r30, 120(r1) ; CHECK-BE-NEXT: std r30, 120(r1)
; CHECK-BE-NEXT: std r29, 112(r1) ; CHECK-BE-NEXT: std r29, 112(r1)
; CHECK-BE-NEXT: li r8, 0 ; CHECK-BE-NEXT: li r8, 0
; CHECK-BE-NEXT: li r10, 0
; CHECK-BE-NEXT: xxlxor f1, f1, f1 ; CHECK-BE-NEXT: xxlxor f1, f1, f1
; CHECK-BE-NEXT: std r4, 168(r1) ; CHECK-BE-NEXT: std r4, 168(r1)
; CHECK-BE-NEXT: li r4, -1 ; CHECK-BE-NEXT: li r4, -1
; CHECK-BE-NEXT: std r4, 128(r1) ; CHECK-BE-NEXT: std r4, 128(r1)
; CHECK-BE-NEXT: li r4, 1024 ; CHECK-BE-NEXT: li r4, 1024
; CHECK-BE-NEXT: bl call_4 ; CHECK-BE-NEXT: bl call_4
; CHECK-BE-NEXT: nop ; CHECK-BE-NEXT: nop
; CHECK-BE-NEXT: .LBB0_16: # %bb54 ; CHECK-BE-NEXT: .LBB0_16: # %bb54
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llvm/test/CodeGen/RISCV/miss-sp-restore-eh.ll

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; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: .cfi_offset ra, -8 ; CHECK-NEXT: .cfi_offset ra, -8
; CHECK-NEXT: .cfi_offset s0, -16 ; CHECK-NEXT: .cfi_offset s0, -16
; CHECK-NEXT: .cfi_offset s1, -24 ; CHECK-NEXT: .cfi_offset s1, -24
; CHECK-NEXT: addi s0, sp, 32 ; CHECK-NEXT: addi s0, sp, 32
; CHECK-NEXT: .cfi_def_cfa s0, 0 ; CHECK-NEXT: .cfi_def_cfa s0, 0
; CHECK-NEXT: .Ltmp0: ; CHECK-NEXT: .Ltmp0:
; CHECK-NEXT: addi sp, sp, -32 ; CHECK-NEXT: addi sp, sp, -32
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: li a1, 0
; CHECK-NEXT: li a2, 0
; CHECK-NEXT: li a3, 0
; CHECK-NEXT: li a4, 0
; CHECK-NEXT: li a5, 0
; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a7, 0
; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi@plt ; CHECK-NEXT: call _Z3fooiiiiiiiiiiPi@plt
; CHECK-NEXT: addi sp, sp, 32 ; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: .Ltmp1:
; CHECK-NEXT: # %bb.1: # %try.cont.unreachable ; CHECK-NEXT: # %bb.1: # %try.cont.unreachable
; CHECK-NEXT: .LBB0_2: # %lpad ; CHECK-NEXT: .LBB0_2: # %lpad
; CHECK-NEXT: .Ltmp2: ; CHECK-NEXT: .Ltmp2:
; CHECK-NEXT: sext.w a1, a1 ; CHECK-NEXT: sext.w a1, a1
; CHECK-NEXT: li a2, 1 ; CHECK-NEXT: li a2, 1
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llvm/test/CodeGen/RISCV/pr51206.ll

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; CHECK-NEXT: bltu a0, a3, .LBB0_2 ; CHECK-NEXT: bltu a0, a3, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb10 ; CHECK-NEXT: # %bb.1: # %bb10
; CHECK-NEXT: addi sp, sp, -16 ; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT: call quux@plt ; CHECK-NEXT: call quux@plt
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: .LBB0_2: # %bb12 ; CHECK-NEXT: .LBB0_2: # %bb12
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
bb: bb:
%tmp = load i8, ptr @global, align 1 %tmp = load i8, ptr @global, align 1
%tmp1 = zext i8 %tmp to i32 %tmp1 = zext i8 %tmp to i32
%tmp2 = add nuw nsw i32 %tmp1, 1 %tmp2 = add nuw nsw i32 %tmp1, 1
store i32 %tmp2, ptr @global.1, align 4 store i32 %tmp2, ptr @global.1, align 4
%tmp3 = load i8, ptr @global.2, align 1 %tmp3 = load i8, ptr @global.2, align 1
%tmp4 = zext i8 %tmp3 to i32 %tmp4 = zext i8 %tmp3 to i32
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llvm/test/CodeGen/RISCV/sext-zext-trunc.ll

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; RV64I-NEXT: seqz a0, a0 ; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: addi a0, a0, -1 ; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: ret ; RV64I-NEXT: ret
%cmp = icmp eq i64 %x, 7 %cmp = icmp eq i64 %x, 7
%zext = zext i1 %cmp to i64 %zext = zext i1 %cmp to i64
%dec = sub i64 %zext, 1 %dec = sub i64 %zext, 1
ret i64 %dec ret i64 %dec
} }
define dso_local signext i32 @ret_sext_i32undef_to_i64(i32 noundef signext %Int_1_Par_Val, i32 noundef signext %Int_2_Par_Val, ptr nocapture noundef writeonly %Int_Par_Ref) local_unnamed_addr align 8 {
; RV32I-LABEL: ret_sext_i32undef_to_i64:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: addi a0, a0, 2
; RV32I-NEXT: sw a0, 0(a2)
; RV32I-NEXT: ret
;
; RV64I-LABEL: ret_sext_i32undef_to_i64:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: addiw a0, a0, 2
; RV64I-NEXT: sw a0, 0(a2)
; RV64I-NEXT: ret
entry:
%add = add nsw i32 %Int_1_Par_Val, 2
%add1 = add nsw i32 %add, %Int_2_Par_Val
store i32 %add1, ptr %Int_Par_Ref, align 4
ret i32 undef
}

llvm/test/CodeGen/X86/vector-shuffle-v1.ll

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} }
define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) { define <2 x i1> @shuf2i1_1_2(<2 x i1> %a) {
; AVX512F-LABEL: shuf2i1_1_2: ; AVX512F-LABEL: shuf2i1_1_2:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0 ; AVX512F-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0] ; AVX512F-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; AVX512F-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7] ; AVX512F-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1 ; AVX512F-NEXT: vptestmq %zmm0, %zmm0, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0 ; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: shuf2i1_1_2: ; AVX512VL-LABEL: shuf2i1_1_2:
; AVX512VL: # %bb.0: ; AVX512VL: # %bb.0:
; AVX512VL-NEXT: vpsllq $63, %xmm0, %xmm0 ; AVX512VL-NEXT: vpsllq $63, %xmm0, %xmm0
; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k1 ; AVX512VL-NEXT: vptestmq %xmm0, %xmm0, %k1
; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 ; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} {z} ; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm1 {%k1} {z}
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm2 = [18446744073709551615,0] ; AVX512VL-NEXT: vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7]
; AVX512VL-NEXT: vpalignr {{.*#+}} xmm1 = xmm1[8,9,10,11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7]
; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1 ; AVX512VL-NEXT: vptestmq %xmm1, %xmm1, %k1
; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z} ; AVX512VL-NEXT: vmovdqa64 %xmm0, %xmm0 {%k1} {z}
; AVX512VL-NEXT: retq ; AVX512VL-NEXT: retq
; ;
; VL_BW_DQ-LABEL: shuf2i1_1_2: ; VL_BW_DQ-LABEL: shuf2i1_1_2:
; VL_BW_DQ: # %bb.0: ; VL_BW_DQ: # %bb.0:
; VL_BW_DQ-NEXT: vpsllq $63, %xmm0, %xmm0 ; VL_BW_DQ-NEXT: vpsllq $63, %xmm0, %xmm0
; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0
; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 ; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0
; VL_BW_DQ-NEXT: vmovdqa {{.*#+}} xmm1 = [18446744073709551615,0] ; VL_BW_DQ-NEXT: vpcmpeqd %xmm1, %xmm1, %xmm1
; VL_BW_DQ-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7] ; VL_BW_DQ-NEXT: vpalignr {{.*#+}} xmm0 = xmm0[8,9,10,11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7]
; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0 ; VL_BW_DQ-NEXT: vpmovq2m %xmm0, %k0
; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0 ; VL_BW_DQ-NEXT: vpmovm2q %k0, %xmm0
; VL_BW_DQ-NEXT: retq ; VL_BW_DQ-NEXT: retq
%b = shufflevector <2 x i1> %a, <2 x i1> <i1 1, i1 0>, <2 x i32> <i32 1, i32 2> %b = shufflevector <2 x i1> %a, <2 x i1> <i1 1, i1 0>, <2 x i32> <i32 1, i32 2>
ret <2 x i1> %b ret <2 x i1> %b
} }
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} }
define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) { define i8 @shuf8i1__9_6_1_10_3_7_7_1(i8 %a) {
; AVX512F-LABEL: shuf8i1__9_6_1_10_3_7_7_1: ; AVX512F-LABEL: shuf8i1__9_6_1_10_3_7_7_1:
; AVX512F: # %bb.0: ; AVX512F: # %bb.0:
; AVX512F-NEXT: kmovw %edi, %k1 ; AVX512F-NEXT: kmovw %edi, %k1
; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z} ; AVX512F-NEXT: vpternlogq $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [9,6,1,0,3,7,7,1] ; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm1 = [9,6,1,0,3,7,7,1]
; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,0,0,0,0] ; AVX512F-NEXT: vbroadcasti64x4 {{.*#+}} zmm2 = [18446744073709551615,18446744073709551615,0,0,18446744073709551615,18446744073709551615,0,0]
; AVX512F-NEXT: # zmm2 = mem[0,1,2,3,0,1,2,3]
; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm2 ; AVX512F-NEXT: vpermt2q %zmm0, %zmm1, %zmm2
; AVX512F-NEXT: vptestmq %zmm2, %zmm2, %k0 ; AVX512F-NEXT: vptestmq %zmm2, %zmm2, %k0
; AVX512F-NEXT: kmovw %k0, %eax ; AVX512F-NEXT: kmovw %k0, %eax
; AVX512F-NEXT: # kill: def $al killed $al killed $eax ; AVX512F-NEXT: # kill: def $al killed $al killed $eax
; AVX512F-NEXT: vzeroupper ; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq ; AVX512F-NEXT: retq
; ;
; AVX512VL-LABEL: shuf8i1__9_6_1_10_3_7_7_1: ; AVX512VL-LABEL: shuf8i1__9_6_1_10_3_7_7_1:
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