[RISCV] Add missing Read classes to some compressed instructions.

[wangpc]

Typo in title: classe->classes.
IIUC, the change has no influence to scheduler but static machine code analyser like llvm-mca, since there is no C instructions when doing scheduling.

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

554

Comment not aim for this patch:
Do we really need a SchedWrite WriteJmpReg? It's only used in C instructions and it won't influence scheduler actually.
I think it can be removed and replaced by WriteJalr.

[craig.topper]

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

554

Agreed. I’ll post another patch for that.

[wangpc]

LGTM

llvm/lib/Target/RISCV/RISCVInstrInfoC.td

 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_J : RVInst16CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
                      "c.j", "$offset">, Sched<[WriteJmp]> {
   let isBranch = 1;
   let isTerminator=1;
   let isBarrier=1;
 }
 
-def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp]>;
-def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp]>;
+def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp, ReadJmp]>;
+def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp, ReadJmp]>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
                         (ins GPRNoX0:$rd, uimmlog2xlennonzero:$imm),
                         "c.slli", "$rd, $imm">,
              Sched<[WriteShiftImm, ReadShiftImm]> {
   let Constraints = "$rd = $rd_wb";
   let Inst{6-2} = imm{4-0};

 def C_LDSP : CStackLoad<0b011, "c.ldsp", GPRNoX0, uimm9_lsb000>,
              Sched<[WriteLDD, ReadMemBase]> {
   let Inst{6-5} = imm{4-3};
   let Inst{4-2} = imm{8-6};
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
-                      "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
+                      "c.jr", "$rs1">, Sched<[WriteJmpReg, ReadJalr]> {
   let isBarrier = 1;
   let isTerminator = 1;
   let rs2 = 0;
 }
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
     isAsCheapAsAMove = 1 in
 def C_MV : RVInst16CR<0b1000, 0b10, (outs GPRNoX0:$rs1), (ins GPRNoX0:$rs2),

llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s

 beqz a0, 1f
 1:
 c.add a0, a0
 bnez a0, 1f
 1:
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      18
-# CHECK-NEXT: Total Cycles:      24
+# CHECK-NEXT: Total Cycles:      20
 # CHECK-NEXT: Total uOps:        18
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.75
-# CHECK-NEXT: IPC:               0.75
+# CHECK-NEXT: uOps Per Cycle:    0.90
+# CHECK-NEXT: IPC:               0.90
 # CHECK-NEXT: Block RThroughput: 9.0
 
 # CHECK:      Instruction Info:
 # CHECK-NEXT: [1]: #uOps
 # CHECK-NEXT: [2]: Latency
 # CHECK-NEXT: [3]: RThroughput
 # CHECK-NEXT: [4]: MayLoad
 # CHECK-NEXT: [5]: MayStore

 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     srai  a0, a0, 1
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     add a0, a0, a0
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     beqz  a0, .Ltmp0
 # CHECK-NEXT:  -      -     1.00    -      -      -      -      -     add a0, a0, a0
 # CHECK-NEXT:  -      -      -     1.00    -      -      -      -     bnez  a0, .Ltmp1
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0123
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeE .    .    .    .  .   lui  a0, 1
-# CHECK-NEXT: [0,1]     .DeeE.    .    .    .  .   add  a0, a0, a0
-# CHECK-NEXT: [0,2]     . DeeE    .    .    .  .   addi a0, a0, 1
-# CHECK-NEXT: [0,3]     .  DeeE   .    .    .  .   addw a0, a0, a0
-# CHECK-NEXT: [0,4]     .   DeeE  .    .    .  .   addiw  a0, a0, 1
-# CHECK-NEXT: [0,5]     .    DeeE .    .    .  .   sub  a0, a0, a0
-# CHECK-NEXT: [0,6]     .    .DeeE.    .    .  .   subw a0, a0, a0
-# CHECK-NEXT: [0,7]     .    . DeeE    .    .  .   and  a0, a0, a0
-# CHECK-NEXT: [0,8]     .    .  DeeE   .    .  .   andi a0, a0, 1
-# CHECK-NEXT: [0,9]     .    .   DeeE  .    .  .   or a0, a0, a0
-# CHECK-NEXT: [0,10]    .    .    DeeE .    .  .   xor  a0, a0, a0
-# CHECK-NEXT: [0,11]    .    .    .DeeE.    .  .   slli a0, a0, 1
-# CHECK-NEXT: [0,12]    .    .    . DeeE    .  .   srli a0, a0, 1
-# CHECK-NEXT: [0,13]    .    .    .  DeeE   .  .   srai a0, a0, 1
-# CHECK-NEXT: [0,14]    .    .    .   DeeE  .  .   add  a0, a0, a0
-# CHECK-NEXT: [0,15]    .    .    .    . DeeE  .   beqz a0, .Ltmp0
-# CHECK-NEXT: [0,16]    .    .    .    . DeeE  .   add  a0, a0, a0
-# CHECK-NEXT: [0,17]    .    .    .    .    DeeE   bnez a0, .Ltmp1
+# CHECK:      [0,0]     DeeE .    .    .   .   lui  a0, 1
+# CHECK-NEXT: [0,1]     .DeeE.    .    .   .   add  a0, a0, a0
+# CHECK-NEXT: [0,2]     . DeeE    .    .   .   addi a0, a0, 1
+# CHECK-NEXT: [0,3]     .  DeeE   .    .   .   addw a0, a0, a0
+# CHECK-NEXT: [0,4]     .   DeeE  .    .   .   addiw  a0, a0, 1
+# CHECK-NEXT: [0,5]     .    DeeE .    .   .   sub  a0, a0, a0
+# CHECK-NEXT: [0,6]     .    .DeeE.    .   .   subw a0, a0, a0
+# CHECK-NEXT: [0,7]     .    . DeeE    .   .   and  a0, a0, a0
+# CHECK-NEXT: [0,8]     .    .  DeeE   .   .   andi a0, a0, 1
+# CHECK-NEXT: [0,9]     .    .   DeeE  .   .   or a0, a0, a0
+# CHECK-NEXT: [0,10]    .    .    DeeE .   .   xor  a0, a0, a0
+# CHECK-NEXT: [0,11]    .    .    .DeeE.   .   slli a0, a0, 1
+# CHECK-NEXT: [0,12]    .    .    . DeeE   .   srli a0, a0, 1
+# CHECK-NEXT: [0,13]    .    .    .  DeeE  .   srai a0, a0, 1
+# CHECK-NEXT: [0,14]    .    .    .   DeeE .   add  a0, a0, a0
+# CHECK-NEXT: [0,15]    .    .    .    DeeE.   beqz a0, .Ltmp0
+# CHECK-NEXT: [0,16]    .    .    .    DeeE.   add  a0, a0, a0
+# CHECK-NEXT: [0,17]    .    .    .    .DeeE   bnez a0, .Ltmp1
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
 # CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
 # CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
 # CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
 
 # CHECK:            [0]    [1]    [2]    [3]