This is an archive of the discontinued LLVM Phabricator instance.

[BOLT][RISCV] Add tests for simple CFG transformations
ClosedPublic

Authored by jobnoorman on Jun 20 2023, 6:57 AM.

Diff Detail

Event Timeline

jobnoorman created this revision.Jun 20 2023, 6:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2023, 6:57 AM
jobnoorman requested review of this revision.Jun 20 2023, 6:57 AM
Herald added a project: Restricted Project. · View Herald TranscriptJun 20 2023, 6:57 AM
rafauler added inline comments.Jun 20 2023, 6:18 PM
bolt/test/RISCV/internal-func-reloc.s
12

This is something we might want to ask of binaries that intend to be BOLTed, as BOLT is going to do a lot of things that RISCV is attempting to do with linkers and linker relaxation. This is specially true if BOLT later reorders functions in a way that now requires thunks/stubs insertion to extend the range of branches that got prematurely relaxed by the linker.

jobnoorman added inline comments.Jun 21 2023, 1:37 AM
bolt/test/RISCV/internal-func-reloc.s
12

My hope is that this won't be necessary, as it goes against the idea of BOLT working on production binaries where linker relaxation will most certainly be enabled for RISC-V.

I have a WIP patch that tries to deal with this (in a nutshell: "unrelax" instructions in BOLT and let JITLink relax them again later, if possible) that I hope to be able to post later this week.

rafauler accepted this revision.Jun 21 2023, 1:20 PM
This revision is now accepted and ready to land.Jun 21 2023, 1:20 PM
This revision was automatically updated to reflect the committed changes.