[RISCV] Eliminate the extension of index for vector indexed load/store.

[jacquesguan]

Summary

If the offset vector of vector indexed load/store is an extension, we could eliminate it and use the source operand as the index directly.

[sorear]

Is the SIGN_EXTEND case actually correct? Vector indexed memory operations always zero-extend the index, and the getelementptr doesn't provide enough information to prove the indices are nonnegative.

I think the best we can do without new metadata is

vsetvli zero, a1, e8, m1, ta, ma
addi a0, a0, -128
li a1, -128
vxor.vs v9, v9, a1  # vfneg.v can be used for some SEW
vsoxei8.v v8, (a0), v9, v0.t

[jacquesguan]

Limit to zero_ext.

[jacquesguan]

In D152679#4416200, @sorear wrote:

Is the SIGN_EXTEND case actually correct? Vector indexed memory operations always zero-extend the index, and the getelementptr doesn't provide enough information to prove the indices are nonnegative.

I think the best we can do without new metadata is

vsetvli zero, a1, e8, m1, ta, ma
addi a0, a0, -128
li a1, -128
vxor.vs v9, v9, a1  # vfneg.v can be used for some SEW
vsoxei8.v v8, (a0), v9, v0.t

Yes, I change this patch to match only zero_ext.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

void RISCVDAGToDAGISel::addVectorLoadStoreOperands(
     bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl<SDValue> &Operands,
     bool IsLoad, MVT *IndexVT) {
   SDValue Chain = Node->getOperand(0);
   SDValue Glue;
 
   Operands.push_back(Node->getOperand(CurOp++)); // Base pointer.
 
   if (IsStridedOrIndexed) {
-    Operands.push_back(Node->getOperand(CurOp++)); // Index.
+    SDValue StrideOrIndex = Node->getOperand(CurOp++);
+    if (IndexVT && StrideOrIndex.hasOneUse() &&
+        StrideOrIndex.getOpcode() == ISD::ZERO_EXTEND)
+      StrideOrIndex = StrideOrIndex.getOperand(0);
+    Operands.push_back(StrideOrIndex); // Index.
     if (IndexVT)
-      *IndexVT = Operands.back()->getSimpleValueType(0);
+      *IndexVT = StrideOrIndex->getSimpleValueType(0);
   }
 
   if (IsMasked) {
     // Mask needs to be copied to V0.
     SDValue Mask = Node->getOperand(CurOp++);
     Chain = CurDAG->getCopyToReg(Chain, DL, RISCV::V0, Mask, SDValue());
     Glue = Chain.getValue(1);
     Operands.push_back(CurDAG->getRegister(RISCV::V0, Mask.getValueType()));

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

%a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64(
     i64 %4, i64 1)
 
   ret <vscale x 8 x double> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vloxei64.v v8, (a0), v9
+; CHECK-NEXT:    vloxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64(
     <vscale x 1 x i64> undef,
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i64> %i,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vloxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     <vscale x 1 x i1> %3,
     i64 %4, i64 1)
 
   ret <vscale x 1 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/vloxei.ll

%a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8(
     iXLen %4, iXLen 1)
 
   ret <vscale x 8 x double> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vloxei32.v v8, (a0), v9
+; CHECK-NEXT:    vloxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64> undef,
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i32> %i,
     iXLen %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vloxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vloxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   %a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     <vscale x 1 x i1> %3,
     iXLen %4, iXLen 1)
 
   ret <vscale x 1 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

entry:
 
   ret <vscale x 8 x double> %a
 }
 
 
 define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vluxei64.v v8, (a0), v9
+; CHECK-NEXT:    vluxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64(
     <vscale x 1 x i64> undef,
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i64> %i,
     i64 %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vluxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     <vscale x 1 x i1> %3,
     i64 %4, i64 1)
 
   ret <vscale x 1 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/vluxei.ll

%a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(
     iXLen %4, iXLen 1)
 
   ret <vscale x 8 x double> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v9, v8
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vluxei32.v v8, (a0), v9
+; CHECK-NEXT:    vluxei8.v v9, (a0), v8
+; CHECK-NEXT:    vmv.v.v v8, v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64> undef,
     <vscale x 1 x i64>* %0,
     <vscale x 1 x i32> %i,
     iXLen %2)
 
   ret <vscale x 1 x i64> %a
 }
 
 define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
-; CHECK-NEXT:    vluxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vluxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   %a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     <vscale x 1 x i1> %3,
     iXLen %4, iXLen 1)
 
   ret <vscale x 1 x i64> %a
 }

llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll

call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64(
     i64 %4)
 
   ret void
 }
 
 define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei64.v v8, (a0), v10
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   call void @llvm.riscv.vsoxei.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     i64 %3)
 
   ret void
 }
 
 define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vsoxei.ll

call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i8(
     iXLen %4)
 
   ret void
 }
 
 define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei32.v v8, (a0), v10
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   call void @llvm.riscv.vsoxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     iXLen %3)
 
   ret void
 }
 
 define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsoxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsoxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     <vscale x 1 x i1> %3,
     iXLen %4)
 
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll

call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i64(
     i64 %4)
 
   ret void
 }
 
 define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei64.v v8, (a0), v10
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   call void @llvm.riscv.vsuxei.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     i64 %3)
 
   ret void
 }
 
 define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vzext.vf8 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei64.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
   call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i64(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i64> %i,
     <vscale x 1 x i1> %3,
     i64 %4)
 
   ret void
 }

llvm/test/CodeGen/RISCV/rvv/vsuxei.ll

call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i8(
     iXLen %4)
 
   ret void
 }
 
 define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei32.v v8, (a0), v10
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   call void @llvm.riscv.vsuxei.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     iXLen %3)
 
   ret void
 }
 
 define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
 ; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    vsetvli a2, zero, e32, mf2, ta, ma
-; CHECK-NEXT:    vzext.vf4 v10, v9
 ; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
-; CHECK-NEXT:    vsuxei32.v v8, (a0), v10, v0.t
+; CHECK-NEXT:    vsuxei8.v v8, (a0), v9, v0.t
 ; CHECK-NEXT:    ret
 entry:
   %i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
   call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i32(
     <vscale x 1 x i64> %0,
     <vscale x 1 x i64>* %1,
     <vscale x 1 x i32> %i,
     <vscale x 1 x i1> %3,
     iXLen %4)
 
   ret void
 }