This is an archive of the discontinued LLVM Phabricator instance.

Differential D152786

[RISCV][NFC] Pre-commit test for D152679.
Needs ReviewPublic

Authored by jacquesguan on Jun 13 2023, 1:34 AM.
This revision needs review, but there are no reviewers specified.

Details

Reviewers
None

Diff Detail

Revision Contents

PathSize
llvm/
test/
CodeGen/
RISCV/
rvv/
39 lines
39 lines
40 lines
39 lines
39 lines
39 lines
39 lines
39 lines

Diff 530813

llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll

Show First 20 Lines • Show All 1,333 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vloxei64.v v8, (a0), v9
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0,
<vscale x 1 x i64> %i,
i64 %2)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
<vscale x 1 x i1> %3,
i64 %4, i64 1)
ret <vscale x 1 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vloxei.ll

Show First 20 Lines • Show All 5,056 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x double> @llvm.riscv.vloxei.mask.nxv8f64.nxv8i8(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 1) iXLen %4, iXLen 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x i64> @intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vloxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vloxei32.v v8, (a0), v9
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0,
<vscale x 1 x i32> %i,
iXLen %2)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vloxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vloxei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
%a = call <vscale x 1 x i64> @llvm.riscv.vloxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll

Show First 20 Lines • Show All 1,333 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4, i64 1) i64 %4, i64 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vluxei64.v v8, (a0), v9
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i64>
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0,
<vscale x 1 x i64> %i,
i64 %2)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
<vscale x 1 x i1> %3,
i64 %4, i64 1)
ret <vscale x 1 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vluxei.ll

Show First 20 Lines • Show All 5,056 Lines • ▼ Show 20 Lines %a = call <vscale x 8 x double> @llvm.riscv.vluxei.mask.nxv8f64.nxv8i8(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 1) iXLen %4, iXLen 1)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
define <vscale x 1 x i64> @intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64>* %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
; CHECK-LABEL: intrinsic_vluxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v9, v8
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vluxei32.v v8, (a0), v9
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %1 to <vscale x 1 x i32>
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> undef,
<vscale x 1 x i64>* %0,
<vscale x 1 x i32> %i,
iXLen %2)
ret <vscale x 1 x i64> %a
}
define <vscale x 1 x i64> @intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vluxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu
; CHECK-NEXT: vluxei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
%a = call <vscale x 1 x i64> @llvm.riscv.vluxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
<vscale x 1 x i1> %3,
iXLen %4, iXLen 1)
ret <vscale x 1 x i64> %a
}

llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll

Show First 20 Lines • Show All 1,285 Lines • ▼ Show 20 Lines call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret void ret void
} }
define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsoxei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
call void @llvm.riscv.vsoxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
i64 %3)
ret void
}
define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsoxei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
<vscale x 1 x i1> %3,
i64 %4)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vsoxei.ll

Show First 20 Lines • Show All 4,872 Lines • ▼ Show 20 Lines call void @llvm.riscv.vsoxei.mask.nxv8f64.nxv8i8(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4)
ret void ret void
} }
define void @intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsoxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsoxei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
call void @llvm.riscv.vsoxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
iXLen %3)
ret void
}
define void @intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsoxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsoxei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
call void @llvm.riscv.vsoxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
<vscale x 1 x i1> %3,
iXLen %4)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll

Show First 20 Lines • Show All 1,285 Lines • ▼ Show 20 Lines call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i64(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i64> %2, <vscale x 8 x i64> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
i64 %4) i64 %4)
ret void ret void
} }
define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, i64 %3) nounwind {
; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsuxei64.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
call void @llvm.riscv.vsuxei.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
i64 %3)
ret void
}
define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e64, m1, ta, ma
; CHECK-NEXT: vzext.vf8 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsuxei64.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i64>
call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i64(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i64> %i,
<vscale x 1 x i1> %3,
i64 %4)
ret void
}

llvm/test/CodeGen/RISCV/rvv/vsuxei.ll

Show First 20 Lines • Show All 4,872 Lines • ▼ Show 20 Lines call void @llvm.riscv.vsuxei.mask.nxv8f64.nxv8i8(
<vscale x 8 x double> %0, <vscale x 8 x double> %0,
<vscale x 8 x double>* %1, <vscale x 8 x double>* %1,
<vscale x 8 x i8> %2, <vscale x 8 x i8> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4) iXLen %4)
ret void ret void
} }
define void @intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vsuxei_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsuxei32.v v8, (a0), v10
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
call void @llvm.riscv.vsuxei.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
iXLen %3)
ret void
}
define void @intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i64> %0, <vscale x 1 x i64>* %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vsuxei_mask_v_zextidx_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli a2, zero, e32, mf2, ta, ma
; CHECK-NEXT: vzext.vf4 v10, v9
; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma
; CHECK-NEXT: vsuxei32.v v8, (a0), v10, v0.t
; CHECK-NEXT: ret
entry:
%i = zext <vscale x 1 x i8> %2 to <vscale x 1 x i32>
call void @llvm.riscv.vsuxei.mask.nxv1i64.nxv1i32(
<vscale x 1 x i64> %0,
<vscale x 1 x i64>* %1,
<vscale x 1 x i32> %i,
<vscale x 1 x i1> %3,
iXLen %4)
ret void
}