[AArch64][SVE] Add one-use-check to EitherVSelectOrPassthruPatFrags

[dmgreen]

Summary

As pointed out in D149968 vselect predicate patterns could do with a one-use check to prevent multiple operations being created. This updates the EitherVSelectOrPassthruPatFrags pattern frags used in creating predicates min/max.

[dmgreen]

Ping for this and the related patches.

llvm/lib/Target/AArch64/SVEInstrFormats.td

 // SVE pattern match helpers.
 //===----------------------------------------------------------------------===//
 
 // Matches either an intrinsic, or a predicated operation with an all active predicate
 class EitherVSelectOrPassthruPatFrags<SDPatternOperator intrinsic, SDPatternOperator sdnode>
 : PatFrags<(ops node:$Pg, node:$Op1, node:$Op2), [
     (intrinsic node:$Pg, node:$Op1, node:$Op2),
     (vselect node:$Pg, (sdnode (SVEAllActive), node:$Op1, node:$Op2), node:$Op1),
-  ]>;
+  ], [{
+    return N->getOpcode() != ISD::VSELECT || N->getOperand(1).hasOneUse();
+  }]>;
 
 //
 // Pseudo -> Instruction mappings
 //
 def getSVEPseudoMap : InstrMapping {
   let FilterClass = "SVEPseudo2Instr";
   let RowFields = ["PseudoName"];
   let ColFields = ["IsInstr"];

llvm/test/CodeGen/AArch64/sve-min-max-pred.ll

; CHECK-NEXT:    ret
   ret <vscale x 2 x i64> %out
 }
 
 
 define <vscale x 2 x i64> @umin_select_i64_multiuse(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, ptr %p) {
 ; CHECK-LABEL: umin_select_i64_multiuse:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    ptrue p1.d
-; CHECK-NEXT:    movprfx z2, z0
-; CHECK-NEXT:    umin z2.d, p1/m, z2.d, z1.d
-; CHECK-NEXT:    umin z0.d, p0/m, z0.d, z1.d
-; CHECK-NEXT:    st1d { z2.d }, p1, [x0]
+; CHECK-NEXT:    umin z1.d, p1/m, z1.d, z0.d
+; CHECK-NEXT:    mov z0.d, p0/m, z1.d
+; CHECK-NEXT:    st1d { z1.d }, p1, [x0]
 ; CHECK-NEXT:    ret
   %sel = call <vscale x 2 x i64> @llvm.umin.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
   store <vscale x 2 x i64> %sel, ptr %p
   %out = select <vscale x 2 x i1> %pg, <vscale x 2 x i64> %sel, <vscale x 2 x i64> %a
   ret <vscale x 2 x i64> %out
 }
 
 define <vscale x 2 x i64> @smin_select_i64_c(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {