[AArch64][SVE] Add basic predicated add/sub patterns

[dmgreen]

Summary

This adds the most basic form of predicated add and sub patterns, selecting from vselect(m, add(x, y), x).

[paulwalker-arm]

I'm tempted to suggest this is better done as a canonicalisation via DAGCombine? Otherwise we then have to start duplicating other instances of these patterns, for example within mla/mls patfrags.

With (add node:$op1, (vselect node:$pred, node:$op2, (SVEDup0))) having one less use of op1 than (vselect node:$pred, (add node:$op1, node:$op2), node:$op1), such a canonicalisation might have other benefits where combines/patterns are guarded by hasOneUse().

[dmgreen]

Hello. Yes, that was actually the plan, but the other way around. There is a function that can canonicalize in the DAG through shouldFoldSelectWithIdentityConstant, to the select(add) form. Instcombine will fold the other way to add(select(..)). See d321f3aa64b4eaedd790dafe974cfdc0517cb22b for example. It is probably simpler to go via that method than dealing with the identity values for all node types (especially fp types). The predicated instructions are not as general in SVE as they are in MVE (MVE doesn't require destructive operands for many operations), but I think it should be better in general so long as there can always use predicated moves. I have patches for that and some other operations like and/or/xor/mul/mla/mls, but they needed some extra tests.

I will put the last part up now, that enables shouldFoldSelectWithIdentityConstant for SVE. There is one case that looks a little worse, but has a pair of selects that could be simplified.

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

402–405

If you shuffle your patches can this use VSelectCommPredOrPassthruPatFrags?

409

As you're previous patch canonicalises to the new pattern, can this old pattern be removed?

[dmgreen]

Thanks. I had this one earlier in the sequence to add the patterns before D149967 enabled shouldFoldSelectWithIdentityConstant, to keep the two separate. D149967 removes the pattern again to use VSelectUnpredOrPassthruPatFrags, so I can fold this into there.

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

 def AArch64bic : PatFrags<(ops node:$op1, node:$op2),
                           [(and node:$op1, (xor node:$op2, (splat_vector (i32 -1)))),
                            (and node:$op1, (xor node:$op2, (splat_vector (i64 -1)))),
                            (and node:$op1, (xor node:$op2, (SVEAllActive))),
                            (AArch64bic_node node:$op1, node:$op2)]>;
 
 def AArch64subr : PatFrag<(ops node:$op1, node:$op2),
                           (sub node:$op2, node:$op1)>;
 def AArch64add_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2),
                              [(int_aarch64_sve_add node:$pred, node:$op1, node:$op2),
+                              (vselect node:$pred, (add node:$op1, node:$op2), node:$op1),
                               (add node:$op1, (vselect node:$pred, node:$op2, (SVEDup0)))]>;
 def AArch64sub_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2),
                              [(int_aarch64_sve_sub node:$pred, node:$op1, node:$op2),
+                              (vselect node:$pred, (sub node:$op1, node:$op2), node:$op1),
                               (sub node:$op1, (vselect node:$pred, node:$op2, (SVEDup0)))]>;
 def AArch64mla_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
                              [(int_aarch64_sve_mla node:$pred, node:$op1, node:$op2, node:$op3),
                               // add(a, select(mask, mul(b, c), splat(0))) -> mla(a, mask, b, c)
                               (add node:$op1, (vselect node:$pred, (AArch64mul_p_oneuse (SVEAllActive), node:$op2, node:$op3), (SVEDup0)))]>;
 // pattern for generating pseudo for MLA_ZPmZZ/MAD_ZPmZZ
 def AArch64mla_p : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),
                             [(add node:$op1, (AArch64mul_p_oneuse node:$pred, node:$op2, node:$op3))]>;
 def AArch64mls_m1 : PatFrags<(ops node:$pred, node:$op1, node:$op2, node:$op3),

llvm/test/CodeGen/AArch64/sve-pred-selectop2.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=aarch64-none-eabi -mattr=+neon,+sve2 -verify-machineinstrs %s -o - | FileCheck %s
 
 define <vscale x 4 x i32> @add_v4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: add_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    add z1.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %a = add <vscale x 4 x i32> %x, %y
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @add_v8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: add_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    add z1.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %a = add <vscale x 8 x i16> %x, %y
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @add_v16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: add_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    add z1.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %a = add <vscale x 16 x i8> %x, %y
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
 }
 
 define <vscale x 4 x i32> @sub_v4i32_x(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: sub_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    sub z1.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %a = sub <vscale x 4 x i32> %x, %y
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @sub_v8i16_x(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: sub_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    sub z1.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %a = sub <vscale x 8 x i16> %x, %y
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @sub_v16i8_x(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: sub_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    sub z1.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %a = sub <vscale x 16 x i8> %x, %y
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
 }
 
entry:
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
 }
 
 define <vscale x 4 x i32> @addqr_v4i32_x(<vscale x 4 x i32> %x, i32 %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: addqr_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    add z1.s, z0.s, z2.s
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    add z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
   %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %a = add <vscale x 4 x i32> %x, %ys
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @addqr_v8i16_x(<vscale x 8 x i16> %x, i16 %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: addqr_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    add z1.h, z0.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    add z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
   %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %a = add <vscale x 8 x i16> %x, %ys
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @addqr_v16i8_x(<vscale x 16 x i8> %x, i8 %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: addqr_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    add z1.b, z0.b, z2.b
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    add z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
   %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %a = add <vscale x 16 x i8> %x, %ys
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
 }
 
 define <vscale x 4 x i32> @subqr_v4i32_x(<vscale x 4 x i32> %x, i32 %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: subqr_v4i32_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    sub z1.s, z0.s, z2.s
-; CHECK-NEXT:    mov z0.s, p0/m, z1.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    sub z0.s, p0/m, z0.s, z1.s
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
   %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %a = sub <vscale x 4 x i32> %x, %ys
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %x
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @subqr_v8i16_x(<vscale x 8 x i16> %x, i16 %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: subqr_v8i16_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    sub z1.h, z0.h, z2.h
-; CHECK-NEXT:    mov z0.h, p0/m, z1.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    sub z0.h, p0/m, z0.h, z1.h
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
   %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %a = sub <vscale x 8 x i16> %x, %ys
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %x
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @subqr_v16i8_x(<vscale x 16 x i8> %x, i8 %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: subqr_v16i8_x:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    sub z1.b, z0.b, z2.b
-; CHECK-NEXT:    mov z0.b, p0/m, z1.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    sub z0.b, p0/m, z0.b, z1.b
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
   %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %a = sub <vscale x 16 x i8> %x, %ys
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
entry:
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %x
   ret <vscale x 16 x i8> %b
 }
 
 define <vscale x 4 x i32> @add_v4i32_y(<vscale x 4 x i32> %x, <vscale x 4 x i32> %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: add_v4i32_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    add z0.s, z0.s, z1.s
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z2.s, #0
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z1.s
+; CHECK-NEXT:    add z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %a = add <vscale x 4 x i32> %x, %y
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %y
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @add_v8i16_y(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: add_v8i16_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    add z0.h, z0.h, z1.h
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z2.h, #0
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z1.h
+; CHECK-NEXT:    add z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %a = add <vscale x 8 x i16> %x, %y
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %y
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @add_v16i8_y(<vscale x 16 x i8> %x, <vscale x 16 x i8> %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: add_v16i8_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    add z0.b, z0.b, z1.b
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z2.b, #0
-; CHECK-NEXT:    sel z0.b, p0, z0.b, z1.b
+; CHECK-NEXT:    add z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %a = add <vscale x 16 x i8> %x, %y
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
   ret <vscale x 16 x i8> %b
 }
 
entry:
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %y
   ret <vscale x 16 x i8> %b
 }
 
 define <vscale x 4 x i32> @addqr_v4i32_y(<vscale x 4 x i32> %x, i32 %y, <vscale x 4 x i32> %n) {
 ; CHECK-LABEL: addqr_v4i32_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    mov z2.s, w0
 ; CHECK-NEXT:    cmpge p0.s, p0/z, z1.s, #0
-; CHECK-NEXT:    add z0.s, z0.s, z2.s
-; CHECK-NEXT:    sel z0.s, p0, z0.s, z2.s
+; CHECK-NEXT:    mov z1.s, w0
+; CHECK-NEXT:    add z1.s, p0/m, z1.s, z0.s
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 4 x i32> %n, zeroinitializer
   %i = insertelement <vscale x 4 x i32> undef, i32 %y, i32 0
   %ys = shufflevector <vscale x 4 x i32> %i, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer
   %a = add <vscale x 4 x i32> %x, %ys
   %b = select <vscale x 4 x i1> %c, <vscale x 4 x i32> %a, <vscale x 4 x i32> %ys
   ret <vscale x 4 x i32> %b
 }
 
 define <vscale x 8 x i16> @addqr_v8i16_y(<vscale x 8 x i16> %x, i16 %y, <vscale x 8 x i16> %n) {
 ; CHECK-LABEL: addqr_v8i16_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    mov z2.h, w0
 ; CHECK-NEXT:    cmpge p0.h, p0/z, z1.h, #0
-; CHECK-NEXT:    add z0.h, z0.h, z2.h
-; CHECK-NEXT:    sel z0.h, p0, z0.h, z2.h
+; CHECK-NEXT:    mov z1.h, w0
+; CHECK-NEXT:    add z1.h, p0/m, z1.h, z0.h
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 8 x i16> %n, zeroinitializer
   %i = insertelement <vscale x 8 x i16> undef, i16 %y, i32 0
   %ys = shufflevector <vscale x 8 x i16> %i, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer
   %a = add <vscale x 8 x i16> %x, %ys
   %b = select <vscale x 8 x i1> %c, <vscale x 8 x i16> %a, <vscale x 8 x i16> %ys
   ret <vscale x 8 x i16> %b
 }
 
 define <vscale x 16 x i8> @addqr_v16i8_y(<vscale x 16 x i8> %x, i8 %y, <vscale x 16 x i8> %n) {
 ; CHECK-LABEL: addqr_v16i8_y:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    mov z2.b, w0
 ; CHECK-NEXT:    cmpge p0.b, p0/z, z1.b, #0
-; CHECK-NEXT:    add z0.b, z0.b, z2.b
-; CHECK-NEXT:    sel z0.b, p0, z0.b, z2.b
+; CHECK-NEXT:    mov z1.b, w0
+; CHECK-NEXT:    add z1.b, p0/m, z1.b, z0.b
+; CHECK-NEXT:    mov z0.d, z1.d
 ; CHECK-NEXT:    ret
 entry:
   %c = icmp sge <vscale x 16 x i8> %n, zeroinitializer
   %i = insertelement <vscale x 16 x i8> undef, i8 %y, i32 0
   %ys = shufflevector <vscale x 16 x i8> %i, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer
   %a = add <vscale x 16 x i8> %x, %ys
   %b = select <vscale x 16 x i1> %c, <vscale x 16 x i8> %a, <vscale x 16 x i8> %ys
   ret <vscale x 16 x i8> %b