[X86][NFC] Correct the instruction names for PUSH16i, PUSH32i

[maksfb]

Since it’s just internal names, it’s better to include NFC/NFCI in the title. clang-format is not happy. Otherwise, LGTM.

[skan]

In D151012#4358279, @maksfb wrote:

Since it’s just internal names, it’s better to include NFC/NFCI in the title. clang-format is not happy. Otherwise, LGTM.

You'd like me to clang-format the code in this patch too?

[maksfb]

In D151012#4358288, @skan wrote:

In D151012#4358279, @maksfb wrote:

Since it’s just internal names, it’s better to include NFC/NFCI in the title. clang-format is not happy. Otherwise, LGTM.

You'd like me to clang-format the code in this patch too?

If it complains only about the existing code, it’s all good.

bolt/lib/Target/X86/X86MCPlusBuilder.cpp

int getPushSize(const MCInst &Inst) const override {
     case X86::PUSHA16:
     case X86::PUSHCS16:
     case X86::PUSHDS16:
     case X86::PUSHES16:
     case X86::PUSHF16:
     case X86::PUSHFS16:
     case X86::PUSHGS16:
     case X86::PUSHSS16:
-    case X86::PUSHi16:
+    case X86::PUSH16i:
       return 2;
     case X86::PUSH32i8:
     case X86::PUSH32r:
     case X86::PUSH32rmm:
     case X86::PUSH32rmr:
     case X86::PUSHA32:
     case X86::PUSHCS32:
     case X86::PUSHDS32:
     case X86::PUSHES32:
     case X86::PUSHF32:
     case X86::PUSHFS32:
     case X86::PUSHGS32:
     case X86::PUSHSS32:
-    case X86::PUSHi32:
+    case X86::PUSH32i:
       return 4;
     case X86::PUSH64i32:
     case X86::PUSH64i8:
     case X86::PUSH64r:
     case X86::PUSH64rmm:
     case X86::PUSH64rmr:
     case X86::PUSHF64:
     case X86::PUSHFS64:
bool replaceRegWithImm(MCInst &Inst, unsigned Register,
     };
 
     InstInfo I;
 
     switch (Inst.getOpcode()) {
     default: {
       switch (getPushSize(Inst)) {
 
-      case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSHi16}}}; break;
-      case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSHi32}}}; break;
+      case 2: I = {2, false, {{CHECK8, X86::PUSH16i8}, {NOCHECK, X86::PUSH16i}}}; break;
+      case 4: I = {4, false, {{CHECK8, X86::PUSH32i8}, {NOCHECK, X86::PUSH32i}}}; break;
       case 8: I = {8, false, {{CHECK8, X86::PUSH64i8},
                               {CHECK32, X86::PUSH64i32},
                               {NOCHECK, Inst.getOpcode()}}}; break;
       default: return false;
       }
       break;
     }
 

llvm/lib/Target/X86/MCTargetDesc/X86InstrRelaxTables.cpp

static const X86InstrRelaxTableEntry InstrRelaxTable[] = {
   // OR
   { X86::OR16mi8,    X86::OR16mi      },
   { X86::OR16ri8,    X86::OR16ri      },
   { X86::OR32mi8,    X86::OR32mi      },
   { X86::OR32ri8,    X86::OR32ri      },
   { X86::OR64mi8,    X86::OR64mi32    },
   { X86::OR64ri8,    X86::OR64ri32    },
   // PUSH
-  { X86::PUSH16i8,   X86::PUSHi16     },
-  { X86::PUSH32i8,   X86::PUSHi32     },
+  { X86::PUSH16i8,   X86::PUSH16i     },
+  { X86::PUSH32i8,   X86::PUSH32i     },
   { X86::PUSH64i8,   X86::PUSH64i32   },
   // SBB
   { X86::SBB16mi8,   X86::SBB16mi     },
   { X86::SBB16ri8,   X86::SBB16ri     },
   { X86::SBB32mi8,   X86::SBB32mi     },
   { X86::SBB32ri8,   X86::SBB32ri     },
   { X86::SBB64mi8,   X86::SBB64mi32   },
   { X86::SBB64ri8,   X86::SBB64ri32   },

llvm/lib/Target/X86/X86CallFrameOptimization.cpp

for (int Idx = (Context.ExpectedDist >> Log2SlotSize) - 1; Idx >= 0; --Idx) {
     case X86::AND16mi:
     case X86::AND32mi:
     case X86::AND64mi32:
     case X86::OR16mi:
     case X86::OR32mi:
     case X86::OR64mi32:
     case X86::MOV32mi:
     case X86::MOV64mi32:
-      PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSHi32;
+      PushOpcode = Is64Bit ? X86::PUSH64i32 : X86::PUSH32i;
       // If the operand is a small (8-bit) immediate, we can use a
       // PUSH instruction with a shorter encoding.
       // Note that isImm() may fail even though this is a MOVmi, because
       // the operand can also be a symbol.
       if (PushOp.isImm()) {
         int64_t Val = PushOp.getImm();
         if (isInt<8>(Val))
           PushOpcode = Is64Bit ? X86::PUSH64i8 : X86::PUSH32i8;

llvm/lib/Target/X86/X86DynAllocaExpander.cpp

 }
 
 static bool isPushPop(const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   case X86::PUSH32i8:
   case X86::PUSH32r:
   case X86::PUSH32rmm:
   case X86::PUSH32rmr:
-  case X86::PUSHi32:
+  case X86::PUSH32i:
   case X86::PUSH64i8:
   case X86::PUSH64r:
   case X86::PUSH64rmm:
   case X86::PUSH64rmr:
   case X86::PUSH64i32:
   case X86::POP32r:
   case X86::POP64r:
     return true;

llvm/lib/Target/X86/X86FrameLowering.cpp

if (Is64Bit) {
 
     BuildMI(allocMBB, DL, TII.get(getMOVriOpcode(IsLP64, StackSize)), Reg10)
         .addImm(StackSize);
     BuildMI(allocMBB, DL,
             TII.get(getMOVriOpcode(IsLP64, X86FI->getArgumentStackSize())),
             Reg11)
         .addImm(X86FI->getArgumentStackSize());
   } else {
-    BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
+    BuildMI(allocMBB, DL, TII.get(X86::PUSH32i))
       .addImm(X86FI->getArgumentStackSize());
-    BuildMI(allocMBB, DL, TII.get(X86::PUSHi32))
+    BuildMI(allocMBB, DL, TII.get(X86::PUSH32i))
       .addImm(StackSize);
   }
 
   // __morestack is in libgcc
   if (Is64Bit && MF.getTarget().getCodeModel() == CodeModel::Large) {
     // Under the large code model, we cannot assume that __morestack lives
     // within 2^31 bytes of the call site, so we cannot use pc-relative
     // addressing. We cannot perform the call via a temporary register,

llvm/lib/Target/X86/X86InstrInfo.cpp

int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
   // in call sequences
   switch (MI.getOpcode()) {
   default:
     return 0;
   case X86::PUSH32i8:
   case X86::PUSH32r:
   case X86::PUSH32rmm:
   case X86::PUSH32rmr:
-  case X86::PUSHi32:
+  case X86::PUSH32i:
     return 4;
   case X86::PUSH64i8:
   case X86::PUSH64r:
   case X86::PUSH64rmm:
   case X86::PUSH64rmr:
   case X86::PUSH64i32:
     return 8;
   }

llvm/lib/Target/X86/X86InstrMisc.td

 def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>,
                  OpSize16;
 def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>,
                  OpSize32, Requires<[Not64BitMode]>;
 } // isCodeGenOnly = 1, ForceDisassemble = 1
 
 def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
                    "push{w}\t$imm", []>, OpSize16;
-def PUSHi16  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
+def PUSH16i  : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
                    "push{w}\t$imm", []>, OpSize16;
 
 def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
                    "push{l}\t$imm", []>, OpSize32,
                    Requires<[Not64BitMode]>;
-def PUSHi32  : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
+def PUSH32i  : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
                    "push{l}\t$imm", []>, OpSize32,
                    Requires<[Not64BitMode]>;
 } // mayStore, SchedRW
 
 let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in {
 def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>,
                  OpSize16;
 def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>,

llvm/lib/Target/X86/X86ScheduleAtom.td

 // Port0 and Port1
 def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> {
   let Latency = 1;
   let ResourceCycles = [1, 1];
 }
 def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r,
                                        POP16rmr, POP32rmr, POP64rmr,
                                        PUSH16r, PUSH32r, PUSH64r,
-                                       PUSHi16, PUSHi32,
+                                       PUSH16i, PUSH32i,
                                        PUSH16rmr, PUSH32rmr, PUSH64rmr,
                                        PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32,
                                        XCH_F)>;
 def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$",
                                           "IRET(16|32|64)?")>;
 
 def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> {
   let Latency = 5;