[RISCV] Avoid RegScavenger::forward in RISCVMakeCompressibleOpt

[foad]

Summary

RegScavenger::backward is preferred because it does not rely on accurate
kill flags.

[craig.topper]

LGTM

llvm/lib/Target/RISCV/RISCVMakeCompressible.cpp

 // compressed register is available, return that compressed register.
 static Register analyzeCompressibleUses(MachineInstr &FirstMI,
                                         RegImmPair RegImm,
                                         SmallVectorImpl<MachineInstr *> &MIs) {
   MachineBasicBlock &MBB = *FirstMI.getParent();
   const TargetRegisterInfo *TRI =
       MBB.getParent()->getSubtarget().getRegisterInfo();
 
-  RegScavenger RS;
-  RS.enterBasicBlock(MBB);
-
   for (MachineBasicBlock::instr_iterator I = FirstMI.getIterator(),
                                          E = MBB.instr_end();
        I != E; ++I) {
     MachineInstr &MI = *I;
 
     // Determine if this is an instruction which would benefit from using the
     // new register.
     RegImmPair CandidateRegImm = getRegImmPairPreventingCompression(MI);
-    if (CandidateRegImm.Reg == RegImm.Reg &&
-        CandidateRegImm.Imm == RegImm.Imm) {
-      // Advance tracking since the value in the new register must be live for
-      // this instruction too.
-      RS.forward(I);
-
+    if (CandidateRegImm.Reg == RegImm.Reg && CandidateRegImm.Imm == RegImm.Imm)
       MIs.push_back(&MI);
-    }
 
     // If RegImm.Reg is modified by this instruction, then we cannot optimize
     // past this instruction. If the register is already compressed, then it may
     // possible to optimize a large offset in the current instruction - this
     // will have been detected by the preceeding call to
     // getRegImmPairPreventingCompression.
     if (MI.modifiesRegister(RegImm.Reg, TRI))
       break;
if (RISCV::GPRRegClass.contains(RegImm.Reg))
     RCToScavenge = &RISCV::GPRCRegClass;
   else if (RISCV::FPR32RegClass.contains(RegImm.Reg))
     RCToScavenge = &RISCV::FPR32CRegClass;
   else if (RISCV::FPR64RegClass.contains(RegImm.Reg))
     RCToScavenge = &RISCV::FPR64CRegClass;
   else
     return RISCV::NoRegister;
 
+  RegScavenger RS;
+  RS.enterBasicBlockEnd(MBB);
+  RS.backward(MIs.back()->getIterator());
   return RS.scavengeRegisterBackwards(*RCToScavenge, FirstMI.getIterator(),
                                       /*RestoreAfter=*/false, /*SPAdj=*/0,
                                       /*AllowSpill=*/false);
 }
 
 // Update uses of the old register in the given instruction to the new register.
 static void updateOperands(MachineInstr &MI, RegImmPair OldRegImm,
                            Register NewReg) {