[mlir][openacc] Cleanup acc.update from old data clause operands

[clementval]

Summary

Since the new data operand operations have been added in D148389 and
adopted on acc.update in D149909, the old clause operands are no longer
needed. This is a first patch to start cleaning the OpenACC operations
with data clause operands.

The LegalizeDataOpForLLVMTranslation will become obsolete when all
operations will be cleaned. For the time being only the appropriate
part are being removed.

processOperands will also receive some updates once all the operands
will be coming from an acc data operand operation.

[clementval]

clang-format

[clementval]

Rebase

flang/lib/Lower/OpenACC.cpp

genACCUpdateOp(Fortran::lower::AbstractConverter &converter,
   // Prepare the operand segment size attribute and the operands value range.
   llvm::SmallVector<mlir::Value> operands;
   llvm::SmallVector<int32_t> operandSegments;
   addOperand(operands, operandSegments, ifCond);
   addOperand(operands, operandSegments, async);
   addOperand(operands, operandSegments, waitDevnum);
   addOperands(operands, operandSegments, waitOperands);
   addOperands(operands, operandSegments, deviceTypeOperands);
-  operandSegments.append({0, 0});
   addOperands(operands, operandSegments, dataClauseOperands);
 
   mlir::acc::UpdateOp updateOp = createSimpleOp<mlir::acc::UpdateOp>(
       builder, currentLocation, operands, operandSegments);
 
   genDataExitOperations<mlir::acc::GetDevicePtrOp, mlir::acc::UpdateHostOp>(
       builder, updateHostOperands, /*structured=*/false, /*implicit=*/false);
 

flang/lib/Optimizer/Transforms/OpenACC/OpenACCDataOperandConversion.cpp

void OpenACCDataOperandConversion::runOnOperation() {
   LowerToLLVMOptions options(context);
   options.useOpaquePointers = useOpaquePointers;
   fir::LLVMTypeConverter converter(
       op.getOperation()->getParentOfType<mlir::ModuleOp>(), true);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::DataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::EnterDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ExitDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ParallelOp>>(converter);
-  patterns.add<LegalizeDataOpForLLVMTranslation<acc::UpdateOp>>(converter);
 
   ConversionTarget target(*context);
   target.addLegalDialect<fir::FIROpsDialect>();
   target.addLegalDialect<LLVM::LLVMDialect>();
   target.addLegalOp<mlir::UnrealizedConversionCastOp>();
 
   auto allDataOperandsAreConverted = [](ValueRange operands) {
     for (Value operand : operands) {
target.addDynamicallyLegalOp<acc::ParallelOp>(
                allDataOperandsAreConverted(op.getNoCreateOperands()) &&
                allDataOperandsAreConverted(op.getPresentOperands()) &&
                allDataOperandsAreConverted(op.getDevicePtrOperands()) &&
                allDataOperandsAreConverted(op.getAttachOperands()) &&
                allDataOperandsAreConverted(op.getGangPrivateOperands()) &&
                allDataOperandsAreConverted(op.getGangFirstPrivateOperands());
       });
 
-  target.addDynamicallyLegalOp<acc::UpdateOp>(
-      [allDataOperandsAreConverted](acc::UpdateOp op) {
-        return allDataOperandsAreConverted(op.getHostOperands()) &&
-               allDataOperandsAreConverted(op.getDeviceOperands());
-      });
-
   if (failed(applyPartialConversion(op, target, std::move(patterns))))
     signalPassFailure();
 }

flang/test/Transforms/OpenACC/convert-data-operands-to-llvmir.fir

 
 // -----
 
 fir.global internal @_QFEa : !fir.array<10xf32> {
   %0 = fir.undefined !fir.array<10xf32>
   fir.has_value %0 : !fir.array<10xf32>
 }
 
-func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
-  %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
-  acc.update device(%0 : !fir.ref<!fir.array<10xf32>>)
-  return
-}
-
-// CHECK-LABEL: func.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
-// CHECK: %[[ADDR:.*]] = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
-// CHECK: %[[CAST:.*]] = builtin.unrealized_conversion_cast %[[ADDR]] : !fir.ref<!fir.array<10xf32>> to !llvm.ptr<array<10 x f32>>
-// CHECK: acc.update device(%[[CAST]] : !llvm.ptr<array<10 x f32>>)
-
-// LLVMIR-LABEL: llvm.func @_QQsub_update() attributes {fir.bindc_name = "a"} {
-// LLVMIR: %[[ADDR:.*]] = llvm.mlir.addressof @_QFEa : !llvm.ptr<array<10 x f32>>
-// LLVMIR: acc.update device(%[[ADDR]] : !llvm.ptr<array<10 x f32>>)
-
-// -----
-
-fir.global internal @_QFEa : !fir.array<10xf32> {
-  %0 = fir.undefined !fir.array<10xf32>
-  fir.has_value %0 : !fir.array<10xf32>
-}
-
 func.func @_QQsub_parallel() attributes {fir.bindc_name = "test"} {
   %0 = fir.address_of(@_QFEa) : !fir.ref<!fir.array<10xf32>>
   %1 = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"}
   acc.parallel copyin(%0: !fir.ref<!fir.array<10xf32>>) {
     acc.loop {
       acc.yield
     }
     acc.yield

mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

def OpenACC_UpdateOp : OpenACC_Op<"update", [AttrSizedOperandSegments]> {
 
   let arguments = (ins Optional<I1>:$ifCond,
                        Optional<IntOrIndex>:$asyncOperand,
                        Optional<IntOrIndex>:$waitDevnum,
                        Variadic<IntOrIndex>:$waitOperands,
                        UnitAttr:$async,
                        UnitAttr:$wait,
                        Variadic<IntOrIndex>:$deviceTypeOperands,
-                       Variadic<AnyType>:$hostOperands,
-                       Variadic<AnyType>:$deviceOperands,
                        Variadic<OpenACC_PointerLikeTypeInterface>:$dataClauseOperands,
                        UnitAttr:$ifPresent);
 
   let extraClassDeclaration = [{
     /// The number of data operands.
     unsigned getNumDataOperands();
 
     /// The i-th data operand passed.
     Value getDataOperand(unsigned i);
   }];
 
   let assemblyFormat = [{
     oilist(
         `if` `(` $ifCond `)`
       | `async` `(` $asyncOperand `:` type($asyncOperand) `)`
       | `wait_devnum` `(` $waitDevnum `:` type($waitDevnum) `)`
       | `device_type` `(` $deviceTypeOperands `:`
           type($deviceTypeOperands) `)`
       | `wait` `(` $waitOperands `:` type($waitOperands) `)`
-      | `host` `(` $hostOperands `:` type($hostOperands) `)`
-      | `device` `(` $deviceOperands `:` type($deviceOperands) `)`
       | `dataOperands` `(` $dataClauseOperands `:` type($dataClauseOperands) `)`
     )
     attr-dict-with-keyword
   }];
 
   let hasCanonicalizer = 1;
   let hasVerifier = 1;
 }

mlir/lib/Conversion/OpenACCToLLVM/OpenACCToLLVM.cpp

 } // namespace
 
 void mlir::populateOpenACCToLLVMConversionPatterns(
     LLVMTypeConverter &converter, RewritePatternSet &patterns) {
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::DataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::EnterDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ExitDataOp>>(converter);
   patterns.add<LegalizeDataOpForLLVMTranslation<acc::ParallelOp>>(converter);
-  patterns.add<LegalizeDataOpForLLVMTranslation<acc::UpdateOp>>(converter);
 }
 
 namespace {
 struct ConvertOpenACCToLLVMPass
     : public impl::ConvertOpenACCToLLVMPassBase<ConvertOpenACCToLLVMPass> {
   using Base::Base;
 
   void runOnOperation() override;
target.addDynamicallyLegalOp<acc::ParallelOp>(
                allDataOperandsAreConverted(op.getNoCreateOperands()) &&
                allDataOperandsAreConverted(op.getPresentOperands()) &&
                allDataOperandsAreConverted(op.getDevicePtrOperands()) &&
                allDataOperandsAreConverted(op.getAttachOperands()) &&
                allDataOperandsAreConverted(op.getGangPrivateOperands()) &&
                allDataOperandsAreConverted(op.getGangFirstPrivateOperands());
       });
 
-  target.addDynamicallyLegalOp<acc::UpdateOp>(
-      [allDataOperandsAreConverted](acc::UpdateOp op) {
-        return allDataOperandsAreConverted(op.getHostOperands()) &&
-               allDataOperandsAreConverted(op.getDeviceOperands());
-      });
-
   if (failed(applyPartialConversion(op, target, std::move(patterns))))
     signalPassFailure();
 }

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

 }
 
 //===----------------------------------------------------------------------===//
 // UpdateOp
 //===----------------------------------------------------------------------===//
 
 LogicalResult acc::UpdateOp::verify() {
   // At least one of host or device should have a value.
-  if (getHostOperands().empty() && getDeviceOperands().empty() &&
-      getDataClauseOperands().empty())
-    return emitError(
-        "at least one value must be present in hostOperands or deviceOperands");
+  if (getDataClauseOperands().empty())
+    return emitError("at least one value must be present in dataOperands");
 
   // The async attribute represent the async clause without value. Therefore the
   // attribute and operand cannot appear at the same time.
   if (getAsyncOperand() && getAsync())
     return emitError("async attribute cannot appear with asyncOperand");
 
   // The wait attribute represent the wait clause without values. Therefore the
   // attribute and operands cannot appear at the same time.
   if (!getWaitOperands().empty() && getWait())
     return emitError("wait attribute cannot appear with waitOperands");
 
   if (getWaitDevnum() && getWaitOperands().empty())
     return emitError("wait_devnum cannot appear without waitOperands");
 
   for (mlir::Value operand : getDataClauseOperands())
     if (!mlir::isa<acc::UpdateDeviceOp, acc::UpdateHostOp, acc::GetDevicePtrOp>(
             operand.getDefiningOp()))
       return emitError("expect data entry/exit operation or acc.getdeviceptr "
                        "as defining op");
 
   return success();
 }
 
 unsigned UpdateOp::getNumDataOperands() {
-  return getHostOperands().size() + getDeviceOperands().size() +
-         getDataClauseOperands().size();
+  return getDataClauseOperands().size();
 }
 
 Value UpdateOp::getDataOperand(unsigned i) {
   unsigned numOptional = getAsyncOperand() ? 1 : 0;
   numOptional += getWaitDevnum() ? 1 : 0;
   numOptional += getIfCond() ? 1 : 0;
   return getOperand(getWaitOperands().size() + getDeviceTypeOperands().size() +
                     numOptional + i);

mlir/lib/Target/LLVMIR/Dialect/OpenACC/OpenACCToLLVMIRTranslation.cpp

 processDataOperands(llvm::IRBuilderBase &builder,
                     LLVM::ModuleTranslation &moduleTranslation,
                     acc::UpdateOp op, SmallVector<uint64_t> &flags,
                     SmallVectorImpl<llvm::Constant *> &names,
                     struct OpenACCIRBuilder::MapperAllocas &mapperAllocas) {
   unsigned index = 0;
 
   // Host operands are handled as `from` call.
-  if (failed(processOperands(builder, moduleTranslation, op,
-                             op.getHostOperands(), op.getNumDataOperands(),
+  // Device operands are handled as `to` call.
+  llvm::SmallVector<mlir::Value> from, to;
+  for (mlir::Value dataOp : op.getDataClauseOperands()) {
+    if (auto getDevicePtrOp = mlir::dyn_cast_or_null<acc::GetDevicePtrOp>(
+            dataOp.getDefiningOp())) {
+      from.push_back(getDevicePtrOp.getVarPtr());
+    } else if (auto updateDeviceOp =
+                   mlir::dyn_cast_or_null<acc::UpdateDeviceOp>(
+                       dataOp.getDefiningOp())) {
+      to.push_back(updateDeviceOp.getVarPtr());
+    }
+  }
+
+  if (failed(processOperands(builder, moduleTranslation, op, from, from.size(),
                              kHostCopyoutFlag, flags, names, index,
                              mapperAllocas)))
     return failure();
 
-  // Device operands are handled as `to` call.
-  if (failed(processOperands(builder, moduleTranslation, op,
-                             op.getDeviceOperands(), op.getNumDataOperands(),
+  if (failed(processOperands(builder, moduleTranslation, op, to, to.size(),
                              kDeviceCopyinFlag, flags, names, index,
                              mapperAllocas)))
     return failure();
-
   return success();
 }
 
 //===----------------------------------------------------------------------===//
 // Conversion functions
 //===----------------------------------------------------------------------===//
 
 /// Converts an OpenACC data operation into LLVM IR.
return llvm::TypeSwitch<Operation *, LogicalResult>(op)
       })
       .Case<acc::TerminatorOp, acc::YieldOp>([](auto op) {
         // `yield` and `terminator` can be just omitted. The block structure was
         // created in the function that handles their parent operation.
         assert(op->getNumOperands() == 0 &&
                "unexpected OpenACC terminator with operands");
         return success();
       })
+      .Case([&](acc::UpdateDeviceOp) {
+        // NOP
+        return success();
+      })
       .Default([&](Operation *op) {
         return op->emitError("unsupported OpenACC operation: ")
                << op->getName();
       });
 }
 
 void mlir::registerOpenACCDialectTranslation(DialectRegistry &registry) {
   registry.insert<acc::OpenACCDialect>();

mlir/test/Conversion/OpenACCToLLVM/convert-data-operands-to-llvmir.mlir

func.func @testexitdataop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
   acc.exit_data if(%ifCond) copyout(%b : memref<10xf32>) delete(%a : memref<10xf32>)
   return
 }
 
 // CHECK: acc.exit_data if(%{{.*}}) copyout(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) delete(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>)
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
-  acc.update host(%b : memref<10xf32>) device(%a : memref<10xf32>)
-  return
-}
-
-// CHECK: acc.update host(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) device(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>)
-
-// -----
-
-func.func @testupdateop(%a: !llvm.ptr, %b: memref<10xf32>) -> () {
-  acc.update host(%b : memref<10xf32>) device(%a : !llvm.ptr)
-  return
-}
-
-// CHECK: acc.update host(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) device(%{{.*}} : !llvm.ptr)
-
-// -----
-
-func.func @testupdateop(%a: memref<10xi64>, %b: memref<10xf32>) -> () {
-  acc.update host(%b : memref<10xf32>) device(%a : memref<10xi64>) attributes {async}
-  return
-}
-
-// CHECK: acc.update host(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) device(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) attributes {async}
-
-// -----
-
-func.func @testupdateop(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
-  %ifCond = arith.constant true
-  acc.update if(%ifCond) host(%b : memref<10xf32>) device(%a : memref<10xf32>)
-  return
-}
-
-// CHECK: acc.update if(%{{.*}}) host(%{{.*}} : !llvm.struct<"openacc_data", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>) device(%{{.*}} : !llvm.struct<"openacc_data.1", (struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)>, ptr, i64)>)
-
-// -----
-
 func.func @testdataregion(%a: memref<10xf32>, %b: memref<10xf32>) -> () {
   acc.data copy(%b : memref<10xf32>) copyout(%a : memref<10xf32>) {
     acc.parallel {
       acc.yield
     }
     acc.terminator
   }
   return

mlir/test/Conversion/OpenACCToSCF/convert-openacc-to-scf.mlir

 
 // CHECK:      func @testexitdataop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
 // CHECK:        scf.if [[IFCOND]] {
 // CHECK-NEXT:     acc.exit_data delete(%{{.*}} : memref<10xf32>)
 // CHECK-NEXT:   }
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>, %ifCond: i1) -> () {
-  acc.update if(%ifCond) host(%a: memref<10xf32>)
+func.func @testupdateop(%a: memref<f32>, %ifCond: i1) -> () {
+  %0 = acc.update_device varPtr(%a : memref<f32>) -> memref<f32>
+  acc.update if(%ifCond) dataOperands(%0 : memref<f32>)
   return
 }
 
-// CHECK:      func @testupdateop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
+// CHECK:      func @testupdateop(%{{.*}}: memref<f32>, [[IFCOND:%.*]]: i1)
 // CHECK:        scf.if [[IFCOND]] {
-// CHECK-NEXT:     acc.update host(%{{.*}} : memref<10xf32>)
+// CHECK:          acc.update dataOperands(%{{.*}} : memref<f32>)
 // CHECK-NEXT:   }
 
 // -----
 
-func.func @update_true(%arg0: memref<10xf32, #spirv.storage_class<StorageBuffer>>) {
+func.func @update_true(%arg0: memref<f32>) {
   %true = arith.constant true
-  acc.update if(%true) host(%arg0 : memref<10xf32, #spirv.storage_class<StorageBuffer>>)
+  %0 = acc.update_device varPtr(%arg0 : memref<f32>) -> memref<f32>
+  acc.update if(%true) dataOperands(%0 : memref<f32>)
   return
 }
 
 // CHECK-LABEL: func.func @update_true
-// CHECK-NOT:if
-// CHECK:acc.update host
+// CHECK-NOT:     if
+// CHECK:         acc.update dataOperands
 
 // -----
 
-func.func @update_false(%arg0: memref<10xf32, #spirv.storage_class<StorageBuffer>>) {
+func.func @update_false(%arg0: memref<f32>) {
   %false = arith.constant false
-  acc.update if(%false) host(%arg0 : memref<10xf32, #spirv.storage_class<StorageBuffer>>)
+  %0 = acc.update_device varPtr(%arg0 : memref<f32>) -> memref<f32>
+  acc.update if(%false) dataOperands(%0 : memref<f32>)
   return
 }
 
 // CHECK-LABEL: func.func @update_false
-// CHECK-NOT:acc.update
+// CHECK-NOT:     acc.update dataOperands
 
 // -----
 
 func.func @enter_data_true(%d1 : memref<10xf32>) {
   %true = arith.constant true
   acc.enter_data if(%true) create(%d1 : memref<10xf32>) attributes {async}
   return
 }
 
 // CHECK-LABEL: func.func @enter_data_true
-// CHECK-NOT:if
-// CHECK:acc.enter_data create
+// CHECK-NOT:     if
+// CHECK:           acc.enter_data create
 
 // -----
 
 func.func @enter_data_false(%d1 : memref<10xf32>) {
   %false = arith.constant false
   acc.enter_data if(%false) create(%d1 : memref<10xf32>) attributes {async}
   return
 }

mlir/test/Dialect/OpenACC/canonicalize.mlir

func.func @testexitdataop(%a: memref<10xf32>) -> () {
   return
 }
 
 // CHECK: func @testexitdataop
 // CHECK-NOT: acc.exit_data
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>) -> () {
+func.func @testupdateop(%a: memref<f32>) -> () {
+  %0 = acc.getdeviceptr varPtr(%a : memref<f32>) -> memref<f32>
+  acc.update_host accPtr(%0 : memref<f32>) to varPtr(%a : memref<f32>)
   %ifCond = arith.constant true
-  acc.update if(%ifCond) host(%a: memref<10xf32>)
+  acc.update if(%ifCond) dataOperands(%0: memref<f32>)
   return
 }
 
-// CHECK: acc.update host(%{{.*}} : memref<10xf32>)
+// CHECK: acc.update dataOperands(%{{.*}} : memref<f32>)
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>) -> () {
+func.func @testupdateop(%a: memref<f32>) -> () {
+  %0 = acc.getdeviceptr varPtr(%a : memref<f32>) -> memref<f32>
+  acc.update_host accPtr(%0 : memref<f32>) to varPtr(%a : memref<f32>)
   %ifCond = arith.constant false
-  acc.update if(%ifCond) host(%a: memref<10xf32>)
+  acc.update if(%ifCond) dataOperands(%0: memref<f32>)
   return
 }
 
 // CHECK: func @testupdateop
-// CHECK-NOT: acc.update
+// CHECK-NOT: acc.update{{.$}}
 
 // -----
 
 func.func @testenterdataop(%a: memref<10xf32>, %ifCond: i1) -> () {
   acc.enter_data if(%ifCond) create(%a: memref<10xf32>)
   return
 }
 
 // CHECK:  func @testenterdataop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
 // CHECK:    acc.enter_data if(%{{.*}}) create(%{{.*}} : memref<10xf32>)
 
 // -----
 
 func.func @testexitdataop(%a: memref<10xf32>, %ifCond: i1) -> () {
   acc.exit_data if(%ifCond) delete(%a: memref<10xf32>)
   return
 }
 
 // CHECK: func @testexitdataop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
 // CHECK:   acc.exit_data if(%{{.*}}) delete(%{{.*}} : memref<10xf32>)
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>, %ifCond: i1) -> () {
-  acc.update if(%ifCond) host(%a: memref<10xf32>)
+func.func @testupdateop(%a: memref<f32>, %ifCond: i1) -> () {
+  %0 = acc.getdeviceptr varPtr(%a : memref<f32>) -> memref<f32>
+  acc.update_host accPtr(%0 : memref<f32>) to varPtr(%a : memref<f32>)
+  acc.update if(%ifCond) dataOperands(%0: memref<f32>)
   return
 }
 
-// CHECK:  func @testupdateop(%{{.*}}: memref<10xf32>, [[IFCOND:%.*]]: i1)
-// CHECK:    acc.update if(%{{.*}}) host(%{{.*}} : memref<10xf32>)
+// CHECK:  func @testupdateop(%{{.*}}: memref<f32>, [[IFCOND:%.*]]: i1)
+// CHECK:    acc.update if(%{{.*}}) dataOperands(%{{.*}} : memref<f32>)

mlir/test/Dialect/OpenACC/invalid.mlir

 %value = memref.alloc() : memref<10xf32>
 // expected-error@+1 {{expect data entry/exit operation or acc.getdeviceptr as defining op}}
 acc.data dataOperands(%value : memref<10xf32>) {
   acc.yield
 }
 
 // -----
 
-// expected-error@+1 {{at least one value must be present in hostOperands or deviceOperands}}
+// expected-error@+1 {{at least one value must be present in dataOperands}}
 acc.update
 
 // -----
 
 %cst = arith.constant 1 : index
-%value = memref.alloc() : memref<10xf32>
+%value = memref.alloc() : memref<f32>
+%0 = acc.update_device varPtr(%value : memref<f32>) -> memref<f32>
 // expected-error@+1 {{wait_devnum cannot appear without waitOperands}}
-acc.update wait_devnum(%cst: index) host(%value: memref<10xf32>)
+acc.update wait_devnum(%cst: index) dataOperands(%0: memref<f32>)
 
 // -----
 
 %cst = arith.constant 1 : index
-%value = memref.alloc() : memref<10xf32>
+%value = memref.alloc() : memref<f32>
+%0 = acc.update_device varPtr(%value : memref<f32>) -> memref<f32>
 // expected-error@+1 {{async attribute cannot appear with asyncOperand}}
-acc.update async(%cst: index) host(%value: memref<10xf32>) attributes {async}
+acc.update async(%cst: index) dataOperands(%0 : memref<f32>) attributes {async}
 
 // -----
 
 %cst = arith.constant 1 : index
-%value = memref.alloc() : memref<10xf32>
+%value = memref.alloc() : memref<f32>
+%0 = acc.update_device varPtr(%value : memref<f32>) -> memref<f32>
 // expected-error@+1 {{wait attribute cannot appear with waitOperands}}
-acc.update wait(%cst: index) host(%value: memref<10xf32>) attributes {wait}
+acc.update wait(%cst: index) dataOperands(%0: memref<f32>) attributes {wait}
 
 // -----
 
 %cst = arith.constant 1 : index
 // expected-error@+1 {{wait_devnum cannot appear without waitOperands}}
 acc.wait wait_devnum(%cst: index)
 
 // -----

mlir/test/Dialect/OpenACC/ops.mlir

 // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
 // CHECK:      acc.data present([[ARGA]] : memref<10xf32>) {
 // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue present>}
 // CHECK:      acc.data {
 // CHECK-NEXT: } attributes {defaultAttr = #acc<defaultvalue none>}
 
 // -----
 
-func.func @testupdateop(%a: memref<10xf32>, %b: memref<10xf32>, %c: memref<10x10xf32>) -> () {
+func.func @testupdateop(%a: memref<f32>, %b: memref<f32>, %c: memref<f32>) -> () {
   %i64Value = arith.constant 1 : i64
   %i32Value = arith.constant 1 : i32
   %idxValue = arith.constant 1 : index
   %ifCond = arith.constant true
-  acc.update async(%i64Value: i64) host(%a: memref<10xf32>)
-  acc.update async(%i32Value: i32) host(%a: memref<10xf32>)
-  acc.update async(%i32Value: i32) host(%a: memref<10xf32>)
-  acc.update async(%idxValue: index) host(%a: memref<10xf32>)
-  acc.update wait_devnum(%i64Value: i64) wait(%i32Value, %idxValue : i32, index) host(%a: memref<10xf32>)
-  acc.update if(%ifCond) host(%a: memref<10xf32>)
-  acc.update device_type(%i32Value : i32) host(%a: memref<10xf32>)
-  acc.update host(%a: memref<10xf32>) device(%b, %c : memref<10xf32>, memref<10x10xf32>)
-  acc.update host(%a: memref<10xf32>) device(%b, %c : memref<10xf32>, memref<10x10xf32>) attributes {async}
-  acc.update host(%a: memref<10xf32>) device(%b, %c : memref<10xf32>, memref<10x10xf32>) attributes {wait}
-  acc.update host(%a: memref<10xf32>) device(%b, %c : memref<10xf32>, memref<10x10xf32>) attributes {ifPresent}
+  %0 = acc.update_device varPtr(%a : memref<f32>) -> memref<f32>
+  %1 = acc.update_device varPtr(%b : memref<f32>) -> memref<f32>
+  %2 = acc.update_device varPtr(%c : memref<f32>) -> memref<f32>
+  
+  acc.update async(%i64Value: i64) dataOperands(%0: memref<f32>)
+  acc.update async(%i32Value: i32) dataOperands(%0: memref<f32>)
+  acc.update async(%i32Value: i32) dataOperands(%0: memref<f32>)
+  acc.update async(%idxValue: index) dataOperands(%0: memref<f32>)
+  acc.update wait_devnum(%i64Value: i64) wait(%i32Value, %idxValue : i32, index) dataOperands(%0: memref<f32>)
+  acc.update if(%ifCond) dataOperands(%0: memref<f32>)
+  acc.update device_type(%i32Value : i32) dataOperands(%0: memref<f32>)
+  acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>)
+  acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>) attributes {async}
+  acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>) attributes {wait}
+  acc.update dataOperands(%0, %1, %2 : memref<f32>, memref<f32>, memref<f32>) attributes {ifPresent}
   return
 }
 
-// CHECK: func @testupdateop([[ARGA:%.*]]: memref<10xf32>, [[ARGB:%.*]]: memref<10xf32>, [[ARGC:%.*]]: memref<10x10xf32>) {
+// CHECK: func @testupdateop([[ARGA:%.*]]: memref<f32>, [[ARGB:%.*]]: memref<f32>, [[ARGC:%.*]]: memref<f32>) {
 // CHECK:   [[I64VALUE:%.*]] = arith.constant 1 : i64
 // CHECK:   [[I32VALUE:%.*]] = arith.constant 1 : i32
 // CHECK:   [[IDXVALUE:%.*]] = arith.constant 1 : index
 // CHECK:   [[IFCOND:%.*]] = arith.constant true
-// CHECK:   acc.update async([[I64VALUE]] : i64) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update async([[I32VALUE]] : i32) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update async([[I32VALUE]] : i32) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update async([[IDXVALUE]] : index) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update wait_devnum([[I64VALUE]] : i64) wait([[I32VALUE]], [[IDXVALUE]] : i32, index) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update if([[IFCOND]]) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update device_type([[I32VALUE]] : i32) host([[ARGA]] : memref<10xf32>)
-// CHECK:   acc.update host([[ARGA]] : memref<10xf32>) device([[ARGB]], [[ARGC]] : memref<10xf32>, memref<10x10xf32>)
-// CHECK:   acc.update host([[ARGA]] : memref<10xf32>) device([[ARGB]], [[ARGC]] : memref<10xf32>, memref<10x10xf32>) attributes {async}
-// CHECK:   acc.update host([[ARGA]] : memref<10xf32>) device([[ARGB]], [[ARGC]] : memref<10xf32>, memref<10x10xf32>) attributes {wait}
-// CHECK:   acc.update host([[ARGA]] : memref<10xf32>) device([[ARGB]], [[ARGC]] : memref<10xf32>, memref<10x10xf32>) attributes {ifPresent}
+// CHECK:   acc.update async([[I64VALUE]] : i64) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update async([[I32VALUE]] : i32) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update async([[I32VALUE]] : i32) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update async([[IDXVALUE]] : index) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update wait_devnum([[I64VALUE]] : i64) wait([[I32VALUE]], [[IDXVALUE]] : i32, index) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update if([[IFCOND]]) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update device_type([[I32VALUE]] : i32) dataOperands(%{{.*}} : memref<f32>)
+// CHECK:   acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>)
+// CHECK:   acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>) attributes {async}
+// CHECK:   acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>) attributes {wait}
+// CHECK:   acc.update dataOperands(%{{.*}}, %{{.*}}, %{{.*}} : memref<f32>, memref<f32>, memref<f32>) attributes {ifPresent}
 
 // -----
 
 %i64Value = arith.constant 1 : i64
 %i32Value = arith.constant 1 : i32
 %idxValue = arith.constant 1 : index
 %ifCond = arith.constant true
 acc.wait

mlir/test/Target/LLVMIR/openacc-llvm.mlir

 // CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
 
 // CHECK: call void @__tgt_target_data_end_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
 
 // CHECK: declare void @__tgt_target_data_end_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) #0
 
 // -----
 
-llvm.func @testupdateop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>) {
-  %0 = llvm.mlir.constant(10 : index) : i64
-  %1 = llvm.mlir.null : !llvm.ptr<f32>
-  %2 = llvm.getelementptr %1[%0] : (!llvm.ptr<f32>, i64) -> !llvm.ptr<f32>
-  %3 = llvm.ptrtoint %2 : !llvm.ptr<f32> to i64
-  %4 = llvm.extractvalue %arg0[1] : !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>
-  %5 = llvm.mlir.undef : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
-  %6 = llvm.insertvalue %arg0, %5[0] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
-  %7 = llvm.insertvalue %4, %6[1] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
-  %8 = llvm.insertvalue %3, %7[2] : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>
-  acc.update host(%8 : !llvm.struct<"openacc_data", (struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, ptr<f32>, i64)>) device(%arg1 : !llvm.ptr<f32>)
+llvm.func @testupdateop(%arg1: !llvm.ptr<f32>) {
+  %0 = acc.update_device varPtr(%arg1 : !llvm.ptr<f32>) -> !llvm.ptr<f32>
+  acc.update dataOperands(%0 : !llvm.ptr<f32>)
   llvm.return
 }
 
 // CHECK: %struct.ident_t = type { i32, i32, i32, i32, ptr }
 
 // CHECK: [[LOCSTR:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};testupdateop;{{[0-9]*}};{{[0-9]*}};;\00", align 1
 // CHECK: [[LOCGLOBAL:@.*]] = private unnamed_addr constant %struct.ident_t { i32 0, i32 2, i32 0, i32 {{[0-9]*}}, ptr [[LOCSTR]] }, align 8
 // CHECK: [[MAPNAME1:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
-// CHECK: [[MAPNAME2:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i8] c";{{.*}};unknown;{{[0-9]*}};{{[0-9]*}};;\00", align 1
-// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 2, i64 1]
-// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]], ptr [[MAPNAME2]]]
+// CHECK: [[MAPTYPES:@.*]] = private unnamed_addr constant [{{[0-9]*}} x i64] [i64 1]
+// CHECK: [[MAPNAMES:@.*]] = private constant [{{[0-9]*}} x ptr] [ptr [[MAPNAME1]]]
 
-// CHECK: define void @testupdateop({ ptr, ptr, i64, [1 x i64], [1 x i64] } %{{.*}}, ptr [[SIMPLEPTR:%.*]])
-// CHECK: [[ARGBASE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
-// CHECK: [[ARG_ALLOCA:%.*]] = alloca [{{[0-9]*}} x ptr], align 8
-// CHECK: [[SIZE_ALLOCA:%.*]] = alloca [{{[0-9]*}} x i64], align 8
-
-// CHECK: [[ARGBASE:%.*]] = extractvalue %openacc_data %{{.*}}, 0
-// CHECK: [[ARG:%.*]] = extractvalue %openacc_data %{{.*}}, 1
-// CHECK: [[ARGSIZE:%.*]] = extractvalue %openacc_data %{{.*}}, 2
-// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
-// CHECK: store { ptr, ptr, i64, [1 x i64], [1 x i64] } [[ARGBASE]], ptr [[ARGBASEGEP]], align 8
-// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
-// CHECK: store ptr [[ARG]], ptr [[ARGGEP]], align 8
-// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
-// CHECK: store i64 [[ARGSIZE]], ptr [[SIZEGEP]], align 4
-
-// CHECK: [[ARGBASEGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 1
-// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGBASEGEP]], align 8
-// CHECK: [[ARGGEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 1
-// CHECK: store ptr [[SIMPLEPTR]], ptr [[ARGGEP]], align 8
-// CHECK: [[SIZEGEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 1
-// CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr [[SIZEGEP]], align 4
-
-// CHECK: [[ARGBASE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARGBASE_ALLOCA]], i32 0, i32 0
-// CHECK: [[ARG_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x ptr], ptr [[ARG_ALLOCA]], i32 0, i32 0
-// CHECK: [[SIZE_ALLOCA_GEP:%.*]] = getelementptr inbounds [2 x i64], ptr [[SIZE_ALLOCA]], i32 0, i32 0
+// CHECK: define void @testupdateop(ptr %[[SIMPLEPTR:.*]])
+// CHECK: %[[OFFLOAD_BASEPTRS:.*]] = alloca [{{[0-9]*}} x ptr]
+// CHECK: %[[OFFLOAD_PTRS:.*]] = alloca [{{[0-9]*}} x ptr]
+// CHECK: %[[OFFLOAS_SIZES:.*]] = alloca [{{[0-9]*}} x i64]
+
+// CHECK: %[[BASEGEP:.*]] = getelementptr inbounds [1 x ptr], ptr %[[OFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK: store ptr %[[SIMPLEPTR]], ptr %[[BASEGEP]]
+// CHECK: %[[ARGGEP:.*]] = getelementptr inbounds [1 x ptr], ptr %[[OFFLOAD_PTRS]], i32 0, i32 0
+// CHECK: store ptr %[[SIMPLEPTR]], ptr %[[ARGGEP]]
+// CHECK: %[[SIZEGEP:.*]] = getelementptr inbounds [1 x i64], ptr %[[OFFLOAS_SIZES]], i32 0, i32 0
+// CHECK: store i64 ptrtoint (ptr getelementptr (ptr, ptr null, i32 1) to i64), ptr %[[SIZEGEP]]
+
+// CHECK: %[[OFFLOAD_BASEPTRS_GEP:.*]] = getelementptr inbounds [1 x ptr], ptr %[[OFFLOAD_BASEPTRS]], i32 0, i32 0
+// CHECK: %[[OFFLOAD_PTRS_GEP:.*]] = getelementptr inbounds [1 x ptr], ptr %[[OFFLOAD_PTRS]], i32 0, i32 0
+// CHECK: %[[OFFLOAS_SIZES_GEP:.*]] = getelementptr inbounds [1 x i64], ptr %[[OFFLOAS_SIZES]], i32 0, i32 0
 
-// CHECK: call void @__tgt_target_data_update_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 2, ptr [[ARGBASE_ALLOCA_GEP]], ptr [[ARG_ALLOCA_GEP]], ptr [[SIZE_ALLOCA_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
+// CHECK: call void @__tgt_target_data_update_mapper(ptr [[LOCGLOBAL]], i64 -1, i32 1, ptr %[[OFFLOAD_BASEPTRS_GEP]], ptr %[[OFFLOAD_PTRS_GEP]], ptr %[[OFFLOAS_SIZES_GEP]], ptr [[MAPTYPES]], ptr [[MAPNAMES]], ptr null)
 
 // CHECK: declare void @__tgt_target_data_update_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) #0
 
 // -----
 
 llvm.func @testdataop(%arg0: !llvm.struct<(ptr<f32>, ptr<f32>, i64, array<1 x i64>, array<1 x i64>)>, %arg1: !llvm.ptr<f32>, %arg2: !llvm.ptr<i32>) {
   %0 = llvm.mlir.constant(10 : index) : i64
   %1 = llvm.mlir.null : !llvm.ptr<f32>